Preliminary PLL502-67 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO FEATURES • • VDD 1 14 SEL0^ XIN 2 13 CLK4 XOUT 3 12 CLK3 SEL2^ 4 11 VDD SEL1^ 5 10 CLK2 VCON 6 9 CLK1 GND 7 8 GND DESCRIPTIONS PLL 502-67 • • • • • • • Selectable 12.5MHz to 200MHz range. Low phase noise output (@ 10kHz frequency offset, -140dBc/Hz for 17.664MHz, -132dBc/Hz for 35.328MHz, -125dBc/Hz for 155.52MHz). 4 CMOS outputs (in phase). 12 to 25MHz crystal input. No external load capacitor or varicap required. Wide pull range (+/-190 ppm) Selectable 1/2 to 8x frequency multiplier. 3.3V operation. Available in 14-SOP. PIN CONFIGURATION (Top View) ^: Internal pull-up The PLL502-67 is high performance and low phase noise VCXO IC chip. It provides phase noise performance as low as –140dBc at 1kHz offset (at 17.664MHz) and –125dBc at 1kHz offset at 155.52MHz by multiplying the input crystal frequency up to 8x. The wide pull range (+/- 190 ppm) and very low jitter makes this chip ideal for a wide range of applications, from xDSL to SONET/SDH and FEC. The chip accepts a low cost fundamental parallel resonant mode crystal from 12 to 25MHz. BLOCK DIAGRAM SEL CLK4 VCON XIN XOUT Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) CLK3 CLK2 CLK1 PLL by-pass PLL502-67 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/20/03 Page 1 Preliminary PLL502-67 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected Multiplier Reserved Reserved Reserved Fin x 2 Fin / 2 Fin x 4 Fin x 8 No multiplication Note: Internal pull-ups default SEL2, SEL1 and SEL0 to ‘1’ if not connected PIN DESCRIPTIONS Name Pin number Type Description XIN 2 I Crystal in connector. XOUT 3 I Crystal out connector. VCON 6 I Frequency control input (0.3V to 3.0V) GND 7,8 P GND. CLK1, CLK2 9,10 O Output signal CLK3, CLK4 12,13 O Output signal. SEL2 4 I SEL1 5 I SEL0 14 I VDD 1, 11 P Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V VDD. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/20/03 Page 2 Preliminary PLL502-67 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 7 V Input Voltage, dc VI V SS - 0.5 V DD + 0.5 V Output Voltage, dc VO V SS - 0.5 V DD + 0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C 260 °C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. F XIN Parallel Fundamental Mode 12 C L (xtal) At VCON = 1.65V TYP. MAX. UNITS 25 MHz 9 pF C 0 /C 1 (xtal) AT cut 250 - RE AT cut 30 Ω Note: Crystal Loading rating: 9pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/20/03 Page 3 PLL502-67 Preliminary 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL VCXO Stabilization Time * T VCXOSTB CONDITIONS MIN. From power valid TYP. MAX. 10 UNITS ms VCXO Tuning Range F XIN = 12 - 25 MHz; XTAL C 0 /C 1 < 250 380 ppm CLK output pullability 0V ≤ VCON ≤ 3.3V ±190 ppm Linearity 5 VCXO Tuning Characteristic 10 % 150 VCON input impedance 2000 kΩ 25 kHz 0V ≤ VCON ≤ 3.3V, -3dB VCON modulation BW ppm/V Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD CONDITIONS 4 outputs loaded at 18pF MIN. TYP. MAX. Fout = 17.664MHz 15 30 Fout = 35.328MHz 42 60 Fout < 141MHz 71 80 3.13 mA 3.47 ±50 Short Circuit Current UNITS V mA 5. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle MIN. TYP. 12 0.8V ~ 2.0V with 10 pF load 2 2.0V ~ 0.8V with 10 pF load 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 25 MHz 5 1.5 3.0V ~ 0.3V with 15pF load Short Circuit Current UNITS 1.5 0.3V ~ 3.0V with 15 pF load Measured @ 1.4V MAX. 45 2 5 50 55 ±50 ns % mA Rev 02/20/03 Page 4 Preliminary PLL502-67 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO 6. Jitter specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. 17.664MHz 2.5 5 35.328MHz 4 7 UNITS Period jitter RMS With capacitive decoupling between VDD and GND. 155.52MHz 4.5 9 Peak to Peak jitter With capacitive decoupling between VDD and GND. Over 10,000 cycles. 155.52MHz 30 60 ps Integrated jitter RMS Integrated 12 kHz to 20 MHz 155.52MHz 2.5 4 ps ps 7. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz 17.664MHz -60 -90 -112 -140 -150 70.656MHz -60 -90 -112 -127 -125 155.52MHz -60 -90 -112 -125 -123 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/20/03 Page 5 Preliminary PLL502-67 4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO PACKAGE INFORMATION 14 PIN Narrow SOIC ( mm ) SOIC E Symbol Min. Max. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 8.58 8.69 E 3.85 3.97 H 5.80 6.20 L 0.40 1.27 e H D A A1 C 1.27 BSC L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL502-67 S C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 02/20/03 Page 6