Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
DESCRIPTION
PT6553 is an LCD Driver IC providing key scan circuitry which can accept up to a maximum of 30 keys,
thereby, reducing printed circuit board wiring. It can drive up to 126 segments and is capable of
controlling up to 4 general purpose output ports. The reset circuit provides on-chip voltage detection
making it possible to prevent incorrect displays. Pin assignments and application circuit are optimized
for easy PCB layout and cost saving advantages.
FEATURES
•
•
•
•
•
•
•
•
Up to 126 segments outputs
Up to 4 general purpose output ports
Key input function (up to 30 Keys)
1/3 duty - 1/2 bias and 1/3 duty - 1/3 bias drive techniques
Sleep mode and all segments off function
Direct display of display data without using a decoder
On-chip voltage-detection type reset circuit
RC oscillation circuit
APPLICATIONS
•
•
•
•
•
•
•
•
•
Cellular phone
Data bank, Organizer
Electronic dictionary/Translator
P.D.A.
P.O.S.
Information appliance
Caller ID
Pager
Electronic equipment with LCD display
PT6553 V1.7
-1-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
BLOCK DIAGRAM
COM1 COM2
TEST
COM3
SG40
COMMON
DRIVER
SG5 SG4/P4 SG3/P3 SG2/P2 SG1/P1
SEGMENT DRIVER & LATCH
SHIFT REGISTER
OSC
CONTROL
REGISTER
CLOCK
GENERATOR
DO
DI
CLK
KEY BUFFER
INTERFACE
CE
VDD
VDD1
KEY SCAN
VDET
VDD2
VSS
KI5
PT6553 V1.7
-2-
KI1
KO6
KO3
SG42/KO2 SG41/KO1
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CLK, CE, DI
VDD
VSS
INPUT PIN: KI1 TO KI5
VDD
VSS
OUTPUT PIN: DO
VDD
VSS
PT6553 V1.7
-3-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
OUTPUT PIN: SG1/P1 TO SG4/P4, SG5 TO SG40, SG41/KO1, SG42/KO2
VDD
VDD
VSS
VSS
VDD1
VDD2
OUTPUT PIN: KO3 TO KO6
VDD
VSS
OUTPUT PIN: COM1 TO COM3
VDD
VDD2
VDD2
VSS
PT6553 V1.7
-4-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
KO5
KO4
KO3
KO2/SG42
KO1/SG41
COM3
COM2
COM1
SG40
SG39
SG38
SG37
SG36
SG35
SG34
SG33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN CONFIGURATION
KO6
49
32
SG32
KI1
50
31
SG31
KI2
51
30
SG30
KI3
52
29
SG29
KI4
53
28
SG28
KI5
54
27
SG27
TEST
55
26
SG26
VDD
56
25
SG25
VDD1
57
24
SG24
VDD2
58
23
SG23
VSS
59
22
SG22
OSC
60
21
SG21
DO
61
20
SG20
CE
62
19
SG19
CLK
63
18
SG18
DI
64
17
SG17
PT6553 V1.7
-5-
SG16
SG15
SG14
SG13
SG12
SG11
SG10
SG9
SG8
SG7
SG6
SG5
P4/SG4
P3/SG3
P2/SG2
P1/SG1
PT6553
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
PIN DESCRIPTION
Pin Name
I/O
SG1/P1 ~ SG4/P4
O
SG5 ~ SG40
COM1, COM2, COM3
KO1/SG41
KO2/SG42
KO3 ~ KO6
KI1 ~ KI5
TEST
VDD
O
O
O
O
O
I
I
-
VDD1
-
VDD2
-
VSS
OSC
DO
CE
CLK
DI
I/O
O
I
I
I
PT6553 V1.7
Description
Segment Output/General Purpose Output Pins
Under serial data control, these pins may be
used a General Purpose Output Ports.
Segment Output
Common Driver Output Pins
Key Scan Output/Segment Output Pin
Key Scan Output/Segment Output Pin
Key Scan Output Pins
Key Scan Input Pins
Test Pin
Power Supply
Power Supply
This power supply pin is used for applying the LCD
Drive 2/3 bias voltage externally and must be
connected to VDD2 when using 1/2 bias drive.
Power Supply
This power supply pin is used for applying the LCD
Drive 1/3 bias voltage externally and must be
connected to VDD1 when using 1/2 bias drive.
Ground
Oscillator Pin
Data Output Pin
Chip Enable Pin
Synchronization Clock Input Pin
Data Transfer Input Pin
-6-
Pin No.
1~4
5 ~ 40
41, 42, 43
44
45
46 ~ 49
50 ~ 54
55
56
57
58
59
60
61
62
63
64
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
FUNCTION DESCRIPTION
SERIAL DATA INPUT
CONDITION 1: CLK IS TERMINATED AT THE "LOW" LEVEL
CE
CLK
DI
0
1
0
0
0
0
1
0
D1
D2
B0 B1 B2 B3 A0 A1 A2 A3
D3
D41
D42
0
0
0
DISPLAY DATA
0
S0
S1
K0
K1
P0
P1
SC
DR
CONTROL DATA
0
0
DD
DO
0
1
0
0
0
0
1
0
D43
D44
B0 B1 B2 B3 A0 A1 A2 A3
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
D45
D83
D84
0
0
0
0
DISPLAY DATA
D85
D86
D87
0
0
0
0
0
0
0
FIXED DATA
D125 D126
DISPLAY DATA
0
0
0
0
0
0
0
0
0
FIXED DATA
0
1
DD
0
0
0
0
1
0
DD
Where: DD= Direction Data
- Address: 42H
- D1 to D126: Display Data
- S0, S1: Sleep Control Data
- K0, K1: Key Scan Output/Segment Output Selection Data
- P0, P1: Segment Output Port/General Purpose Output Port Selection Data
- SC: Segment ON/OFF Control Data
- DR: 1/2 Bias or 1/3 Bias Drive Selection Data
PT6553 V1.7
-7-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
CONDITION 2: CLK IS TERMINATED AT THE "HIGH" LEVEL
CE
CLK
DI
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2
A3
0
0
D1
D2
D3
D41
D42
0
0
0
0
DISPLAY DATA
S0
S1
K0
K1
P0
P1
SC
DR
0
0
DD
CONTROL DATA
DO
0
1
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
0
1
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2
D43
D44
D45
A3
0
A3
D83
D84
0
0
0
0
DISPLAY DATA
D85
D86
D87
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FIXED DATA
0
1
DD
FIXED DATA
D125 D126
DISPLAY DATA
0
0
0
0
0
1
0
DD
Where: DD= Direction Data
- Address: 42H
- D1 to D126: Display Data
- S0, S1: Sleep Control Data
- K0, K1: Key Scan Output/Segment Output Selection Data
- P0, P1: Segment Output Port/General Purpose Output Port Selection Data
- SC: Segment ON/OFF Control Data
- DR: 1/2 Bias or 1/3 Bias Drive Selection Data
PT6553 V1.7
-8-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
CONTROL DATA FUNCTIONS
SLEEP CONTROL DATA BITS: S0, S1
S0 and S1 are sleep control data bits which can be switched between the normal and the sleep modes.
They are used to set the states of the KO1 to KO6 Key Scan Outputs when the key scan is in a standby
mode.
Control Data
S0
0
0
1
1
S1
0
1
0
1
Mode
OSC
Normal Operating
Sleep Stopped
Sleep Stopped
Sleep Stopped
Segment Outputs
Common Outputs
Operating
L
L
L
State of Output Pin during Key Scan
Standby Condition
KO1 KO2 KO3 KO4 KO5 KO6
H
H
H
H
H
H
L
L
L
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
Note: This is under the assumption that the KO1/SG41 and KO2/SG42 Pins are selected for Key Scan
Output.
KEY SCAN OUTPUT/SEGMENT OUTPUT SELECTION CONTROL DATA BITS: K0,
K1
K0 and K1 are control data bits which may be used for key scan output or segment output.
Control Data
K0
K1
0
0
0
1
1
x
State of Output Pins
KO1/SG41
KO2/SG42
KO1
KO2
SG41
KO2
SG41
SG42
Maximum Number of Input Keys
30
25
20
Note: x = Irrelevant
PT6553 V1.7
-9-
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
SEGMENT OUTPUT/GENERAL PURPOSE OUTPUT PORTS SELECTION DATA
BITS: P0, P1
P1 and P0 are control data bits which may be used for segment output port or general purpose output
port.
Control Data
P0
P1
0
0
0
1
1
0
1
1
SG1/P1
SG1
P1
P1
P1
State of Output Pin
SG2/P2
SG3/P3
SG2
SG3
P2
SG3
P2
P3
P2
P3
SG4/P4
SG4
SG4
SG4
P4
Condition 1: P0 and P1 are selected as General Purpose Output Port
When the control data bits, P0 and P1 are selected as General Purpose Output Port, the
corresponding display data and output pins are listed below.
Output Pin
SG1/P1
SG2/P2
SG3/P3
SG4/P4
Corresponding Display Data
D1
D4
D7
D10
This means that, if for example the output pin -- SG4/P4 is used as a General Purpose Output Port,
SG4/P4 Pin will output a high level when the display data , D10 is given a value of "1".
PT6553 V1.7
- 10 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
SEGMENT ON/OFF CONTROL DATA BITS: SC
SC is used to control the ON/OFF state of segments.
SC
0
1
Display State
On
Off
When SC is set to "0", the segment display state is "ON". When SC is set to "1", the segment display is
"OFF". This "OFF" state is achieved by outputting segment "OFF" waveforms from the segment output
pins.
1/2 BIAS OR 1/3 BIAS DRIVE SELECTION DATA BIT: DR
DR is the control data bit used to select either an LCD 1/2 or 1/3 bias drive. When DR is set to "0", the
1/3 LCD Bias Drive is selected. On the other hand, if DR is set to "1", the 1/2 LCD Bias Drive is
selected.
DR
0
1
PT6553 V1.7
LCD Bias Drive
1/3
1/2
- 11 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
DISPLAY DATA AND OUTPUT PINS
The display data and their corresponding output pins are listed in the table below.
Output Pin
SG1/P1
SG2/P2
SG3/P3
SG4/P4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
COM1
D1
D4
D7
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
COM2
D2
D5
D8
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
COM3
D3
D6
D9
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
Output Pin
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SG40
KO1/SG41
KO2/SG42
COM1
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D106
D109
D112
D115
D118
D121
D124
COM2
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
D98
D101
D104
D107
D110
D113
D116
D119
D122
D125
COM3
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
D108
D111
D114
D117
D120
D123
D126
Example: The segment output pin -- SG11 has the corresponding display data bits -- D31, D32, D33.
The table below gives the segment output states of SG11 Pin.
Display Date
D31
D32
D33
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PT6553 V1.7
State of Output Pin
SG11
LCD Segments for Com1, Com2, and Com3 are "Off"
LCD Segments for Com3 is "On"
LCD Segment for Com2 is "On"
LCD Segments for Com2 and Com3 are "On"
LCD Segments for Com1 is "On"
LCD Segments for Com1 and Com3 are "On"
LCD Segments for Com 1 and Com2 are "On"
LCD Segments for Com1, Com2, and Com3 are "On
- 12 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
SERIAL DATA OUTPUT
CONDITION 1: CLK IS TERMINATED AT THE "LOW" LEVEL
CE
CLK
DI
1
1
0
0
0
0
1
0
B0
B1
B2
B3
A0
A1
A2
A3
x
DO
KD1
KD2
KD29 KD30 SA
OUTPUT DATA
Where: x = Irrelevant
- Address: 43H
- KD1 to KD30: Key Data
- SA: Sleep Acknowledge Data
Notes:
1. The SA (Sleep Acknowledge data) will not be valid if the key data read operation is executed when
the DO is in "HIGH" level.
2. To be able to read the data correctly, the data reading process must be performed in the midpoint of
the rising and falling edge of the clock.
CONDITION 2: CLK IS TERMINATED AT THE "HIGH" LEVEL
CE
CLK
DI
1
1
0
0
0
0
B0
B1
B2
B3
A0
A1
0
1
A2
A3
x
DO
KD1
KD2 KD3
KD29 KD30 SA
x
OUTPUT DATA
Where: x = Irrelevant
- Address: 43H
- KD1 to KD30: Key Data
- SA: Sleep Acknowledge Data
Notes:
1. The SA (Sleep Acknowledge data) will not be valid if the key data read operation is executed
when the DO is in "HIGH" level.
2. To be able to read the data correctly, the data reading process must be performed in the midpoint of
the rising and falling edge of the clock.
PT6553 V1.7
- 13 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
OUTPUT DATA
KEY DATA: KD1 TO KD30
A key matrix having a maximum of 30 keys maybe constructed using the KO1 to KO6, and KI1 to KI5
lines. If any one of these keys are pressed, the key output data corresponding to the respective key is
set to "1". Please refer to the table below.
KO1/SG41
KO2/SG42
KO3
KO4
KO5
KO6
KI1
KD1
KD6
KD11
KD16
KD21
KD26
KI2
KD2
KD7
KD12
KD17
KD22
KD27
KI3
KD3
KD8
KD13
KD18
KD23
KD28
KI4
KD4
KD9
KD14
KD19
KD24
KD29
KI5
KD5
KD10
KD15
KD20
KD25
KD30
When a key matrix (maximum of 20 keys) are constructed using the KO3 to KO6 and KI1 to KI5 lines
and the KO1/SG41 and KO2/SG42 pins are used as Segment Output Pins via the control data bits -K0 and K1--, the KD1 to KD10 key data bits are set to "0".
SLEEP ACKNOWLEDGE DATA BIT: SA
SA is sleep acknowledge data bit. SA is set to "1" during the Sleep Mode and "0" during the Normal
Mode. When the key is pressed, the sleep acknowledge data bit will be set to the state.
PT6553 V1.7
- 14 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
SLEEP MODE FUNCTION
The Sleep Mode is activated by setting S0 or S1 to "1". Both the segment and common outputs will be
"LOW" and oscillation operation will stop reducing the power dissipation. However, oscillation
operation will be activated again when a key is pressed. The Sleep Mode is deactivated when both S0
and S1 bits are set to "0". It should be noted that even in the Sleep Mode, the SG1/P1 to SG4/P4 pins
can also be used as General Purpose Output Ports depending on the states of the P0 and P1 control
data bits. Please refer to the control data section for details.
KEY SCAN OPERATION
KEY SCAN TIMING
The key scan period is 288T (s). The key is scanned twice and when the key data is in agreement with
the key that has been pressed, then the key operation is valid. The key data read request (DO is set to
"LOW") is outputted after starting a key scan operation. If the key data is not in agreement with the key
that has been pressed, the PT6553 scans the key again. PT6553 can only detect a key press longer
than or equal to 615T (s). Please refer to the diagram below.
KO1
*
KO2
*
KO3
*
KO4
*
KO5
*
1
1
*
*
2
2
*
3
3
*
4
4
6
6
KO6
*
5
5
576T (s)
KEY ON
Note:
* = During the Sleep Mode Condition, the States ("HIGH" or "LOW") of these pins are determined by
the control data bits -- S0 and S1 bits. When these pins are set to "LOW" State the key scan output
signals are not outputted.
PT6553 V1.7
- 15 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
NORMAL MODE
Under the normal mode, the pins -- KO1 to KO6 -- are set to "HIGH". When a key is pressed, a key
scan operation commences. The keys are scanned until all keys are released. Multiple key operation is
recognized. When a key is pressed longer than 615T (s), PT6553 outputs a key data read request to
the controller. Please take note that T= 1/[fosc] and during the key data read request, the DO is set to
"LOW". The controller then acknowledges the key data request and reads the key data. However, if the
CE is "HIGH" during the serial data transfer, DO will be set to "HIGH". After the key data reading
operation is completed, the key data request is cleared (DO is set to "HIGH") and another key scan
operation is performed. It must be noted that DO is an open-drain output and thus requires a 1K to 10K
Ohms pull-up resistor. Please refer to the diagram below.
Key input 1
Key input 2
Key scan
615T(s)
615T(s)
615T(s)
CE
Serial data transfer
Serial data transfer
Key address (43H) Serial data transfer
Key address
Key address
DI
DO
Key data read
Key data read
Key data read request
Key data read request
Key data read
Key data read request
T = 1/fosc
PT6553 V1.7
- 16 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
SLEEP MODE
Under the Sleep Mode, the pins -- KO1 to KO6 are set to "HIGH" or "LOW" depending on the states of
the S0 and S1 control data bits. When a key located in one of the lines connected to any of the KO1 to
KO6 pins which is set to "HIGH" is pressed, the oscillation starts and a key scan operation is performed.
Keys are scanned until all the keys are released. Multiple key operation is valid if the multiple key data
bits are set. When a key is pressed longer than 615T (s), PT6553 outputs a key data
request to the controller. The controller acknowledges this request and performs the key data read
operation. However, of CE is set to "HIGH" during the serial data transfer, DO will be set to "HIGH".
After completion of the key data read operation by the controller, the key data read request is cleared
(DO is set to "HIGH") and another key scan operation is performed. Please note that this does not clear
the Sleep Mode. Please also be aware the DO is an open-drain output and requires 1K to 10 KΩ
pull-up resistor. The following is an example of a Sleep Mode Key Scan.
Example: S0="0", S1="1", Sleep Mode with KO6 = "HIGH"
「L」 K O 1
「L」 K O 2
When any one of these keys is pressed,
the oscillator starts and the key scan
operation commences.
「L」 K O 3
「L」 K O 4
「L」 K O 5
「H」 K O 6
*
KI1
KI2
KI3
KI4
KI5
Note: * = It is recommended that these diodes be connected in order to prevent incorrect operation due
to sneak currents in the KO6 scan output signals when the keys on the KO1 to KO5 lines are pressed
simultaneously. These diodes are needed to recognize multiple key presses on the KO6 line under the
sleep mode state with only the KO6 Line is "HIGH" (i.e. the example above.)
PT6553 V1.7
- 17 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
Key input
(KO6 line)
Key scan
615T(s)
615T(s)
CE
Serial data transfer
Serial data transfer
Key address (43H) Serial data transfer
Key address
DI
DO
Key data read
Key data read
Key data read request
Key data read request
T = 1/fosc
MULTIPLE KEY OPERATION
For dual key operation, triple key operation on the KI1 to KI5 input lines, or multiple key operation on
the KO1 to KO6 output lines do not to connect an external diode. Other multiple key operation other
than those stated may result in erroneous key press recognition. Therefore, to avoid this from
happening, a diode must be inserted in series with each key. Applications that do not recognize
multiple (3 or more) key operation should check the key data for three or more bits and ignore such
data.
PT6553 V1.7
- 18 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
1/3 DUTY, 1/2 BIAS DRIVE WAVEFORMS
f OSC /384 (Hz)
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
COM1
COM2
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
VDD
VDD1, VDD2
0V
COM3
LCD driver output
(All LCD segments corresponding to
COM1,COM2, COM3 are turned off)
LCD driver output
(LCD segments corresponding to
COM1 are on.
LCD driver output
(LCD segments corresponding to
COM2 are on.
LCD driver output
(LCD segments corresponding to
COM1, COM2 are on.
LCD driver output
(LCD segments corresponding to
COM3 are on.
LCD driver output
(LCD segments corresponding to
COM1 and COM3 are on.
LCD driver output
(LCD segments corresponding to
COM2 and COM3 are on.
LCD driver output
(LCD segments corresponding to
COM1, COM2 and COM3 are on.
PT6553 V1.7
- 19 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
1/3 DUTY, 1/3 BIAS DRIVE WAVEFORMS
f OSC /384 (Hz)
COM1
VDD
VDD1
VDD2
0V
COM2
VDD
VDD1
VDD2
0V
COM3
VDD
VDD1
VDD2
0V
LCD driver output
(All LCD segments corresponding to
COM1,COM2, COM3 are turned off)
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM1 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM2 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM1, COM2 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM1 and COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM2 and COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output
(LCD segments corresponding to
COM1, COM2 and COM3 are on.
VDD
VDD1
VDD2
0V
PT6553 V1.7
- 20 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET)
The Voltage Detection Type Reset Circuit (VDET) generates an output signal and resets the system
when the power is first applied as well as when the voltage drops (i.e., when the power supply voltage
is less than or equal to the power down detection voltage, VDET [3.0v typ.]). To insure proper operation
of this function, a capacitor must be connected to the power supply line so that the power supply
voltage (VDD) rise time (when the power is first applied) and the power supply voltage (VDD) fall time
(when the voltage drops) are at least 1ms. Please refer to the diagram below.
SYSTEM RESET
RESET METHOD
If the Supply voltage VDD rise time is at least 1 ms when power is applied, a system reset will be
initialized by the VDET output signal when the supply voltage is increased. If the supply voltage VDD fall
time is at least 1ms when the power drops, a system reset will be initialized by the VDET output signal
when the supply voltage is decreased. When all the serial data (including display data, D1 to D126 and
the control data) has been transferred, reset function is cleared.
This means that if for example, on the falling edge of the last direction data transfer's CE signal, (that is
after all the direction data have been transferred), the reset function is cleared. Please refer to the
diagram below.
VDD
VDET
VDET
t1
t2
CE
Display and control data transfer
INTERNAL
DATA
Undefined
Defined
System reset period
Power Supply Voltage (VDD) Rise Time: t1 ≥ 1ms
Power Supply Voltage (VDD) Fall Time: t2 ≥ 1ms
PT6553 V1.7
- 21 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
STATES OF THE PT6553 INTERNAL BLOCK DURING THE RESET PERIOD
Clock Generator
When the reset function is initialized, the base clock is terminated. The OSC Pin state, however is
determined after the S0 and S1 control data bits are transferred.
Common Driver, Segment Driver & Latch
When the reset function is initialized, the display is turned off. The display data, however, can be
inputted to the latch circuit in this state.
Key Scan
When the reset function is applied, the circuit is set to the initial state and at the same time, the key
scan operation is disabled.
Key Buffer
When the reset function is initialized, all the key data are set to "LOW".
Interface, Control Register, Shift Register
These circuits are not reset since serial data transfer is possible.
COM1
TEST
COM2
COM3
SG40
SG5 SG4/P4 SG3/P3 SG2/P2 SG1/P1
COMMON
DRIVER
SEGMENT DRIVER & LATCH
SHIFT REGISTER
OSC
CONTROL
REGISTER
CLOCK
GENERATOR
DO
DI
CLK
KEY BUFFER
INTERFACE
CE
VDD
VDD1
KEY SCAN
VDET
VDD2
VSS
KI5
KI1
KO6
KO3
SG42/KO2 SG41/KO1
Blocks that are reset
PT6553 V1.7
- 22 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
STATES OF THE OUTPUT PINS DURING THE RESET PERIOD
The states of the output pins during the reset period are shown in the table below.
Output Pin
SG1/P1 to SG4/P4
SG5 to SG40
COM1 to COM3
KO1/SG41, KO2/SG42
KO3 to KO5
KO6
DO
State during the Reset Period
L(see Note 1)
L
L
L (see Note 1)
x (see Note 2)
H
H (see Note 3)
Notes:
1. These output pins are forcibly set to the "Segment Output Function" and set to "LOW".
2. When the power is first applied, these output pins are undefined until the S0 and S1 control data bits
have been transferred.
3. This output pin is an open drain output, therefore, a 1K to 10 KΩ pull-up resistor is needed. This pin
remains "HIGH" during the reset period even if a key data read operation is performed.
4. x = irrelevant
PT6553 V1.7
- 23 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
DISPLAY DATA TRANSFER FROM CONTROLLER
There are three operations involved in the transfer of display data (D1 to D126) to the PT6553. All
display data must be transferred within 30 ms so as to insure and maintain the quality of the displayed
image.
CONTROLLER KEY DATA READ TECHNIQUE
Timer - based key Data Acquisition
The controller makes use of a timer to determine the Key ON/OFF states and to read the key data. The
controller must check every t7 period the DO state when the CE is in the "LOW" state. If the DO is
"LOW", the controller will acknowledge the key that has been pressed and execute the key data read
operation. The t7 must satisfy the following condition:
t7 ≥ (t5 + t6 + t4)
If a key read operation is executed when the DO is in "HIGH" State, the read key data (KD1 to KD30)
and the sleep acknowledge data (SA) will be invalid.
The timer based key data acquisition flowchart is given below.
CE=[L]
DO=[L]
No
Yes
Key Data Read
Processing
PT6553 V1.7
- 24 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
Timing Diagram
Key on
Key on
Key input
Key scan
t3
t4
t3
t3
CE
t6
t6
t6
DI
t5
t5
Key data read t5
DO
Key data read request
t7
Controller determination
(key on)
t7
Controller determination
(key on)
t7
Controller determination
(key off)
t7
Controller determination Controller determination
(key off)
(key on)
Notes:
1. t3 = Key Scan Execution Time when after two key scan operations, the key data match (615T (s))
2. t4 = Key Scan Execution Time when after two key scan operations, the key data do not match and
the key scan operation was once again performed. (1230T (s)).
3. T = 1/fosc
4. t5 = Key Address (43H) Transfer Time
5. t6 = Key Data Read Time
PT6553 V1.7
- 25 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
Interrupt - Based Key Data Acquisition
The interrupt-based key data acquisition flowchart is given below.
CE = [L]
DO = [L]
NO
YE S
K ey Data Read
Processing
Wait for at
Least t8
CE = [L]
NO
DO = [H]
YE S
Key Off
PT6553 V1.7
- 26 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
Interrupt - Based Key Data Acquisition Timing Diagram
Key on
Key on
Key input
Key scan
t4
t3
t3
t3
CE
t6
t6
t6
t6
DI
t5
Key data read
t5
t5
t5
DO
Key data read request
t8
Controller determination
(key on)
t8
t8
t8
Controller determination
Controller determination
(key on)
Controller determination (key on)
Controller determination
Controller determination
(key off)
(key off)
(key on)
Notes:
1. t3 = Key Scan Execution Time when after two key scan operations, the key data match (615T (s))
2. t4 = Key Scan Execution Time when after two key scan operations, the key data do not match and
the key scan operation was once again performed. (1230T (s)).
3. T = 1/fosc
4. t5 = Key Address (43H) Transfer Time
5. t6 = Key Data Read Time
PT6553 V1.7
- 27 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
ABSOLUTE MAXIMUM RATING
(Unless otherwise specified Ta=25℃, Vss=0V)
Parameter
Symbol
Conditions
Maximum supply voltage
VDDmax VDD
VIN1
CE, CLK, DI
Input voltage
OSC, KI1 to KI5, TEST,
VIN2
VDD1, VDD2
VOUT1
DO
OSC, SG1 to SG42,
Output voltage
VOUT2
COM1 to COM3,
KO1 to KO6, P1 to P4
IOUT1
SG1 to SG42
IOUT2
COM1 to COM3
Output current
IOUT3
KO1 to KO6
P1 to P4
IOUT4
Ta=85℃
Allowable power dissipation
Pdmax
Operating temperature
Topr
Storage temperature
Tstg
-
PT6553 V1.7
- 28 -
Rating
-0.3 to +7.0
-0.3 to VDD+0.3
Unit
V
V
-0.3 to VDD+0.3
V
-0.3 to VDD+0.3
V
-0.3 to +VDD+0.3
V
300
3
1
5
200
-40 ~ +85
-65 ~ +150
µA
mA
mA
mA
mW
℃
℃
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
ALLOWABLE OPERATING CONDITION
(Unless otherwise specified, Ta=25℃, Vss=0V)
Parameter
Symbol
Condition
Supply voltage
VDD
VDD
VDD1 VDD1
Input voltage
VDD2 VDD2
VIH1
CE, CLK, DI
High level input voltage
VIH2
KI1 to KI5
Low level input voltage
VIL
CE, CLK, DI, KI1 to KI5
Oscillation resistance
ROSC OSC
Oscillation capacitor
COSC OSC
Oscillation range
fOSC
OSC
Data setup time
tds
CLK, DI (see Note 2)
Data hold time
tdh
CLK, DI (see Note 2)
CE wait time
tcp
CE, CLK (see Note 2)
CE setup time
tcs
CE, CLK (see Note 2)
CE hold time
tch
CE, CLK (see Note 2)
High level clock pulse
tøH
CLK (see Note 2)
width
Low level clock pulse
tøL
CLK (see Note 2)
width
CE, CLK, DI
Rise time
tr
(see Note 2)
CE, CLK, DI
Fall time
tf
(see Note 2)
DO, Rpu=4.7KΩ, CL=10pF
DO output delay time
tdc
(see Note 1 & 2)
DO, Rpu=4.7KΩ, CL=10pF
DO rise time
tdr
(see Note 1 & 2)
Min.
4.5
0.8VDD
0.6VDD
0
19
160
160
160
160
160
Typ.
2/3VDD
1/3VDD
68
820
38
-
Max.
6.0
VDD
VDD
VDD
VDD
0.2VDD
76
-
Unit
V
V
V
V
V
V
KΩ
pF
KHz
ns
ns
ns
ns
ns
160
-
-
ns
160
-
-
ns
-
160
-
ns
-
160
-
ns
-
-
1.5
µs
-
-
1.5
µs
Notes:
1. DO is an open-drain output, therefore, these values depend on the resistance value of pull-up
resistor Rpu and the capacitance value of the load capacitor, CL.
2. Refer to the Timing Waveforms shown on page 30.
PT6553 V1.7
- 29 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
TIMING WAVEFORMS
CONDITION 1: WHEN CLK IS TERMINATED AT "LOW" LEVEL
V IH1
V IL
CE
tψL
tψH
V IH1
CLK 50%
V IL
tr
tf
tcp
tch
tcs
V IH1
DI
V IL
tds
tdh
tdr
tdc
DO
D0
D1
CONDITION 2: WHEN CLK IS TERMINATED AT "HIGH" LEVEL
V IH1
V IL
CE
tψL
tψH
V IH1
50%
V IL
CLK
tf
tr
tcs
tch
V IH1
DI
V IL
tds
DO
tcp
tdh
D0
D1
tdc
PT6553 V1.7
- 30 -
tdr
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, Ta=25℃, VDD=5V, VSS=0V)
Parameter
Hysteresis
Power-down detection voltage
High level input current
Low level input current
Pull-down resistance
High level output voltage
Symbol
VH
VDET
IIH
IIL
RPD
VOH1
VOH2
VOH3
VOH4
Low level output voltage
VOL1
VOL2
VOL3
VOL4
VOL5
VMID1
VMID2
Middle level output voltage*
VMID3
VMID4
VMID5
Oscillation frequency
Current drain
fosc
IDD1
IDD2
IDD3
PT6553 V1.7
Condition
CE, CLK, DI
CE, CLK, DI, VI=VDD
CE, CLK, DI, VI=0V
KI1 to KI5, VDD=5.0V
KO1 to KO6, IO=-500µA
P1 to P4, IO=-1mA
SG1 to SG42, IO=-20µA
COM1 to COM3,
IO=-100µA
KO1 to KO6, IO=35µA
P1 to P4, IO=1mA
SG1 to SG42, IO=20µA
COM1 to COM3,
IO=100µA
DO, IO=1mA
COM1 to COM3, 1/2 Bias.
IO=±100µA
SG1 to SG42, 1/3 Bias.
IO=±20µA
SG1 to SG42, 1/3 Bias.
IO=±20µA
COM1 to COM3, 1/3 Bias.
IO=±100µA
COM1 to COM3, 1/3 Bias.
IO=±100µA
OSC, R=68KΩ, C=820pF
Sleep Mode
VDD=6.0,
Output Open 1/3 Bias
fosc=38kHz
VDD=6.0
Output Open 1/2 Bias
fosc=38kHz
- 31 -
Min.
2.7
-5.0
50
VDD-1.2
VDD-1.0
VDD-1.0
Typ.
0.1VDD
3.0
100
VDD-0.5
-
Max.
3.3
5.0
250
VDD-0.2
-
Unit
V
V
µA
µA
KΩ
V
V
V
VDD-1.0
-
-
V
0.2
-
0.5
-
1.5
1.0
1.0
V
V
V
-
-
1.0
V
-
0.1
0.5
V
1/2VDD-1.0
-
1/2VDD+1.0
V
2/3VDD-1.0
-
2/3VDD+1.0
V
1/3VDD-1.0
-
1/3VDD+1.0
V
2/3VDD-1.0
-
2/3VDD+1.0
V
1/3VDD-1.0
-
1/3VDD+1.0
V
30.4
-
38
-
45.6
100
KHz
µA
-
350
700
µA
-
300
600
µA
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
Note: * Excluding the Bias Voltage Generation Divider Resistor built into the VDD1 and VDD2. Refer to
the diagram below.
VDD
VDD1
TO THE COMMON SEGMENT
DRIVER
VDD2
EXCLUDING THESE RESISTORS
PT6553 V1.7
- 32 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
APPLICATION CIRCUIT 1
1/2 BIAS (FOR NORMAL PANEL USE)
+5V
*1
SG33 33
SG34 34
SG36 36
SG35 35
SG37 37
SG38 38
SG40 40
SG39 39
COM1 41
COM2 42
COM3 43
SG31 31
51 KI2
SG30 30
52 KI3
SG29 29
53 KI4
SG28 28
54 KI5
SG27 27
55 TEST
SG26
56 VDD
SG25 25
P T 6553
57 VDD1
C
58 VDD2
SG24 24
(general-purpose
output ports)
Used with the
backlight controller
or other ciucuit.
16 SG16
14 SG14
SG9
9
15 SG15
SG8
8
13 SG13
SG7
7
11 SG11
SG6
6
12 SG12
SG5
10 SG10
P4/SG4
SG17 17
5
SG18 18
64 DI
4
SG19 19
63 CLK
P3/SG3
62 CE
P2/SG2
SG20 20
3
SG21 21
61 DO
2
MCU
*2
60 OSC
P1/SG1
+5V
SG22 22
1
820pF
26
SG23 23
59 VSS
68K
SG32 32
LCD panel (up to 126 segments)
C > 0.047μF
KO1/SG41 44
49 KO6
50 KI1
KO2/SG42 45
KO3 46
KO4 47
KO5 48
Key matrix
(up to 30 keys)
(P1)
(P2)
(P3)
(P4)
Notes:
1. Connect a capacitor to the power supply line so that the when the PT6553 is reset by the VDET, the
power supply VDD rise time when power is applied and the power supply voltage VDD fall time when
power drops are both at least 1ms.
2. Since the DO Pin is an open drain output, it needs a pull-up resistor (1K to 10KΩ) which is
appropriate for the capacitance of the external wiring so that the waveforms are not degraded.
PT6553 V1.7
- 33 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
APPLICATION CIRCUIT 2
1/2 BIAS (FOR LARGE PANEL USE)
+5V
10K
*1
R1
C > 0.047μF
C
>R>1K
SG33 33
SG34 34
SG35 35
SG36 36
SG37 37
SG38 38
SG40 40
SG39 39
COM1 41
COM2 42
COM3 43
SG31 31
51 KI2
SG30 30
52 KI3
SG29 29
53 KI4
SG28 28
54 KI5
SG27 27
55 TEST
SG26
56 VDD
SG25 25
P T 6553
57 VDD1
R2
58 VDD2
SG24 24
(general-purpose
output ports)
Used with the
backlight controller
or other ciucuit.
16 SG16
15 SG15
14 SG14
SG9
9
13 SG13
SG8
8
12 SG12
SG7
7
11 SG11
SG6
6
10 SG10
SG5
5
SG17 17
P4/SG4
SG18 18
P3/SG3
63 CLK
64 DI
4
SG19 19
3
62 CE
P2/SG2
SG20 20
P1/SG1
MCU
*2
SG21 21
61 DO
1
+5V
SG22 22
60 OSC
2
820pF
26
SG23 23
59 VSS
68K
SG32 32
LCD panel (up to 126 segments)
50 KI1
KO1/SG41 44
KO3 46
49 KO6
KO2/SG42 45
KO4 47
KO5 48
Key matrix
(up to 30 keys)
(P1)
(P2)
(P3)
(P4)
Notes:
1. Connect a capacitor to the power supply line so that the when the PT6553 is reset by the VDET, the
power supply VDD rise time when power is applied and the power supply voltage VDD fall time when
power drops are both at least 1ms.
2. Since the DO Pin is an open drain output, it needs a pull-up resistor (1K to 10KΩ) which is
appropriate for the capacitance of the external wiring so that the waveforms are not degraded.
3. R1=R2, the resistance value must be decide by the LCD panel size.
PT6553 V1.7
- 34 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
APPLICATION CIRCUIT 3
1/3 BIAS (FOR NORMAL PANEL USE)
+5V
*1
SG33 33
SG34 34
SG36 36
SG35 35
SG37 37
SG38 38
SG40 40
SG39 39
SG29 29
53 KI4
SG28 28
54 KI5
SG27 27
55 TEST
SG26
56 VDD
SG25 25
P T 6553
SG24 24
(general-purpose
output ports)
Used with the
backlight controller
or other ciucuit.
16 SG16
14 SG14
15 SG15
SG9
9
13 SG13
SG8
8
11 SG11
SG7
7
12 SG12
SG6
6
10 SG10
SG5
SG17 17
P4/SG4
SG18 18
64 DI
5
SG19 19
63 CLK
4
62 CE
P3/SG3
SG20 20
P2/SG2
SG21 21
61 DO
3
MCU
*2
60 OSC
2
+5V
SG22 22
P1/SG1
820pF
26
SG23 23
59 VSS
1
68K
COM1 41
SG30 30
52 KI3
58 VDD2
C
COM2 42
COM3 43
SG31 31
51 KI2
57 VDD1
C
SG32 32
LCD panel (up to 126 segments)
C > 0.047μF
KO1/SG41 44
49 KO6
50 KI1
KO2/SG42 45
KO3 46
KO4 47
KO5 48
Key matrix
(up to 30 keys)
(P1)
(P2)
(P3)
(P4)
Notes:
1. Connect a capacitor to the power supply line so that the when the PT6553 is reset by the VDET, the
power supply VDD rise time when power is applied and the power supply voltage VDD fall time when
power drops are both at least 1ms.
2. Since the DO Pin is an open drain output, it needs a pull-up resistor (1K to 10KΩ) which is
appropriate for the capacitance of the external wiring so that the waveforms are not degraded.
PT6553 V1.7
- 35 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
APPLICATION CIRCUIT 4
1/3 BIAS (FOR LARGE PANEL USE)
10K >R>1K
C > 0.047μF
SG33 33
SG34 34
SG35 35
SG36 36
SG37 37
SG38 38
SG39 39
SG40 40
COM1 41
COM2 42
COM3 43
SG29 29
53 KI4
SG28 28
54 KI5
SG27 27
55 TEST
SG26
56 VDD
SG25 25
P T 6553
58 VDD2
SG24 24
(general-purpose
output ports)
Used with the
backlight controller
or other ciucuit.
16 SG16
14 SG14
15 SG15
SG9
9
12 SG12
SG8
8
13 SG13
SG7
7
11 SG11
SG6
6
10 SG10
SG5
SG17 17
5
SG18 18
64 DI
P4/SG4
SG19 19
63 CLK
P3/SG3
62 CE
4
SG20 20
3
SG21 21
61 DO
P2/SG2
*2
SG22 22
60 OSC
P1/SG1
+5V
26
SG23 23
59 VSS
820pF
MCU
52 KI3
57 VDD1
*3
R3
C
SG30 30
1
R2
C
68K
*1
R1
SG31 31
51 KI2
2
+5V
SG32 32
LCD panel (up to 126 segments)
50 KI1
KO1/SG41 44
KO3 46
49 KO6
KO2/SG42 45
KO4 47
KO5 48
Key matrix
(up to 30 keys)
(P1)
(P2)
(P3)
(P4)
Notes:
1. Connect a capacitor to the power supply line so that the when the PT6553 is reset by the VDET, the
power supply VDD rise time when power is applied and the power supply voltage VDD fall time when
power drops are both at least 1ms.
2. Since the DO Pin is an open drain output, it needs a pull-up resistor (1K to 10KΩ) which is
appropriate for the capacitance of the external wiring so that the waveforms are not degraded.
3. R1=R2=R3, the resistance value must be decide by the LCD panel size.
PT6553 V1.7
- 36 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
ORDER INFORMATION
Valid Part Number
PT6553-Q
PT6553-LQ
PT6553 V1.7
Package Type
64 Pins, QFP
64 Pins, LQFP
- 37 -
Top Code
PT6553-Q
PT6553-LQ
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
PACKAGE INFORMATION
64 PINS, QFP
D
D1
A
A2
D2
A1
-B-
-A-
L1
E1
E2
E
-D-
e
c
b
θ1
C SEATING PLANE
θ
0.10
C
θ2
R1
R2
-H-
GAUGE PLANE
0.25mm
S
L
θ3
PT6553 V1.7
- 38 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
Symbol
c
L
L1
A
A1
A2
b
D
D1
D2
E
E1
E2
e
S
θ
θ1
θ2
θ3
R1
R2
Min.
0.11
0.73
PT6553
Nom.
0.88
1.60 BASIC
2.70
17.20 BSC.
14.00 BSC.
12.00 REF.
17.20 BSC.
14.00 BSC.
12.00 REF.
0.80 BSC.
-
0.00
2.50
0.29
0.20
0°
0°
5°
5°
0.13
0.13
Max.
0.23
1.03
3.15
0.25
2.90
0.45
7°
16°
16°
0.30
Notes:
1. All dimensioning and tolerancing conform to ASME Y14.5M - 1994.
2. Datum Plane H is located at the bottom of the mold parting line coincident with where the lead
exits the body.
3. Datums A-B and D to be determined at datum plane H.
4. Dimensions D1 and E1 do not include mold prortrusion. Allowable protrusion is 0.25mm per side.
Dimensions D1 and E1 do include mold mismatch and are determined at the datum plane H.
5. Controlling Dimension: MILLIMETERS
6. Dimension b does not include dambar protrusion. The dambar protrusion (s) shall not cause the
lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower
radius or the lead foot.
7. A1 is defined as the distance from the seating plane to the lowest point of the package body.
8. Refer to JEDEC MS-022 Variation BE
JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT6553 V1.7
- 39 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
PT6553
64 PINS, LQFP
D
D1
A
A2
A1
-B-
-A-
L1
E1
E
-D-
e
c
b
θ1
C SEATING PLANE
θ
ccc
θ2
C
R1
R2
-H-
GAUGE PLANE
0.25mm
S
L
θ3
PT6553 V1.7
- 40 -
November, 2007
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
LCD Driver IC with Key Input Function
Symbol
A
A1
A2
b
D
D1
e
E
E1
ccc
θ
θ
θ2
θ3
c
L
L1
R1
R2
S
Min.
0.05
1.35
0.17
0°
0°
11°
11°
0.09
0.45
0.08
0.08
0.20
PT6553
Typ.
1.40
0.22
12.00 BSC
10.00 BSC
0.50 BSC
12.00 BSC
10.00 BSC
0.08
3.5°
12°
12°
0.60
1.00 REF
-
Max
1.60
0.15
1.45
0.27
7°
13°
13°
0.20
0.75
0.20
-
Notes:
1.
Dimensioning and tolerancing per ASME Y14.5M-1994
2.
The top package body size may be smaller than the bottom package size by as much as 0.15mm.
3.
Datum A-B and D to be determined at the datum plane H.
4.
Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per
side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
5.
Controlling Dimension: MILLIMETER
6.
Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be
located on the lower radius or the foot. Minimum space between the protrusion and an adjacent
lead is 0.07mm for 0.4mm and 0.5mm PITCH package.
7.
These dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the
lead tip.
8.
A1 is defined as the distance from the seating plane to the lowest point on the package body.
9.
Details of pin 1 identifier are optional but must be located within the zone identified.
10. Dimension D2 and E2 show the minimum allowed for the optional exposed heat slug. The
maximum allowed is equal to the package body size (D1 and E1). However, the size of the
exposed heat slug is variable depending on the device function (die size). End users should verify
the actual size or either top or bottom exposed thermal pad for specific device application.
11. Refer to JEDEC MS-026 Variation BCD.
JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT6553 V1.7
- 41 -
November, 2007