LQ
CAPACITANCE
QT300
TO
DIGITAL CONVERTER
Capacitance to Digital Converter (CDC) IC
Direct-to-digital conversion, 16 bits
Log response: Wide dynamic range
1
SCK
2
SNS1
3
Vss
4
Outputs raw data to a host device
Single wire UART interface
Master or Slave mode SPI interface
QT300
DRDY
Programmable clock speed
Turns objects into intrinsic touch sensors
8
Vdd
7
SDO
6
REQ / 1W
5
SNS2
One external sample capacitor to control gain
Multiple QT300’s possible on one SPI bus
The QT300 charge-transfer (“QT’”) IC is a self-contained Capacitance-toDigital-Converter (CDC) capable of detecting femotofarad level changes in
capacitance. While designed primarily for instrumentation applications, it can be used
also for touch control applications where signal processing is best handled by a host
MCU.
Primary applications include fluid level sensors, distance sensors, transducer
‘amplifiers’ for pressure and humidity sensing functions, material detectors, and other
uses requiring quantified capacitance data.
APPLICATIONS
Fluid level sensors
Prox sensors
Moisture detection
Position sensing
Transducer driver
Material sensors
Unlike other Quantum products, the QT300 does not process its acquired data. Its only result is raw, unprocessed binary
data which can be transmitted to a host via either a bidirectional SPI interface or a simple polled single wire UART type
interface. This allows the designer to treat the device as a capacitance-to-digital-converter (CDC) for measurement
applications. It is ideal for situations where there are unique signal processing requirements.
The device requires only a single sampling capacitor to function. The value of this capacitor controls the gain of the sensor,
and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components
are required.
The device operates on demand, and can be synchronized to allow several QT300’s to operate near each other without
cross-interference.
LQ
TA
AVAILABLE OPTIONS
SOIC
8-PIN DIP
00C to +700C
-400C to +850C
QT300-IS
QT300-D
-
Copyright © 2002 QRG Ltd
QT300 R1.01 21/09/03
Table 1-1 SPI Mode Pin Description
Pin
Name
Function
1
2
3
4
5
6
7
8
/DRDY
SCK
SNS1
VSS
SNS2
/REQ
SDO
VDD
Vdd
Data Ready
Serial data clock
Sense 1 line
Negative supply (ground)
Sense 2 line
Request input
Serial data out
Positive supply
SNS1
VSS
SNS2
1W
VDD
8
Vcc
1
DRDY
DRDY
2
SCK
Host Micro
6
REQ
7
SDI
Connect to Vdd or Vss
Connect to Vdd or Vss
Sense 1 line
Negative supply (ground)
Sense 2 line
1W UART Line
Connect to Vdd or Vss
Positive supply
SNS 2
5
SENSOR
CS
SDO
8
Vdd
1
SNS1
2
3
Electrode
Host Micro
7
6
SNS2
5
1W
Vss
4
Figure 1-2 Basic QT300 Circuit in UART mode.
Serial clone data clock
Serial clone data in
Serial clone data out
1.2 CS / CX Dependency
The value returned is a direct function of Cs, the fixed sample
capacitor and Cx, the unknown or variable capacitance.
These two values influence device sensitivity and response
time, making them very important parameters.
1 - OVERVIEW
The QT300 is a digital burst mode charge-transfer (QT)
capacitance-to-digital converter (CDC) designed for
applications requiring raw signal information such as fluid
level sensing and distance gauging; it outputs raw digital
signal data over a serial interface. The output data is in a
16-bit format; signal levels depend on load (Cx) and the
sampling capacitor value (Cs).
Sensitivity is also a function of electrode size, shape,
orientation, the composition and aspect of the object being
sensed, the thickness and composition of any dielectric
overlaying the electrode, and the degree of mutual coupling
between the electrode and the object being sensed.
The response follows a logarithmic curve (Figures 7-4, 7-5,
Page 10); each doubling of Cs increases the signal level and
differential sensitivity by a factor of 2. Likewise, doubling Cx
reduces the signal level and differential sensitivity by a factor
of 2.
1.1 Basic Operation
The QT300 does no internal signal processing; data is simply
returned via one of two serial port types.
There are two basic types of serial interface: 4-wire SPI and
a simple single wire (‘1W’) UART. The SPI interface allows
multiple devices to be connected on one SPI bus, while
the1W UART requires that the controller have one dedicated
pin for each QT300. There are two types of SPI mode,
master and slave.
2 - Timing
Figure 2-1 shows the basic QT300 acquisition timing
parameters. The basic timing parameters are:
Tbd
Tacq
Tbs
The type of serial port and its mode can be selected via the
cloning process using a QTM300CA programming adapter.
The QT300 operates only on request from a host device.
After initiation via a trigger signal, the QT300 generates an
acquisition burst and sends the resulting raw signal data
back via one of the serial modes.
LQ
REQ
3
QT300
Table 1-3 Alternate Cloning Pin Functions
Pin
Name
Function
SCK
SDI
SDO
SNS 1
Figure 1-1 Basic QT300 Circuit in SPI mode.
(1W UART)
Rx
2
6
7
SCK
GND
4
Table 1-2 1W UART Mode Pin Description
Pin
Name
Function
1
2
3
4
5
6
7
8
100nF
QT 300
Burst duration
Acquire response time
Burst Spacing
(2.1)
(2.2)
(2.3)
2.1 Tbd - Burst duration
The burst duration depends on the values of Cs and Cx and
to a lesser extent, Vdd. The burst is composed of
charge-transfer cycles operating at about 240kHz.
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QT300 R1.01 21/09/03
The length of this burst is an important
parameter as it is directly related to the signal
value. The burst duration also affects the
response time of the sensor; the larger Cs is, the
longer the burst, the slower the possible
acquisition rate.
2.2 Tacq - Acquire Response Time
The time from the /REQ or 1W line going low
until the completion of data transmission is
Tacq. Tacq depends on the acquisition burst
length as well as the serial transmission time.
SPI Mode: In SPI mode Tacq depends in part on
the serial clock speed and the space between
the returned high and low bytes. In SPI slave
mode the clock speed and the inter-byte spacing
time Tbdly is determine by the host. In SPI
Master mode these timings are set by Setup
parameters SCD and MLS.
1W mode: Tacq depends in part on the Baud
rate as well as the inter-byte spacing. The Baud
rate is auto-set by the trigger pulse width; the
inter-byte spacing is set by the MLS parameter.
See Section 4.
2.3 Tbs - Burst Spacing
Figure 2-1 Signal Acquisition - Slave SPI Mode
Burst spacing is the time from the start of one
acquisition burst to the start of the next burst. It
depends on the host’s trigger rate on the /REQ or 1W pin.
The QT300 only acquires when the host requests it.
In master mode, /DRDY goes high between bytes for the
period determined by Setup parameter MLS; this is a multiple
of 6µs.
While waiting for a new request the part is in a low power
mode.
When not communicating, all SPI lines float to allow multiple
chips to connect over the same SPI lines. A pullup or
pulldown resistor is required on SCK depending on the
selected clock phase, determined by Setups. A pullup
resistor is required on /DRDY. /REQ may require a pullup if
the host ever allows this line to float.
3 - SPI Port
3.1 SPI Specifications
The QT300 can operate in master or slave mode, and thus is
compatible with virtually all SPI-capable microcontrollers. The
SPI interface has the following specifications:
Max clock rate, Fckm
Max clock rate, Fcks
Data length
Inter-byte delay
Clock idle logic level
Clock edge
Data sequence
3.3 SPI Bus Sharing
All SPI float transfers making it possible to have several
QT300 devices (or other unrelated devices) share the SPI
control signals (Figure 3-1).
40KHz (master mode)
40KHz (slave mode)
2 bytes (16 bits total)
≥8µs (master mode)*
≥12µs (slave mode)
Low or High*
Data out on rising or falling edge*
High byte first, MSB first
Each part needs an individual /REQ line, but /DRDY, SCK
and SDO can be connected together.
3.4 SPI Slave Mode
Refer to Figure 7-1 and Table 7-1, page 8.
In SPI Slave mode, /DRDY is used to let the host know when
data is ready for collection in response to a request so that
the host can clock over the data.
*Determined by Setups
The host can clock the SPI at any rate up to and including
the maximum. The maximum clock rate of the part in Master
mode is determined in Setups via cloning.
SPI Slave mode uses 4 signals:
/REQ - Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
3.2 Protocol Overview
The QT300 only transmits data on request, after an
acquisition burst. The host requests an acquire by setting the
/REQ line low for at least 30µs; the device then acquires.
When finished, the DRDY line is pulled low by the QT300 to
indicate it is ready to send data. (Figure 2-1). The transfer is
done as two bytes, with the highest byte transferred first.
LQ
/REQ should return high before the end of the burst. If
/REQ is still low at the end of the burst the part will go into
Setup mode. The minimum duration of /REQ is 30µs.
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QT300 R1.01 21/09/03
A typical SPI slave mode communication sequence is:
Figure 3-1 Multiple QT300's on the same SPI port
1) Host pulses /REQ low for ≥30µs to initiate an acquire.
Vdd
2) QT300 acquires a signal in response to /REQ.
100nF
3) QT300 pulls /DRDY low when ready to send data back.
8
Vcc
1
DRDY
QT 300
DRDY
Host Micro
SCK
2
REQ3
REQ2
REQ1
6
SDI
7
4) Host detects /DRDY is low.
SCK
SNS 1
REQ
SNS 2
3
5
SENSOR
5) Host clocks out the high byte of data from the QT300.
CS
6) Host waits for ≥12µs.
SDO
GND
4
7) Host clocks out the low byte of data from the QT300.
Vdd
8) QT300 releases /DRDY to float high.
100nF
8
Vcc
DRDY
QT 300
1
2
6
7
SCK
SNS 1
REQ
SNS 2
3
5
3.5 SPI Master Mode
SENSOR
Refer to Figure 7-2 and Table 7-2, page 8.
CS
In master SPI mode the QT300 generates the clock signal
after an acquire initiated from the host via the /REQ line. The
clock speed and the spacing between the two bytes is set via
the Setup process (Section 6).
SDO
GND
4
Vdd
100nF
8
Vcc
1
DRDY
QT 300
2
6
7
SCK
SNS 1
REQ
SNS 2
3
5
SCD setup parameter determines the master-mode clock
rate. The default value is 55 (resulting in a 2.55KHz rate).
The relationship is:
SENSOR
CS
SDO
Fscd = 1200/(30+ (SCD x 8)) in Khz
Where SCD = 0..255
GND
4
MLS setup parameter determines the spacing between the
two return bytes; this can be important to allow a slow host
device to recover from receiving the first byte to prevent an
overrun. The default value is 148 (resulting in a 500µs gap).
The relationship is:
SDO - Serial Data Output; Output-only. This is the data
output to the host during an SPI transfer. When not in use,
this pin floats. This pin should be connected to the SDI
input pin of the host device.
Tmls (in µs) = (10 + MLS x 4) / 1.2
Where MLS = 0..255 (from user setup MLS)
SCK - SPI clock; Idle high or idle low; input-only SPI clock
from the host. The idle state is determined in Setups by
the serial mode (SM) parameter.
Master SPI mode requires at least 3 signals to operate:
/REQ - Request Acquisition Input; Active low input-only.
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
If SM is set for idle-low SCK: Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
/REQ must return high before the end of the burst. If
/REQ is still low at the end of the burst the part goes into
Setup mode. The minimum duration of /REQ is 30µs.
If SM is set for idle-high SCK: Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
SDO - Serial Data Output; Idle low output-only. This is the
data output to the host during an SPI transfer. When not in
use, this pin floats. This pin should be connected to the
SDI input pin of the host device.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-1.
/DRDY - Data Ready; active low output only. This indicates to
the host that the device is ready to send data back to the
host. During idle times this pin floats and therefore must
be connected to a pullup resistor. The host must wait until
/DRDY goes low before starting an SPI transfer.
SCK - SPI clock; Idle high or idle low, output-only. The idle
state is determined in Setups by the serial mode (SM)
parameter.
If SM is set for idle-low SCK: Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
Between the high and low byte clockings, the host should
observe a delay of ≥12µs.
If SM is set for idle-high SCK: Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-2.
/DRDY - Data Ready (Optional); active low output only. This
indicates to the host that the device is ready to send data
LQ
4
QT300 R1.01 21/09/03
4 Single-Wire (1W) UART
Interface
The single wire ('1W') UART option allows all
communications to take place over a single
bidirectional line with a 10K pullup resistor. The host
device triggers the QT300 to acquire by means of a
pulse sent to the QT300 over the wire. The Baud rate
is established by the width of this pulse; the pulse
width establishes the bit rate of the UART
transmission to follow. The QT300 then acquires, and
responds by sending two bytes of data back over the
1W line with a delay between the bytes as determined
by parameter MLS.
1W operation permits a device to be controlled from a
single pin on a host controller, using either a hardware
or software UART. Several QT300’s can coexist on a
single host pin, provided there is some logic steering.
This mode is set via the cloning process using
parameter SM (see Section 6).
4.1 1W UART Specifications
The QT300 operates in 1W UART mode with the
following specifications:
Baud rate range
Data length
Stop bit
Parity
Idle state
4,800 to 9,600 bits/sec
2 bytes (16 bits total)
1 (each byte)
None
High
The 1W line must have a pullup resistor on it (i.e.
10K), or 1W communications will not function.
4.2 UART 1W Protocol
The QT300 acquires and transmits only on request.
The sequence is:
1) The host generates a pulse on the 1W pin; the
pulse width must match the Baud rate (bit width)
of the expected return Baud rate from the QT300.
This pulse actually sets the Baud rate each time,
and so it can vary from one acquire to another. See
Section 4.3 and Figure 4-1.
Figure 4-1 UART and Trigger Pulse Signal.
back to the host. During idle times this pin floats and
therefore must be connected to a pullup resistor.
The DRDY line can be used as a Slave Select line (SS).
The host does not need this line to operate in many cases.
DRDY can be used to 'frame' byte transmissions.
2) The 1W pulse width is measured by the QT300 to
determine the Baud rate.
3) The host floats 1W high.
Between bytes /DRDY will go high for a period determined
by the MLS setup parameter; the minimum period is 8.3µs.
4) The QT300 acquires the signal to completion.
A typical Master mode SPI sequence is:
5) QT300 returns data in the following UART format:
start bit (low)
8 bits, high byte
stop bit (high)
delay (determined by MLS setup)
start bit (low)
8 bits, low byte
stop bit (high)
1) Host pulses /REQ low for ≥30µs.
2) QT300 acquires a signal in response to /REQ.
3) QT300 pulls /DRDY low when ready to send data.
4) Host detects /DRDY low and prepares to receive data.
5) QT300 clocks out first byte of data (MSB).
6) QT300 sets /DRDY high for a duration determined by
Setup parameter MLS.
6) The QT300 floats the 1W line and enters idle mode.
7) QT300 pulls /DRDY low.
8) QT300 clocks out the low byte (LSB).
9) QT300 releases /DRDY to float high.
LQ
5
QT300 R1.01 21/09/03
4.3 Trigger pulse description
5.3 PCB LAYOUT
The part wakes from low power mode when the first negative
edge is detected on the 1W pin (Figure 4-1, bottom). The
negative pulse must be at least 30µs wide.
5.3.1 GROUND PLANES
The use of ground planes around the device is encouraged
for noise reasons, but ground or power should not be
coupled too close to the sense pins in order to reduce Cx
load. Likewise, the traces leading from the sense pins to the
electrode should not be placed directly over a ground plane;
rather, the ground plane should be relieved by at least 3
times the width of the sense traces directly under it, with
periodic thin bridges over the gap to provide ground
continuity.
The host then generates the positive pulse that actually sets
the Baud rate. The QT300 measure this pulse and uses its
length to set the Baud bit (shift out) rate. 30µs (or more) of
logic-low must follow this pulse.
The host must then float the 1W line to allow the QT300 to
start the signal acquisition.
5 Circuit Guidelines
5.3.2 NOISE SYNCHRONIZATION
5.1 Sample capacitors
External fields can cause interference leading to a noisy and
unstable signal. The most common external fields usually are
from AC mains power.
Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The normal usable Cs range is
from 1nF ~ 500nF depending on the sensitivity required;
larger values of Cs require higher stability to ensure low drift.
Acceptable capacitor types include NP0 or C0G ceramic,
PPS film, and Y5E and X7R ceramics in that order.
The /REQ line of the QT300 can be used to synchronize the
acquisition to a repetitive external source of interference
such as the power line frequency in order to dramatically
reduce signal noise.
If line frequency is present near the sensors, this feature
should be used.
5.2 Power Supply
5.2.1 STABILITY
The QT300 makes use of the power supply as a reference
voltage. The acquired signal will shift slightly with changes in
Vdd; Vdd fluctuations often happen when additional loads
are switched on or off such as LEDs etc.
6 Parameter Setups Cloning
If the power supply is shared with another electronic system,
care should be taken to assure that the supply is free of
spikes, sags, and surges. It is best practice to use a
regulator just for the QT300 (or one for a set of QT300's).
The QTM300CA cloning board in conjunction with QT3View
software simplifies the Setups cloning process greatly. The
E3A eval board has been designed with a connector to
facilitate direct connection with the QTM300CA. The
QTM300CA in turn connects to any PC with a serial port
which can run QT3View software (included with the
QTM300CA and available free on Quantum’s web site).
A special interface is provided to allow user-defined Setups
to be loaded into internal eeprom or read back out for
development and production purposes.
5.2.2 SUPPLY REQUIREMENTS
Vdd can range from 2 to 5 volts nominal. Current drain will
vary depending on Vdd. During writing of the internal
EEPROM, Vdd must be at least 2.2 volts.
The connections required for cloning are shown in Figure
6-1. Further information on the cloning process can be found
in the QTM300CA instruction guide. The parameters which
can be altered are shown in Table 7-4.
If desired, the supply can be regulated using a conventional
regulator, for example CMOS LDO regulators, or standard
78Lxx-series 3-terminal devices.
The internal eeprom has a life expectancy of 100,000
erase/write cycles and the minimum voltage for a write cycle
is 2.2 Volts.
For proper operation a 100nF (0.1uF) ceramic bypass
capacitor must be used between Vdd and Vss; the bypass
cap should be placed very close to the Vdd and Vss pins.
A serial interface specification for the device can be obtained
by contacting Quantum.
DRDY
SCK
REQ
SDI
GND
SDI
SCK
SDO
Cloning Signal
Vdd
100nF
QT 300
8
Vcc
1
DRDY
2
6
7
SCK
SNS 1
REQ
SNS 2
3
5
SENSOR
CS
SDO
GND
4
Figure 6-1 Clone interface wiring
LQ
6
QT300 R1.01 21/09/03
7 Electrical specifications
7.1 ABSOLUTE MAXIMUM SPECIFICATIONS
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . as designated by suffix
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65OC to +125OC
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +6V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40mA
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to (Vdd + 0.5) Volts
7.2 RECOMMENDED OPERATING CONDITIONS
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2 to 5V
VDD min required to reprogram eeprom Setups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.2V
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV
Cs value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 to 500nF
Cx value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 100pF
7.3 AC SPECIFICATIONS
Vdd = 3.0, Ta = recommended operating range, Cs=100nF unless noted
Parameter
Description
Min
TPC
Charge/transfer duration
TBL
Burst length
0.5
Request pulse
30
TRQP
Typ
Max
Units
25
ms
830
Notes
ns
Cs = 4.7nF to 200nF; Cx = 0
µs
7.4 DC specifications
Vdd = 3.0V, Cs = 10nF, Cx = 5pF, Ta = recommended range, unless otherwise noted
Parameter
VDD
Description
Min
Supply voltage
2
IDD
Supply current
60
VIL
Input low voltage
VIH
Input high voltage
VOL
Low output voltage
VOH
High output voltage
AR
Acquisition resolution
S
Resolution per bit
LQ
Typ
Max
Units
5.5
V
1,500
µA
Dependent on duty cycle
0.3 Vdd
V
Vdd = 2.5 to 5.0V
V
Vdd = 2.5 to 5.0V
0.6 Vdd
0.4
Vdd-0.6
Notes
V
V
1,000
7
16
bits
7
fF
Figs 7-4, 7-5
QT300 R1.01 21/09/03
Tskd
Tskh
DRDY
{from QT300}
Tskl
SCK
{from host}
D15 D14 D13 D12 D11 D10 D9
SDO
{from QT300}
D8
D7
D6
D5
D4
D3
D2
D1
D0
Thso
Tds
Tmls
Tsosh
Figure 7-1 SPI Slave Mode
Tmls
Tskd
Tskh
DRDY
{from QT300}
Tskl
SCK
{from QT300}
SDO
{from QT300}
D15 D14 D13 D12 D11 D10 D9
D8
D7
Tds
D6
D5
D4
D3
D2
D1
D0
Thso
Tsosh
Figure 7-2 SPI Master Mode
Symbol
Parameter
min
max
Units
Symbol
Parameter
min
max
Units
TSKD
Clock Duration
25
-
µs
TSKD
Clock Duration
25
1,725
µs
TSKH
SCK High Duration
13
-
µs
TSKH
SCK High Duration
12.5
862.5
µs
TSKL
SCK Low Duration
SCK High To SDO Ready
Setup Time
SDO Hold Time
12
-
µs
TSKL
12.5
862.5
µs
-
10
µs
TSOSH
4
7
µs
7
-
µs
THSO
SCK Low Duration
SCK High To SDO Ready
Setup Time
SDO Hold Time
12.5
-
-
MSB-LSB Spacing
DRDY Low To SCK High
Delay
12
1,000
µs
TMLS
8.3
1,708
µs
12
1,000
µs
TDS
MSB-LSB Spacing
DRDY Low To SCK High
Delay
12.5
-
-
TSOSH
THSO
TMLS
TDS
Table 7-1
LQ
Slave SPI Timing
Table 7-2
8
Master SPI Timing
QT300 R1.01 21/09/03
1W UART
Tacq
Twu
Tmls
8bits MSB
8bits LSB
Tbr
Tsb
Tstop
Tstart
Figure 7-3 1W UART Mode
Symbol
Twu
Tbr
Tsb
Tacq
Tstart
Parameter
Wake level
Baud set pulse
Baud end level
Baud rate range
Baud rate match accuracy
Acquisition time
Start pulse
Tstop
Tmls
MSB
LSB
Stop pulse
MSB-LSB spacing
-
min
30
104
30
4,800
max
5,000
210
5,000
9,600
2
400
Tbr
Notes
Depends on Cs and Cx
-
Tbr
8
850
8 x Tbr
8 x Tbr
Units
µs
µs
µs
-
%
ms
µs
µs
µs
8 bits data, LSB first
Table 7-3 1W UART Timing
Description
Mode
Symbol
SM
Valid Values
0
1W UART
1
Master Clock
Idle Low
2
Master Clock
Idle High
3
Slave Clock
Idle Low
4
Slave Clock
Idle High
Default
Calculation / Notes
Unit
Slave Clock
Idle Low
-
-
3
Clock Speed
SCD
0 - 255
55
Tscd = (30 + (SCD x 8))/1.2
µs
MSB-LSB
Spacing
MLS
0 - 255
148
Tmls = (10 + (MLS x 4))/1.2
µs
Table 7-4 Setups summary chart
LQ
9
QT300 R1.01 21/09/03
150
500
400
Resolution Per Count (fF)
Resolution Per Count (fF)
Cs
125
Cs
9nF
19nF
43nF
300
74nF
124nF
200nF
200
100
43nF
74nF
100
124nF
200nF
75
50
25
0
0
0
11
21
34
0
48
11
21
34
48
Cx Load
Cx Load
Figure 7-5 Typical resolution vs Cx & Cs;
Vdd = 3.0 Volts
Figure 7-4 Typical resolution vs Cx & Cs;
Vdd = 3.0 Volts
5.00%
4.00%
3.00%
% Deviation
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
-10 -5
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Temperature, C
Figure 7-6 Typical Signal Deviation vs. Temperature
Vdd = 5.0 Volts, Cx = 10pF, Cs = 5~200nF PPS Film
6000
Signal, Counts
5000
200nF PPS
4000
100nF PPS
4.7nF PPS
3000
2000
1000
0
-10
0
10
20
30
40
50
Temperature, °C
60
70
80
Figure 7-7 Typical Signal Vs. Cs & Temp
Vdd = 5.0 Volts, Cx = 10pF, PPS film capacitors
LQ
10
QT300 R1.01 21/09/03
M
A
F
S1
a A
r
S
L2
Pin 1
x
m
L1
Q
L
Package type: 8-pin Dual-In-Line
SYMBOL
Millimeters
Max
Min
a
A
M
m
Q
L
L1
L2
F
r
S
S1
x
6.1
7.62
9.02
7.62
0.69
0.356
1.14
0.203
2.54
0.38
2.92
-
7.11
8.26
10.16
0.94
0.559
1.78
0.305
3.81
5.33
10.9
Notes
Inches
Max
Min
0.24
0.3
0.355
0.3
0.027
0.014
0.045
0.008
0.1
0.015
0.115
-
Typical
BSC
0.28
0.325
0.4
0.037
0.022
0.07
0.012
0.15
0.21
0.43
Notes
Typical
BSC
M
M
a
H
A
φ
e
h
Pin 1
E
F
L
Package type: 8-pin Wide SOIC
SYMBOL
a
A
M
F
L
h
H
e
E
φ
Min
5.21
7.62
5.16
1.27
0.305
0.102
1.78
0.178
0.508
0o
LQ
Millimeters
Max
5.41
8.38
5.38
0.508
0.33
2.03
0.254
0.889
8o
Notes
BSC
11
Min
0.205
0.3
0.203
0.05
0.012
0.004
0.07
0.007
0.02
0o
Inches
Max
0.213
0.33
0.212
0.02
0.013
0.08
0.01
0.035
8o
Notes
BSC
QT300 R1.01 21/09/03
lQ
Copyright © 2002 QRG Ltd. All rights reserved.
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
[email protected]
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject
to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order
acknowledgement. QProx, QTouch, QMatrix, QLevel, and QSlide are trademarks of QRG. QRG products are not suitable for medical
(including life-saving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's
Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection
with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely
responsible for their products and applications which incorporate QRG's products.