SSM1333GU P-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS -20V R DS(ON) 600mΩ ID -550mA DESCRIPTION The SSM1333GU acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as drivers, high-side line and general load-switching circuits. Pb-free; RoHS-compliant SOT-323/SC-70 D The SSM1333GU is supplied in an RoHS-compliant SOT-323/SC-70 package, which is widely used for low power commercial and industrial surface mount applications. S SOT-323/SC-70 G ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDS Drain-source voltage VGS Gate-source voltage ID IDM PD Continuous drain current Pulsed drain current 3 , Value Units -20 V ± 12 V T A = 25°C -550 mA TA = 70°C -440 mA -2.5 A 0.35 W 0.003 W/°C 1,2 3 Total power dissipation , TA = 25°C Linear derating factor TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol RΘJA Parameter Maximum thermal resistance, junction-ambient 3 Value Units 360 °C/W Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on FR4 board, t < 10 sec. 11/26/2005 Rev.3.01 www.SiliconStandard.com 1 of 5 SSM1333GU ELECTRICAL CHARACTERISTICS Symbol (at Tj = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. Max. Unit -20 - - V BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA - 0.01 - V/°C RDS(ON) Static Drain-Source On-Resistance VGS=-10V, ID=-550mA - - 600 mΩ VGS=-4.5V, ID=-500mA - - 800 mΩ VGS=-2.5V, ID=-300mA - - 1000 mΩ VGS=0V, ID=-250uA VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -0.5 - -1.2 V gfs Forward Transconductance VDS=-5V, ID=-500mA - 1 - S IDSS Drain-Source Leakage Current VDS=-20V, VGS=0V - - -1 uA VDS=-16V ,VGS=0V, Tj=70°C - - -10 uA VGS=±12V - - ±100 nA ID=-500mA - 1.7 2.7 nC IGSS Gate-Source Leakage 2 Qg Total Gate Charge Qgs Gate-Source Charge VDS=-16V - 0.3 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 0.4 - nC VDS=-10V - 5 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=-500mA - 8 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=-5V - 10 - ns tf Fall Time RD=20Ω - 2 - ns Ciss Input Capacitance VGS=0V - 66 105.6 pF Coss Output Capacitance VDS=-10V - 25 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 20 - pF Min. Typ. Max. Unit - - -1.2 V Source-Drain Diode Symbol VSD Parameter 2 Forward On Voltage Test Conditions IS=-300mA, VGS=0V Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 11/26/2005 Rev.3.01 www.SiliconStandard.com 2 of 5 SSM1333GU 2.5 2.5 - 5.0V - 4.5V - 3.5V T A =25 C -ID , Drain Current (A) 2.0 1.5 2.0 -3.5V - 2.5V 1.0 V G = - 2.0V 1.5 -2.5V 1.0 V G = - 2.0V 0.5 0.5 0.0 0.0 0.0 0.5 1.0 1.5 2.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical output characteristics Fig 2. Typical output characteristics 1.6 1400 I D = - 0. 3 A 1200 I D = - 0. 5 A V G = - 4.5V 1.4 Normalized RDS(ON) T A =25 o C 1000 RDS(ON) (mΩ ) -5.0V -4.5V T A = 150 o C -ID , Drain Current (A) o 800 600 1.2 1.0 0.8 400 200 0.6 1 4 7 10 -50 0 50 100 150 T j , Junction Temperature ( o C) -V GS , Gate-to-Source Voltage (V) Fig 3. On-resistance vs. gate voltage Fig 4. Normalized on-resistance vs. junction temperature 1.0 2.0 0.8 Normalized -VGS(th) (V) 1.5 0.6 -IS(A) T j =150 o C T j =25 o C 0.4 1.0 0.5 0.2 0.0 0.0 0 0.2 0.4 0.6 0.8 1 -V SD , Source-to-Drain Voltage (V) Fig 5. Forward characteristics of the reverse diode 11/26/2005 Rev.3.01 1.2 -50 0 50 100 150 T j , Junction Temperature ( o C) Fig 6. Gate threshold voltage vs. junction temperature www.SiliconStandard.com 3 of 5 SSM1333GU f=1.0MHz 100 I D =-0.5A V DS =-16V 10 C iss 8 C (pF) -VGS , Gate to Source Voltage (V) 12 6 C oss 4 C rss 2 0 10 0 1 2 3 4 1 3 Q G , Total Gate Charge (nC) 5 7 9 11 -V DS , Drain-to-Source Voltage (V) Fig 7. Gate charge characteristics Fig 8. Typical capacitance characteristics 10 1 Normalized Thermal Response (Rthja) Duty factor=0.5 100us -ID (A) 1 1ms 0.1 10ms 100ms DC o T A =25 C Single Pulse 0.01 0.2 0.1 0.05 0.1 0.02 PDM 0.01 t T Single Pulse Duty factor = t/T Peak Tj = PDM x Rthja + T a 0.01 0.1 1 10 100 0.0001 0.001 0.01 -V DS , Drain-to-Source Voltage (V) Fig 9. Maximum safe operating area 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective transient thermal impedance VG VDS 90% QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching time waveform 11/26/2005 Rev.3.01 Charge Q Fig 12. Gate charge waveform www.SiliconStandard.com 4 of 5 SSM1333GU PHYSICAL DIMENSIONS SOT-23-3 SOT-23-3 SYMBOL MILLIMETERS MIN. MAX. A 0.89 1.45 A1 0 0.15 A2 0.70 1.30 b 0.30 0.50 c 0.08 0.25 D 2.65 3.10 E 2.10 3.00 E1 1.19 2.30 e 0.95BSC e1 1.90BSC L 0.30 L1 Θ 0.60 0.60REF 0° 8° *Dimensions do not include mold protrusions. PART MARKING PART NUMBER CODE: ND = SSM2310GN NDXX XX = DATE/LOT CODE For a detailed explanation of these codes, please contact SSC directly. PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a reel packed in a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/26/2005 Rev.3.01 www.SiliconStandard.com 5 of 5