SSM9567GM P-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS -40V R DS(ON) 50mΩ ID -6A DESCRIPTION The SSM9567GM acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM9567GM is supplied in an RoHS-compliant SO-8 package, which is widely used for medium power commercial and industrial surface mount applications. Pb-free; RoHS-compliant SO-8 D D D D G SO-8 S S S ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units VDS Drain-source voltage -40 V VGS Gate-source voltage ±25 V ID Continuous drain current, TC = 25°C -6 A -4.8 A -30 A 2.5 W 0.02 W/°C TC = 70°C 1 IDM Pulsed drain current PD Total power dissipation, TC = 25°C Linear derating factor TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol RΘ JA Parameter Maximum thermal resistance, junction-ambient 3 Value Units 50 °C/W Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 125°C/W when mounted on the minimum pad area required for soldering. 9/27/2006 Rev.3.01 www.SiliconStandard.com 1 of 5 SSM9567GM ELECTRICAL CHARACTERISTICS Symbol (at Tj = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. -40 - BVDSS Drain-source breakdown voltage VGS=0V, ID=-250uA ∆ BV DSS/∆ Tj Breakdown voltage temperature coefficient Reference to 25°C, ID=-1mA - RDS(ON) Static drain-source on-resistance2 VGS=-10V, ID=-6A VGS(th) Gate threshold voltage Max. Units - V -0.03 - V/°C - - 50 mΩ VGS=-4.5V, ID=-4A - - 80 mΩ VDS=VGS, ID=-250uA -1 - -3 V - 9 - S gfs Forward transconductance VDS=-10V, ID=-6A IDSS Drain-source leakage current VDS=-40V, VGS=0V, Tj = 25°C - - -1 uA VDS=-32V ,VGS=0V, Tj = 70°C - - -25 uA VGS=±25V - - ±100 nA ID=-6A - 11 18 nC IGSS Gate-source leakage current 2 Qg Total gate charge Qgs Gate-source charge VDS=-32V - 3 - nC Qgd Gate-drain ("Miller") charge VGS=-4.5V - 5 - nC VDS=-20V - 10 - ns 2 td(on) Turn-on delay time tr Rise time ID=-1A - 5 - ns td(off) Turn-off delay time RG=3.3Ω , VGS=-10V - 30 - ns tf Fall time RD=20Ω - 6 - ns Ciss Input capacitance VGS=0V - 880 1400 pF Coss Output capacitance VDS=-25V - 135 - pF Crss Reverse transfer capacitance f=1.0MHz - 110 - pF Rg Gate resistance f=1.0MHz - 5 8 Ω Min. Typ. - - -1.2 V Source-Drain Diode Symbol VSD Parameter 2 Forward voltage Test Conditions IIS=-2A, VGS=0V Max. Units trr Reverse-recovery time IS=-6A, VGS=0V, - 24 - ns Qrr Reverse-recovery charge dI/dt=100A/µs - 21 - nC 2 Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 9/27/2006 Rev.3.01 www.SiliconStandard.com 2 of 5 SSM9567GM 50 50 -10V -7.0V - 5.0V T A = 25 C -ID , Drain Current (A) 40 30 T A = 150°C -4.5V 20 V G = -3.0 V 10 - 5.0V 30 -4.5V 20 V G = -3.0 V 10 0 0 0 2 4 6 8 0 2 Fig 1. Typical Output Characteristics 6 8 Fig 2. Typical Output Characteristics 65 1.6 ID=-6A V G =-10V Normalized R DS(ON) ID=-4A T A =25°C RDS(ON) (mΩ) 4 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) 55 45 1.2 0.8 0.4 35 2 4 6 8 -50 10 0 50 100 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 150 o 1.7 Normalized -VGS(th) (V) 6 -IS(A) 4 T j =150 o C T j =25 o C 2 1.2 0.7 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 -V SD , Source-to-Drain Voltage (V) Fig 5. Forward Characteristic of Reverse Diode 9/27/2006 Rev.3.01 -10V -7.0V 40 -ID , Drain Current (A) o 50 100 150 o T j , Junction Temperature ( C) Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9567GM f=1.0MHz 10000 I D = -6A V DS = -32V 10 8 C (pF) -VGS , Gate to Source Voltage (V) 12 6 1000 C iss 4 2 C oss C rss 100 0 0 5 10 15 20 1 25 5 9 Q G , Total Gate Charge (nC) 13 17 21 25 29 -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1 Normalized Thermal Response (Rthja) 100 10 1ms 10ms -ID (A) 1 100ms 1s 0.1 T A =25 o C Single Pulse Duty factor=0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t Single Pulse T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W DC 0.001 0.01 0.1 1 10 100 0.0001 0.001 -V DS , Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 30 VG -ID , Drain Current (A) V DS =-5V T j =25 o C QG T j =150 o C 20 -4.5V QGS QGD 10 Charge Q 0 0 2 4 6 8 -V GS , Gate-to-Source Voltage (V) Fig 11. Transfer Characteristics 9/27/2006 Rev.3.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9567GM PHYSICAL DIMENSIONS D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e e A A1 C B L 1.27(TYP) H 5.80 6.50 L 0.38 1.27 All dimensions in millimeters. Dimensions do not include mold protrusions. PART MARKING PART NUMBER: 9567GM = SSM9567GM 9567GM YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/27/2006 Rev.3.01 www.SiliconStandard.com 5 of 5