SSM2314GN
N-channel Enhancement-mode Power MOSFET
Low gate-charge
D
Simple drive requirement
Fast switching
G
Pb-free; RoHS compliant.
BV DSS
20V
R DS(ON)
75mΩ
ID
3.5A
S
DESCRIPTION
D
The SSM2314GN is in a SOT-23-3 package, which is widely used for lower
power commercial and industrial surface mount applications. This device is
suitable for low-voltage applications such as DC/DC converters and and
general switching applications.
S
SOT-23-3
G
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
20
V
± 12
V
Continuous Drain Current
3
3.5
A
Continuous Drain Current
3
2.8
A
1,2
IDM
Pulsed Drain Current
10
A
PD @ TA=25°C
Total Power Dissipation
1.38
W
Linear Derating Factor
0.01
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
THERMAL DATA
Symbol
RΘJA
4/16/2005 Rev.2.1
Parameter
Maximum Thermal Resistance, Junction-ambient
3
www.SiliconStandard.com
Value
Unit
90
°C/W
1 of 5
SSM2314GN
ELECTRICAL CHARACTERISTICS (at Tj = 25°C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
20
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.02
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance
VGS=4.5V, ID=3.5A
-
-
75
mΩ
VGS=2.5V, ID=1.2A
-
-
125
mΩ
VDS=VGS, ID=250uA
0.5
-
1.2
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=5V, ID=3A
-
7
-
S
o
VDS=20V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=16V ,VGS=0V
-
-
10
uA
Gate-Source Leakage
VGS=±12V
-
-
±100
nA
ID=3A
-
4
7
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=16V
-
0.7
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
2
-
nC
VDS=15V
-
6
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
8
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω , VGS=5V
-
10
-
ns
tf
Fall Time
RD=15Ω
-
3
-
ns
Ciss
Input Capacitance
VGS=0V
-
230
370
pF
Coss
Output Capacitance
VDS=20V
-
55
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
40
-
pF
Rg
Gate Resistance
f=1.0MHz
-
1.1
1.7
Ω
Min.
Typ.
Source-Drain Diode
Symbol
Parameter
2
Test Conditions
Max. Units
VSD
Forward On Voltage
IS=1.2A, VGS=0V
-
-
1.2
V
trr
Reverse Recovery Time
IS=3A, VGS=0V,
-
16
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
8
-
nC
Notes:
1.Pulse width limited by maximum junction temperature.
2.Pulse width <300us, duty cycle <2%.
3.Surface-mounted on 1 in2 copper pad on FR4 board , t < 10sec ; 270°C/W when mounted on minimum copper pad.
4/16/2005 Rev.2.1
www.SiliconStandard.com
2 of 5
SSM2314GN
15
15
5.0V
4.5V
3.0V
ID , Drain Current (A)
5.0V
4.5V
o
T A = 150 C
ID , Drain Current (A)
o
T A =25 C
10
2.5V
5
10
3.0 V
2.5V
5
V G = 1 .5V
V G = 1. 5V
0
0
0
1
2
0
3
2
3
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
1.6
I D =1.2A
I D = 3.5 A
V G =4.5V
1.4
o
Normalized R DS(ON)
T A =25 C
RDS(ON) (mΩ )
1
80
60
1.2
1.0
0.8
0.6
40
2
4
6
8
-50
10
0
100
150
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
0.8
Normalized VGS(th) (V)
3
2
IS(A)
o
o
T j =150 C
T j =25 C
1
0
0.7
0.6
0.5
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
Fig 5. Forward Characteristic of
Reverse Diode
50
100
150
T j , Junction Temperature ( o C)
V SD , Source-to-Drain Voltage (V)
4/16/2005 Rev.2.1
50
o
V GS , Gate-to-Source Voltage (V)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
www.SiliconStandard.com
3 of 5
SSM2314GN
f=1.0MHz
1000
I D =3A
10
C iss
V DS =10V
V DS =12V
V DS =16V
8
6
C (pF)
VGS , Gate to Source Voltage (V)
12
100
C oss
4
C rss
2
0
10
0
2
4
6
8
1
5
9
13
17
21
25
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Normalized Thermal Response (Rthja)
Duty factor=0.5
10
ID (A)
1ms
1
10ms
0.1
100ms
1s
T A =25 o C
Single Pulse
DC
0.01
0.2
0.1
0.1
0.05
PDM
t
0.01
0.01
Single Pulse
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja = 270°C/W
0.001
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
15
VG
ID , Drain Current (A)
V DS =5V
T j =25 o C
10
QG
T j =150 o C
4.5V
QGS
QGD
5
Charge
Q
0
0
2
4
6
V GS , Gate-to-Source Voltage (V)
Fig 11. Transfer Characteristics
4/16/2005 Rev.2.1
Fig 12. Gate Charge Circuit
www.SiliconStandard.com
4 of 5
SSM2314GN
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
4/16/2005 Rev.2.1
www.SiliconStandard.com
5 of 5