STMICROELECTRONICS STSJ25NF3LL

STSJ25NF3LL
N-CHANNEL 30V - 0.0085 Ω - 25A PowerSO-8™
LOW GATE CHARGE STripFET™ II POWER MOSFET
TYPE
STSJ25NF3LL
■
■
■
■
■
VDSS
RDS(on)
ID
30 V
<0.0105 Ω
25 A
TYPICAL RDS(on) = 0.0085 Ω @ 10V
TYPICAL Qg = 24 nC @ 4.5 V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
IMPROVED JUNCTION-CASE THERMAL
RESISTANCE
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique “Single Feature
Size™” strip-based process. This silicon, housed
in thermally improved SO-8™ package, exhibits
optimal on-resistance versus gate charge tradeoff plus lower R thj-c.
PowerSO-8™
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS FOR MOBILE PCS
DRAIN CONTACT ALSO ON THE BACKSIDE
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
VGS
Parameter
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage
Value
Unit
30
V
30
V
± 16
V
ID
Drain Current (continuous) at TC = 25°C (*)
25
A
ID
Drain Current (continuous) at TC = 25°C (#)
12
A
ID
Drain Current (continuous) at TC = 100°C
16
A
Drain Current (pulsed)
100
A
Total Dissipation at TC = 25°C
Total Dissipation at TC = 25°C (#)
70
3
W
W
IDM(•)
Ptot
(•) Pulse width limited by safe operating area.
(*) Value limited by wires bonding
October 2003
NEW DATASHEET ACCORDING TO PCN DSG/CT/2C13 MARKING: 25NF3LL@
1/8
STSJ25NF3LL
THERMAL DATA
Rthj-c
Rthj-amb
Tj
Tstg
Thermal Resistance Junction-case
(*)Thermal Resistance Junction-ambient
Maximum Operating Junction Temperature
Storage Temperature
Max
Max
1.8
42
150
-55 to 150
°C/W
°C/W
°C
°C
(*) When mounted on FR-4 board with 0.5 in2 pad of Cu.
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)
OFF
Symbol
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating TC = 125°C
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 16 V
V(BR)DSS
Min.
Typ.
Max.
30
Unit
V
1
10
µA
µA
±100
nA
Max.
Unit
ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
VGS = 4.5 V
ID = 12.5 A
ID = 12.5 A
Min.
Typ.
1
V
0.0085
0.011
0.0105
0.013
Ω
Ω
Typ.
Max.
Unit
DYNAMIC
Symbol
2/8
Parameter
Test Conditions
gfs (*)
Forward Transconductance
VDS=15 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
ID = 12.5 A
Min.
20
S
1650
540
130
pF
pF
pF
STSJ25NF3LL
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
ID = 12.5 A
VDD = 15 V
RG = 4.7 Ω
VGS = 4.5 V
(Resistive Load, Figure 1)
23
156
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD=15V ID=25A VGS=4.5V
24
8.5
12
33
nC
nC
nC
Typ.
Max.
Unit
(see test circuit, Figure 2)
ns
ns
SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
ID = 12.5 A
VDD = 15 V
RG = 4.7Ω,
VGS = 4.5 V
(Resistive Load, Figure 3)
27
28
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 25 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
di/dt = 100A/µs
ISD = 25 A
VDD = 25 V
Tj = 150°C
(see test circuit, Figure 3)
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
VGS = 0
40
50
2.5
Max.
Unit
25
100
A
A
1.2
V
ns
nC
A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/8
STSJ25NF3LL
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STSJ25NF3LL
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature.
.
.
5/8
STSJ25NF3LL
Fig. 1: Switching Times Test Circuits For Resistive
Load
Fig. 3: Test Circuit For Diode Recovery Behaviour
6/8
Fig. 2: Gate Charge test Circuit
STSJ25NF3LL
7/8
STSJ25NF3LL
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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