S1008C3E 1008C9E WCFS1008C3E WCFS1008C9E 128K x 8 Static RAM Features • High speed — tAA = 15 ns • 2.0V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options Functional Description The WCF1008C3E and WCFS1008C9E are high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The WCFS1008C3E is available in standard 300-mil-wide SOJ. The WCFS1008C9E is available in standard 400-milwide SOJ. The WCFS1008C3E and WCFS1008C9E are functionally equivalent in all other respects.. Logic Block Diagram Pin Configurations SOJ I/O0 INPUT BUFFER I/O1 I/O2 512 x 256 x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O4 I/O5 OE COLUMN DECODER POWER DOWN I/O6 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 CE1 CE2 WE Top View NC A16 A14 A12 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) WCFS1008C3E WCFS1008C9E 15ns 15 80 10 Revised April 12, 2002 WCFS1008C3E WCFS1008C9E Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range [1] Supply Voltage on VCC to Relative GND .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Commercial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% DC Input Voltage[1].................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Test Conditions Parameter Description WCFS1008C3E WCFS1008C9E 15ns Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 80 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX 40 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE1 > VCC – 0.3V, or CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 mA 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.3 0.8 V Capacitance[ 4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 9 pF 8 pF Note: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Page 2 of 8 WCFS1008C3E WCFS1008C9E AC Test Loads and Waveforms R1 480Ω R1 480 Ω 5V ALL INPUT PULSES 5V OUTPUT 3.0V 90% OUTPUT R2 255Ω 30 pF R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) GND 90% 10% 10% ≤ 3 ns ≤ 3 ns THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Switching Characteristics[5] Over the Operating Range WCFS1008C3E WCFS1008C9E-15 Parameter Description Min. Max. Unit 15 ns READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 15 tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6, 7] 3 15 7 3 [6, 7] tHZCE CE1 HIGH to High Z, CE2 LOW to High Z tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up ns ns ns 7 0 CE1 HIGH to Power-Down, CE2 LOW to Power-Down ns ns 7 CE1 LOW to Low Z, CE2 HIGH to Low Z tPD ns 0 [7] tLZCE ns ns ns 15 ns [8] WRITE CYCLE tWC Write Cycle Time[9] 15 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 12 ns tAW Address Set-Up to Write End 12 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 12 ns tSD Data Set-Up to Write End 8 ns tHD Data Hold from Write End 0 ns Z[7] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[6, 7] 3 ns 7 ns Note: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD Page 3 of 8 WCFS1008C3E WCFS1008C9E Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Min. No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE1 > VCC – 0.3V or CE2 < 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Max Unit 2.0 V 0 ns 200 µs Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V VDR > 2V tCDR tR CE Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Note: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Page 4 of 8 WCFS1008C3E WCFS1008C9E Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled)[10, 14] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[10, 14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied. Page 5 of 8 WCFS1008C3E WCFS1008C9E Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE tSD NOTE 15 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 OE WE I/O0 – I/O7 Mode Power H X X X High Z Power-Down Standby (ISB) X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 15 Ordering Code Package Name Package Type WCFS1008C3E-JC15 J 32-Lead (300-Mil) Molded SOJ WCFS1008C9E-JC15 J 32-Lead (400-Mil) Molded SOJ Operating Range Commercial Page 6 of 8 WCFS1008C3E WCFS1008C9E Package Diagrams 32-Lead (300-Mil) Molded SOJ J 32-Lead (400-Mil) Molded SOJ J Page 7 of 8 WCFS1008C3E WCFS1008C9E Document Title: WCFS1008C3E WCFS1008C9E 128K x 8 SRAM REV. Issue Date Orig. of Change Description of Change ** 4/12/02 XFL NEW DATASHEET Page 8 of 8