WEIDA WCMS0808U1X

S0808U1X
WCMS0808U1X
32K x 8 Static RAM
Features
• Low voltage range:
— 2.7V − 3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMS0808U1X is composed of a high-performance
CMOS static RAM organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state drivers. These devices have an automatic power-down feature,
reducing the power consumption by over 99% when deselected. The WCMS0808U1X is available in the 450-mil-wide
(300-mil body width) narrow SOIC and TSOP.
An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
Pin Configurations
Narrow
SOIC
Top View
I/O0
INPUTBUFFER
512x512
ARRAY
SENSE AMPS
I/O1
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
A 12
A 11
A1
A0
A 14
A 13
OE
POWER
DOWN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O6
I/O7
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
WCMS0808U1X
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied................................................... 0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +4.6V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Industrial
DC Voltage Applied to Outputs
in High Z State[1] ........................................ −0.5V to VCC + 0.5V
Ambient Temperature
−40°C to +85°C
VCC
2.7V to 3.6V
Product Portfolio
Power Dissipation (LL Devices)
Product
WCMS0808U1X
VCC Range
Speed
Min.
Typ.
Max.
2.7V
3.0
3.6V
70 ns
Operating (ICC)
Standby (ISB2)
Typ.
Max.
Typ.
Max.
11 mA
30 mA
0.1 µA
40 µA
Electrical Characteristics Over the Operating Range
WCMS0808U1X
Parameter
Description
Test Conditions
Typ.[1]
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
VCC = 3.6V,
IOUT = 0 mA,
f = fMAX = 1/tRC
Ind’l
ISB1
Automatic CE Power-Down
Current— TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
Max.
2.4
Unit
V
0.4
V
2.2
VCC
+0.3V
V
−0.5
0.8
V
−1
+1
µA
−1
+1
µA
11
30
mA
Ind’l
100
300
µA
Ind’l
0.1
40
µA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Max.
Unit
6
pF
8
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = Vcc Typ., TA = 25°C, and tAA=70ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Page 2 of 10
WCMS0808U1X
AC Test Loads and Waveforms
R1
Vcc
ALL INPUT PULSES
OUTPUT
Vcc
10%
R2
50 pF
GND
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
90%
10%
90%
THÉVENIN EQUIVALENT
Rth
OUTPUT
Vth
Parameters
3.3 V
Unit
R1
1103
KOhms
R2
1554
KOhms
RTH
645
KOhms
VTH
1.75V
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions[4]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data
Retention Time
tR[3]
Operation Recovery
Time
Min.
Typ.[2]
Max.
1.4
VCC = 1.6
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Unit
V
0.1
6
uA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
1.8V
tCDR
VDR > 1.4V
1.8V
tR
CE
Page 3 of 10
WCMS0808U1X
Switching Characteristics Over the Operating Range[5]
WCMS0808U1X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[6]
tHZOE
70
OE HIGH to High Z
tLZCE
CE LOW to Low Z
10
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
70
ns
35
ns
ns
25
10
[6, 7]
ns
ns
25
0
CE HIGH to Power-Down
ns
ns
5
[6, 7]
[6]
ns
70
ns
ns
70
ns
[8,9]
WRITE CYCLE
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-Up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
[6, 7]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z[6]
25
10
ns
ns
Notes:
4. No input may exceed VCC+0.3V.
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output
loading of the specified IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
Page 4 of 10
WCMS0808U1X
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [11, 12]
t RC
CE
tACE
OE
t HZOE
tHZCE
tDOE
DATA OUT
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
t PD
t PU
ICC
50%
50%
ISB
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Page 5 of 10
WCMS0808U1X
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[8, 13, 14]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
t PWE
OE
tSD
DATA I/O
NOTE 15
tHD
DATAINVALID
t HZOE
Write Cycle No. 2 (CE Controlled) [8, 13, 14]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
t HD
DATAINVALID
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
Page 6 of 10
WCMS0808U1X
Switching Waveforms (continued)
[ 9, 14]
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
CE
tAW
t HA
tSA
WE
tSD
DATA I/O
NOTE 15
t HD
DATA INVALID
tLZWE
t HZWE
Truth Table
Inputs/Outputs
Mode
Power
CE
WE
OE
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, Output Disabled
Active (ICC)
Page 7 of 10
WCMS0808U1X
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Name
Package Type
WCMS0808U1X -NF70
N28
28-Lead 450-Mil (300-Mil Body Width) narrow SOIC
WCMS0808U1X-TF70
T28
28-Lead Thin Small Outline Package
Operating
Range
Industrial
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC, N28
Page 8 of 10
WCMS0808U1X
Package Diagrams (continued)
28-Lead Thin Small Outline Package, T28
Page 9 of 10
WCMS0808U1X
Document Title: WCMS0808U1X, 32K x 8 Static RAM
REV.
Spec #
ECN #
Issue Date
Orig. of Change
Description of Change
**
38-14009
115224
1/17/02
MGN
New Datasheet
Page 10 of 10