WEIDA WCMS0808C1X

S0808C1X
WCMS0808C1X
32Kx8 Static RAM
Features
• Low Voltage Range
— 4.5V–5.5V Operation
• Low active power
— 275 mW (max.)
• Low standby power
— 28 µW (max.)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMS0808C1X is a high-performance CMOS static
RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active
LOW output enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption
by
99.9%
when
deselected.
The
WCMS0808C1X is in the standard 450-mil-wide (300-mil body
width) SOIC and packages.
An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
Pin Configurations
Narrow SOIC
Top View
I/O0
INPUTBUFFER
512x512
ARRAY
SENSE AMPS
I/O1
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
A 12
A 11
A1
A0
A 13
A 14
OE
POWER
DOWN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O6
I/O7
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
WCMS0808C1X
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied................................................... 0°C to +70°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +7.0V
Range
Ambient Temperature
VCC
–40°C to +85°C
5V ± 10%
Industrial
DC Voltage Applied to Outputs
in High Z State[1] ........................................ −0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
WCMS0808C1X
Parameter
Description
Test Conditions
Min.
2.4
Typ[2]
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
0.4
V
VIH
Input HIGH Voltage
2.2
VCC
+0.5V
V
VIL
Input LOW Voltage
−0.5
0.8
V
IIX
Input Load Current
GND < VI < VCC
−0.5
+0.5
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
−0.5
+0.5
µA
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
25
50
mA
ISB1
Automatic CE
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
0.3
0.5
mA
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC − 0.3V
VIN > VCC − 0.3V
or VIN < 0.3V, f = 0
0.1
10
µA
V
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
6
pF
8
pF
Note:
1. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
3. Tested initially and after any design or process changes that may affect these parameters.
*
WCMS0808C1X
AC Test Loads and Waveforms
R1 1800 Ω
R1 1800 Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
3.0V
GND
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
990Ω
5 pF
90%
10%
90%
10%
(b)
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Conditions[4]
Description
VDR
VCC for Data Retention
VCC = 3.0V,
CE > VCC − 0.3V,
VIN > VCC − 0.3V or
VIN < 0.3V
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data
Retention Time
tR[3]
Operation Recovery
Time
Min.
Typ.[2]
Max.
2.0
V
0.1
10
ns
tRC
ns
DATA RETENTION MODE
3.0V
tCDR
CE
Note:
4. No input may exceed VCC+0.5V.
*
VDR > 2V
µA
0
Data Retention Waveform
VCC
Unit
3.0V
tR
WCMS0808C1X
Switching Characteristics Over the Operating Range[10]
WCMS0808C1X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low
70
Z[6]
70
5
OE HIGH to High
tLZCE
CE LOW to Low Z[6]
tHZCE
CE HIGH to High
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
ns
25
5
Z[6, 7]
ns
ns
5
Z[6, 7]
tHZOE
ns
ns
ns
25
0
ns
ns
70
ns
WRITE CYCLE[8, 9]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-Up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to High
Z[6, 7]
WE HIGH to Low
Z[6]
25
5
ns
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
*
WCMS0808C1X
Switching Waveforms
Read Cycle No. 1 [10,11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
Read Cycle No. 2 [11,12]
DATA VALID
tRC
CE
tACE
OE
DATA OUT
tDOE
tLZOE
HIGH IMPEDANCE
tHZOE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
*
50%
ISB
WCMS0808C1X
Switching Waveforms (continued)
[8,13,14]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 15
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)
[8,13,14]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
DATAIN VALID
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
*
tHD
WCMS0808C1X
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[9,14]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tLZWE
tHZWE
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
Truth Table
CE
*
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, Output Disabled
Active (ICC)
WCMS0808C1X
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Name
Package Type
WCMS0808C1X–NF70
N28
28-Lead 450-Mil (300-Mil Body Width) Narrow SOIC
WCMS0808C1X–TF70
T28
28-Lead Thin Small Outiline Package (TSOP)
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC, N28
*
Operating
Range
Industrial
WCMS0808C1X
Package Diagrams (continued)
28-Lead Thin Small Outline Package, T28
*
WCMS0808C1X
32Kx8 Static RAM
Document Title: WCMS0808C1X, 32K x 8 Static RAM
Spec #
ECN #
Issue Date
Orig. of
Change
Description
of Change
38-14010
115225
1/17/02
MGN
New
Datasheet
REV.
**