A1008U1X WCMA1008U1X 128K x 8 Static RAM Features ic power-down feature, reducing the power consumption by over 99% when deselected. • High Speed — 55ns and 70ns availability • Voltage range — 2.7V–3.6V • Ultra low active power — Typical active current: 20 mA @ f = fmax (70ns speed) • Low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Functional Description The WCMA1008U1X is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE) and three-state drivers. These devices have an automat- The WCMA1008U1X is available in a 32 Lead TSOP and STSOP packages. Logic Block Diagram Pin Configurations I/O0 INPUT BUFFER OE SENSE AMPS 512x 256x 8 ARRAY I/O2 I/O3 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 A9 A 10 A 11 A12 A13 A14 A15 A16 CE1 CE2 WE I/O1 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 STSOP Top View (not to scale) TSOP I Top View (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 WCMA1008U1X Maximum Ratings DC Voltage Applied to Outputs in High Z State[1]........................................0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage[1]..................................–0.5V to VCC + 0.5V Storage Temperature .................................–65°C to +150°C Output Current into Outputs (LOW)............................20 mA Ambient Temperature with Power Applied...............................................55°C to +125°C Static Discharge Voltage ..........................................>2001V (per MIL-STD-883, Method 3015) Supply Voltage to Ground Potential..... ..........–0.5V to +4.6V Latch-Up Current ......................................................>200 mA Operating Range Product WCMA1008U1X Range Industrial Ambient Temperature –40°C to +85°C VCC 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) VCC Range Product WCMA1008U1X Speed Min. Typ.[2] Max. 2.7V 3.0V 3.6V 70 ns 55 ns Operating, ICC f = fmax Typ.[2] Max. 20 mA 40 mA Standby (ISB2) Typ.[2] Max. 0.4 µA 30 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2 WCMA1008U1X Electrical Characteristics Over the Operating Range WCMA1008U1X-70/55 Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current IOZ ICC ISB1 ISB2 Typ.[2] Min. Max. Unit 2.4 V 0.4 V 2 VCC + 0.5V V –0.5 0.8 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC mA Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs VCC = 3.6V 70ns IOUT = 0 mA 55ns CMOS Levels Max. VCC, CE1≥VIH, 70ns CE2<VIH 55ns VIN > VIH or VIN < VIL, f = fMAX 20 40 23 50 15 300 17 350 Max. VCC, CE1 ≥ VCC – 0.3V,CE2 <0.3 VIN > VCC – 0.3V or VIN < 0.3V, f = 0 0.4 30 µA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz,VCC = Vcc(typ) 6 pF 8 pF Thermal Resistance Description Thermal Resistance[3] (Junction to Ambient) Test Conditions Symbol BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance[3] (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 WCMA1008U1X AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC Typ R2 30 pF 90% 10% 90% 10% GND Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.3V Unit R1 1213 Ohms R2 1378 Ohms RTH 645 Ohms VTH 1.75 Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions Min. VCC for Data Retention Typ.[2] Max. 1.6 ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[4] Operation Recovery Time VCC = 2V, CE1 ≥ VCC – 0.3V, CE2 < 0.3V VIN > VCC – 0.3V or VIN < 0.3V V 0.4 20 ns tRC ns DATA RETENTION MODE VDR > 1.6V 1.8V tCDR 1.8V tR CE Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 4 µA 0 Data Retention Waveform VCC Unit WCMA1008U1X Switching Characteristics Over the Operating Range[5] WCMA1008U1X-55 Parameter Description Min. Max. WCMA1008U1X-70 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[6] 5 tLZCE 20 [6] 10 [6, 7] tHZCE CE1 HIGH or CE2 LOW to High Z tPU CE1 LOW and CE2 HIGH to Power-Up ns 35 ns ns 25 20 CE1 HIGH or CE2 LOW to Power-Down 70 10 0 ns ns 25 0 55 ns ns 10 20 CE1 LOW and CE2 HIGH to Low Z tPD 10 10 OE HIGH to High Z ns 70 55 [6, 7] tHZOE 70 55 ns ns 70 ns [8,] WRITE CYCLE tWC Write Cycle Time 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 55 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns [6, 7] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[6] 20 5 25 5 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 5 WCMA1008U1X Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Notes: 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 6 WCMA1008U1X Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [8, 12, 14] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 13 tHZOE [8, 12, 14] Write Cycle No. 2 (CE1 or CE2 Controlled) tWC ADDRESS tSCE CE1 tSA CE2 tHA tAW tPWE WE OE tSD DATA I/O tHD DATAIN VALID Notes: 12. Data I/O is high impedance if OE = VIH. 13. During this period, the I/Os are in output state and input signals should not be applied. 14. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 7 WCMA1008U1X Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [14] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD DATAI/O NOTE 13 tHD DATAIN VALID tLZWE tHZWE 8 WCMA1008U1X Truth Table CE1 CE2 WE OE Inputs/Outputs Mode H X X X High Z Deselect/Power-Down Standby (ISB) X L X X High Z Deselect/Power-Down Standby (ISB) L H H L Data Out Read Active (ICC) L H L X Data In Write Active (ICC) L H H H High Z Output Disabled Active (ICC) 9 Power WCMA1008U1X Ordering Information Speed (ns) 70 55 Ordering Code Package Name Package Type Operating Range Industrial WCMA1008U1X-TF70 T32 32-Lead TSOP WCMA1008U1X-SF70 S32 32-Lead STSOP WCMA1008U1X-TF55 T32 32-Lead TSOP WCMA1008U1X-SF55 S32 32-Lead STSOP Package Diagrams 32-Lead Thin Small Outline Package, T32 10 WCMA1008U1X Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package, S32 11 WCMA1008U1X Document Title: WCMA1008U1X, 128K x 8 Static RAM REV. Spec # ECN # Issue Date Orig. of Change ** 38-14023 115246 4/24/2002 MGN 12 Description of Change New Data Sheet