S1008V1C WCFS1008V1C 128K x 8 Static RAM Features • High speed — tAA = 12ns • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options Functional Description The WCFS1008V1C is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS1008V1C is available in standard 400-mil-wide package. Logic Block Diagram Pin Configurations SOJ Top View I/O0 INPUT BUFFER I/O1 I/O2 512 x 256 x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O4 I/O5 CE COLUMN DECODER I/O6 I/O7 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 WE OE POWER DOWN A0 A1 A2 A3 Selection Guide WCFS1008V1C 12ns Maximum Access Time (ns) 12 Maximum Operating Current (mA) 160 Maximum Standby Current (mA) 5 Revised April 19, 2002 WCFS1008V1C Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Commercial Ambient Temperature[2] VCC 0°C to +70°C 3.3V ± 10% DC Input Voltage[1].................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range WCFS1008V1C 12ns Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = – 4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current IOZ Min. Max. Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.3 0.8 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 160 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 20 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 5 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. 2 Max. Unit 6 pF 8 pF WCFS1008V1C AC Test Loads and Waveforms R1 480 Ω R1 480 Ω 3.3V OUTPUT ALL INPUT PULSES 3.3V 3.0V 90% OUTPUT R2 255 Ω 30 pF INCLUDING JIG AND SCOPE (a) R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% ≤ 3 ns ≤ 3 ns THÉVENIN EQUIVALENT 167 Ω 1.73V OUTPUT Equivalent to: Switching Characteristics[4] Over the Operating Range WCFS1008V1C 12ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Data Hold from Address Change ns 12 3 ns ns tACE CE LOW to Data Valid 12 ns tDOE OE LOW to Data Valid 6 ns tLZOE OE LOW to Low Z OE HIGH to High tHZOE 0 Z[5, 6] Z[6] tLZCE CE LOW to Low tHZCE CE HIGH to High Z[5, 6] tPU CE LOW to Power-Up 6 ns 6 ns 3 ns 0 CE HIGH to Power-Down tPD ns ns 12 ns [7, 8] WRITE CYCLE tWC Write Cycle Time 12 ns tSCE CE LOW to Write End 9 ns tAW Address Set-Up to Write End 8 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 8 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z[6] 3 ns tHZWE WE LOW to High Z[5, 6] 6 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 3 WCFS1008V1C Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention tCDR[3] Chip Deselect to Data Retention Time tR Operation Recovery Time Min. No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Max. Unit 2.0 V 0 ns 200 µs Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 4 WCFS1008V1C Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS tSCE CE tSA tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O DATAIN VALID NOTE 14 tHZOE Notes: 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. 5 tHD WCFS1008V1C Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 14 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0–I/O7 Mode Power H X X High Z Power-Down Standby (ISB) X X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code WCFS1008V1C-JC12 Package Name J Package Type 32-Lead 300-Mil Molded SOJ 6 Operating Range Commercial WCFS1008V1C Package Diagram 32-Lead (400-Mil) Molded SOJ J 51-85041-A 7 WCFS1008V1C Document Title: WCFS1008V1C 128K x 8 Static RAM REV. Issue Date Orig. of Change Description of Change ** 4/15/02 XFL New Datasheet 8