WCMA2008U1B WCMA2008U1B 256K x 8 Static RAM Features • High Speed — 70ns availability • Voltage range — 2.7V–3.3V • Ultra low active power — Typical active current: 1 mA @ f = 1MHz — Typical active current: 7 mA @ f = fmax (70ns speed) • Low standby power • Easy memory expansion with CE1,CE2 ,and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The WCMA2008U1B is a high-performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is device is ideal for portable applications. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE 1 HIGH or CE2 LOW). Writing to the device is accomplished by taking Chip Enable (CE 1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE 2) HIGH. Data on the eight I/O pins (I/O0 through I/O7 ) is then written into the location specified on the address pins (A 0 through A17 ). Reading from the device is accomplished by taking Chip Enable (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable 2 (CE2 ) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE 1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE 1 LOW and CE2 HIGH and WE LOW). The WCMA2008U1B is available in a 36-ball FBGA package. Logic Block Diagram I/O0 Data in Drivers I/O2 I/O3 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 WE OE SENSE AMPS 128K x 8 ARRAY A12 A13 A14 A15 A16 A17 CE 2 CE1 I/O1 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 WCMA2008U1B Pin Configurations FBGA (Top View) 1 2 3 4 5 6 A0 A1 CE 2 A3 A6 A8 A I/O4 A2 WE A4 A7 I/O0 B DNU A5 I/O1 C VSS VCC D VCC VSS E I/O2 F I/O5 I/O6 NC A17 I/O7 OE CE1 A16 A 15 I/O3 G A9 A10 A11 A12 A13 A 14 H Maximum Ratings DC Voltage Applied to Outputs in High Z State [1] ........................................0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C DC Input Voltage [1] ..................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................20 mA Ambient Temperature with Power Applied...............................................55°C to +125°C Static Discharge Voltage ..........................................>2001V (per MIL-STD-883, Method 3015) Supply Voltage to Ground Potential..... ..........–0.5V to +4.6V Latch-Up Current ......................................................>200 mA Operating Range Product WCMA2008U1B Range Industrial Ambient Temperature –40°C to +85°C VCC 2.7V to 3.3V Product Portfolio Power Dissipation (Industrial) VCC Range Product Min. WCMA2008U1B 2.7V Typ. [2] 3.0V Speed Max. 3.3V Operating, I CC f = 1 MHz [2] Max. 1.5 mA 3 mA Typ. 70 ns f = fmax [2] Typ. 7 mA Standby (I SB2) Max. Typ. [2] Max. 15 mA 2 µA 10 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.) , T A = 25°C. 2 WCMA2008U1B Electrical Characteristics Over the Operating Range WCMA2008U1B-70 Parameter Description Test Conditions Min. VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V VO L Output LOW Voltage IO L = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VIL Input LOW Voltage I IX Input Leakage Current I OZ Output Leakage Current GND < VO < VCC , Output Disabled I CC VCC Operating Supply Current f =fMAX = 1/t RC I SB1 Automatic CE Power-Down Current — CMOS Inputs CE1 > VCC – 0.2V or CE 2 < 0.2V VIN > VCC – 0.2V or V IN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE) I SB2 Automatic CE Power-Down Current— CMOS Inputs CE1 > VCC – 0.2V or CE 2 < 0.2V VIN > VCC − 0.2V or VIN < 0.2V, f = 0, V CC =3.3V GND < VI < VCC f = 1 MHz Typ. [2] Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.3V V –0.3 0.8 V –1 +1 µA –1 +1 µA 7 15 mA 1.5 3 2 10 VCC = 3.3V IOUT = 0 mA CMOS Levels µA Capacitance[3] Parameter Description CIN COUT Input Capacitance Output Capacitance Test Conditions Max. Unit T A = 25°C, f = 1 MHz,VCC = Vcc(typ) 6 8 pF pF Thermal Resistance Description [3] Thermal Resistance (Junction to Ambient) Test Conditions Symbol BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance[3] (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 WCMA2008U1B AC Test Loads and Waveforms R1 V CC ALL INPUT PULSES OUTPUT V CC Typ R2 30 pF GND Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% THÉVENIN EQUIVALENT R TH OUTPUT V TH Parameters R1 3.3V 1105 Unit Ohms R2 1550 Ohms RTH VTH 645 1.75 Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions Min. VCC for Data Retention Typ.[2] 1.5 I CCDR Data Retention Current t CDR[3] Chip Deselect to Data Retention Time t R[4] Operation Recovery Time VCC = 1.5V CE1 > VCC – 0.2V or CE2 < 0.2V VIN > V CC − 0.2V or VIN < 0.2V 1 V 6 µA t RC ns VDR > 1.5 V tCDR V CC(min) tR CE 1 or CE2 Note: 4. Full Device AC operation requires linear VCC ramp from V DR to VCC(min.) > 100 µs or stable at V CC(min.) > 100 µs. 4 Vccmax ns DATA RETENTION MODE V CC(min) Unit 0 Data Retention Waveform VCC Max. WCMA2008U1B Switching Characteristics Over the Operating Range [5] WCMA2008U1B-70 Parameter Description Min. Max. Unit READ CYCLE t RC Read Cycle Time t AA Address to Data Valid 70 t OHA Data Hold from Address Change t ACE CE 1 LOW and CE2 HIGH to Data Valid t DOE OE LOW to Data Valid t LZOE OE LOW to Low Z[6] 10 OE HIGH to High Z t LZCE CE 1 LOW and CE2 HIGH to Low Z ns 35 ns ns 10 [6, 7] t HZCE CE 1 HIGH or CE2 LOW to High Z t PU CE 1 LOW and CE2 HIGH to Power-Up t PD 70 25 [6] ns ns 25 0 CE 1 HIGH or CE2 LOW to Power-Down ns ns 5 [6, 7] t HZOE ns 70 ns ns 70 ns [8,] WRITE CYCLE t WC Write Cycle Time 70 ns t SCE CE 1 LOW and CE2 HIGH to Write End 60 ns t AW Address Set-Up to Write End 60 ns t HA Address Hold from Write End 0 ns t SA Address Set-Up to Write Start 0 ns t PWE WE Pulse Width 50 ns t SD Data Set-Up to Write End 30 ns t HD Data Hold from Write End 0 ns [6, 7] t HZWE WE LOW to High Z t LZWE WE HIGH to Low Z [6] 25 10 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to VCC(typ.) , and output loading of the specified IOL /I O H and 30 pF load capacitance. 6. At any given temperature and voltage condition, tH Z C E is less than t LZCE , t HZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. t HZOE, t HZCE, and t HZWE transitions are measured when the outputs enter a high impedance state. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = V IL , and CE2 = VIH . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 5 WCMA2008U1B Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [9, 10] tRC ADDRESS tAA tO H A DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE 1 CE 2 tACE OE tHZOE tDOE tH Z C E tLZOE DATA OUT HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IC C 50% 50% ISB Notes: 9. Device is continuously selected. OE , CE 1 = V IL, CE2 = VIH . 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 6 WCMA2008U1B Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [8, 12, 14] tWC ADDRESS tS C E CE1 CE2 tAW tHA tSA tPWE WE OE tSD DATA I/O tH D DATA I N VALID NOTE 13 tHZOE [8, 12, 14] Write Cycle No. 2 (CE1 or CE2 Controlled) tWC ADDRESS tS C E CE 1 tSA CE 2 tAW tH A tPWE WE OE tSD DATA I/O tHD DATAIN VALID Notes: 12. Data I/O is high impedance if OE = VIH . 13. During this period, the I/Os are in output state and input signals should not be applied. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 7 WCMA2008U1B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [14] tWC ADDRESS tS C E CE 1 CE 2 tAW tSA tH A tP W E WE tSD DATAI/O NOTE 13 tHD DATAIN VALID tLZWE tH Z W E 8 WCMA2008U1B Truth Table CE1 CE2 WE OE Inputs/Outputs Mode H X X X High Z Deselect/Power-Down Standby (ISB) X L X X High Z Deselect/Power-Down Standby (ISB) L H H L Data Out Read Active (ICC ) L H L X Data In Write Active (ICC ) L H H H High Z Output Disabled Active (ICC ) 9 Power WCMA2008U1B Ordering Information Speed (ns) 70 Ordering Code WCMA2008U1B-FF70 Package Name Package Type Operating Range FB36A 36-ball Fine Pitch BGA (6.0 mm x 8.0 mm x 1.0 mm) Industrial Package Diagrams 36-Lead VFBGA (6.0 mm x 8.0 mm x 1.0 mm) FB36A 51-85149-** 10 WCMA2008U1B Document Title: WCMA2008U1B, 256K x 8 Static RAM REV. Spec # ECN # Issue Date Orig. of Change ** 38-05321 117495 3/18/2002 CBD 11 Description of Change New Data Sheet