SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE (TOP VIEW) Functionally Similar to AMD’s AM29854 High-Speed Bus Transceiver With Parity Generator/Checker Parity-Error Flag With Open-Collector Outputs Latch for Storing the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE The SN74ALS29854 is an 8-bit to 9-bit parity 11 14 transceiver designed for two-way communication 12 13 between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector ERR flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. The SN74ALS29854 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT AND I/O OEB OEA CLR LE Ai ∑ of Hs Bi† ∑ of Ls L H X X Odd Even NA NA A H L NA A data to B bus and generate parity H L X L NA Odd Even B NA NA H L B data to A bus and check parity H L H H NA X X NA NA N-1 Store error flag X X L H X X X NA NA H Clear error-flag register H H H L X X H H L L X X L Odd H Even X Z Z Z NC H L H Isolation§ L L X X Odd Even NA NA A L H NA A data to B bus and generate inverted parity A B PARITY ERR‡ OPERATION NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR, when enabled, shows inverted parity of the A bus. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 logic diagram (positive logic) A1 – A8 2–9 8x 8 8 16 – 23 B1 – B8 EN 8x 8 EN 14 OEB OEA 1 15 8 PARITY 8 1 MUX 1 9 1 2K P 1 G1 LE CLR 2 13 10 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ERR SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 error-flag waveforms OEB H L OEA H L Even Bi + PARITY Odd LE H L CLR H L ERR H L Pass Sample Store Clear ERROR-FLAG FUNCTIONS INTERNAL TO DEVICE OUTPUT PRESTATE OUTPUT CLR POINT P ERRn–1† ERR L L L H X L H Pass L H L X H X L H L L H Sample H L X X H Clear H H X L H L H Store INPUTS LE FUNCTION † ERRn–1 represents the state of ERR before any changes at CLR, LE, or point P. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 recommended operating conditions MIN NOM MAX UNIT 4.75 5 5.25 V VCC VIH Supply voltage VIL VOH Low-level input voltage 5.5 V IOH IOL High-level output current – 24 mA Low-level output current 48 mA tw Pulse duration High-level input voltage 2 V 0.8 High-level output voltage, ERR LE high 10 LE low 10 CLR low 10 Bi and PARITY 10 CLR high 15 tsu Set p time before LE↓ Setup th TA Hold time, Bi and PARITY after LE↓ 3 Operating free-air temperature 0 V ns ns ns 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.75 V, VOH e cept ERR All I/Os except 75 V VCC = 4 4.75 IOH VOL ERR VCC = 4.75 V, VCC = 4.75 V, II IIH‡ IIL‡ VCC = 5.25 V, VCC = 5.25 V, Data Control 25 V VCC = 5 5.25 V, II = – 18 mA IOH = – 15 mA IOH = – 24 mA VOH = 5.5 V IOL = 48 mA VI = 5.5 V VI = 2.7 V 4V VI = 0 0.4 MIN TYP† MAX UNIT – 1.2 V 2.4 V 2 0.1 0.35 mA 0.5 V 0.1 mA 20 µA – 0.2 – 0.75 mA IO§ VCC = 5.25 V, VO = 0 – 75 – 250 mA ICC VCC = 5.25 V, All outputs open 70 100 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 switching characteristics (see Figure 1) VCC = 4.75 V to 5.25 V, TA = MIN to MAX† FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL A or B B or A CL = 50 pF tPLH tPHL A or B B or A CL = 300 pF tPLH tPHL A PARITY CL = 50 pF tPLH tPHL A PARITY CL = 300 pF tPZH tPZL OEA or OEB A or B CL = 50 pF tPZH tPZL OEA or OEB A or B CL = 300 pF tPHZ tPLZ OEA or OEB A or B CL = 5 pF tPHZ tPLZ OEA or OEB A or B CL = 50 pF 8 tPHL LE ERR CL = 50 pF 12 ns tPLH tPLH CLR ERR CL = 50 pF 12 ns PARAMETER tPHL tPLH tPHL tPLH MIN 8 8 13 13 15 18 22 22 17 17 23 23 8 8 15 17 OEA PARITY CL = 50 pF OEA PARITY CL = 300 pF 19 22 Bi/PARITY ERR CL = 50 pF tPHL † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 25 20 20 ns ns ns ns ns ns ns ns ns ns ns 5 SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION Test Point VCC S1 From Output Under Test RL = 180 Ω R1 1 kΩ CL (see Note A) VCC SWITCH POSITION TABLE All Diodes 1N916 or 1N3064 S2 TEST S1 S2 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed 180 Ω From Output Under Test 1.5 V Timing Input LOAD CIRCUIT 2 ERROR-FLAG OUTPUT High-Level Pulse 3V 1.5 V 1.5 V 0 0 tw th tsu 510 Ω CL (see Note A) LOAD CIRCUIT 1 ALL OUTPUTS EXCEPT FOR ERROR FLAG 3V Test Point 3V 3V Data Input 1.5 V 1.5 V 0 Low-Level Pulse 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 0 tPZL tPLZ ≈ 4.5 V 3V Input 1.5 V 1.5 V 0 1.5 V tPHL tPLH 1.5 V 1.5 V VOL tPHZ VOH 1.5 V VOH Waveform 2 (see Note B) 1.5 V 1.5 V 0.5 V ≈ 1.5 V ≈0 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 0.5 V tPZH tPLH tPHL ≈ 1.5 V VOL VOH In-Phase Output Out-of-Phase Output Waveform 1 (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74ALS29854NT3 OBSOLETE PDIP NT Pins Package Eco Plan (2) Qty 24 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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