APA2069 Stereo 2.6W Audio Power Amplifier (with DC_Volume Control) Features General Description • • Low Operating Current with 9mA APA2069 is a monolithic integrated circuit, which Improved Depop Circuitry to Eliminate Turn-on provides precise DC volume control, and a stereo and Turn-off Transients in Outputs bridged audio power amplifiers capable of producing High PSRR 2.6W (1.8W) into 4Ω with less than 10% (1.0%)THD+N. • • The attenuator range of the volume control in APA2069 32 Steps Volume Adjustable by DC Voltage is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with Hysteresis • with 32 steps. The advantage of internal gain setting 2.6W per Channel Output Power into 4Ω Load can be less components and PCB area. Both of the at 5V,BTL Mode • depop circuitry and the thermal shutdown protection Two Output Modes Allowable with BTL and SE circuitry are integrated in APA2069, that reduce pops Modes Selected by SE/BTL pin • and clicks noise during power up or shutdown mode Low Current Consumption in Shutdown Mode operation. It also improves the power off pop noise (1µA) • • • • and protects the chip from being destroyed by over Short Circuit Protection temperature and short current failure. To simplify the Thermal shutdown protection and over current audio system design, APA2069 combines a stereo protection circuitry bridge-tied loads (BTL) mode for speaker drive and a Power DIP-16 Package stereo single-end (SE) mode for headphone drive into Lead Free Available (RoHS Compliant) a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Applications • NoteBook PC • LCD Monitor or TV ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 1 www.anpec.com.tw APA2069 Ordering and Marking Information Package Code J : PDIP-16 Operating Ambient Temp. Range I : - 40 to 85 °C Handling Code TU : Tube Lead Free Code L : Lead Free Device Blank : Original Device APA2069 Lead Free Code Handling Code Temp. Range Package Code APA2069 XXXXX APA2069 J : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Block Diagram LOUT+ LINVolume Control LOUT- RINBYPASS BYPASS ROUT+ VOLUME ROUTSE/BTL SHUTDOWN VDD SE/BTL Power and Depop circuit Shutdown ckt GND APA2069_Block Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 2 www.anpec.com.tw APA2069 Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) Symbol VDD VIN TA TJ TSTG TS VESD PD Parameter Supply Voltage Range Input Voltage Range, SE/BTL, SHUTDOWN Operating Ambient Temperature Range Maximum Junction Temperature Rating Unit -0.3 to 6 V -0.3 to VDD+0.3 V °C -40 to 85 Intermal Limited* Storage Temperature Range Soldering Temperature,10 seconds Electrostatic Discharge Power Dissipation °C 1 -65 to +150 °C 260 2 -3000 to 3000* 3 -200 to 200* Intermal Limited °C V Notes: 1.APA2069 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C 2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses 3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses Recommended Operating Conditions Supply Voltage, VDD High level threshold voltage, VIH Low level threshold voltage, VIL Min. Max. Unit 4.5 5.5 V SHUTDOWN 2 SE/BTL 4 V 1.0 SHUTDOWN V 3 SE/BTL Common mode input voltage, VICM VDD-1.0 V Thermal Characteristics Symbol Parameter RTHJA Thermal Resistance from Junction to Ambient in Free Air DIP-16 Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 3 Value Unit 45 °C/W www.anpec.com.tw APA2069 Electrical Characteristics VDD=5V, -20°C<TA<85°C (unless otherwise noted) Symbol VDD Parameter Supply Voltage IDD Supply Current ISD Test Condition Supply Current in Shutdown Mode Min. APA2069 Unit Typ. Max. 4.5 5.5 SE/BTL=0V 9 20 SE/BTL=5V 4 10 V mA SE/BTL=0V SHUTDOWN=0V 1 µA IIH High input Current 900 nA IIL Low Input Current 900 nA 5 mV VOS Output Differential Voltage Operating Characteristics, BTL mode. VDD=5V,TA=25°C,RL=4Ω, Gain=2V/V (unless otherwise noted) Symbol Parameter Test Condition Min. THD=10%, RL=3Ω, Fin=1kHz 2.9 THD=10%, R =4Ω, Fin=1kHz 2.6 THD=10%, RL=8Ω, Fin=1kHz 1.6 THD=1%, RL=3Ω, Fin=1kHz 2.4 THD=1%, RL=4Ω, Fin=1kHz 1.8 L PO Maximum Output Power THD=0.5%, RL=8Ω, Fin=1kHz THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio APA2069 Unit Typ. Max. 1 W 1.3 PO=1.2W, RL=4Ω, Fin=1kHz 0.07 PO=0.9W, RL=8Ω, Fin=1kHz 0.08 % VIN=0.1Vrms, RL=8Ω, CB=1µF, Fin=120Hz 60 dB Xtalk Channel Separation CB=1µF, RL=8Ω, Fin=1kHz 90 dB S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_wieght 95 dB Operating Characteristics, SE mode. VDD=5V,TA=25°C, Gain=1V/V (unless otherwise noted) Symbol PO Parameter Maximum Output Power Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 Test Condition APA2069 Unit Min. Typ. Max. THD=10%, RL=16Ω, Fin=1kHz 220 THD=10%, RL=32Ω, Fin=1kHz 120 THD=1%, RL=16Ω, Fin=1kHz 160 THD=1%, RL=32Ω, Fin=1kHz 95 4 mW www.anpec.com.tw APA2069 Electrical Characteristics (Cont.) Operating Characteristics, SE mode. VDD=5V,TA=25°C, Gain=1V/V (unless otherwise noted) Symbol Parameter APA2069 Unit Min. Typ. Max. Test Condition THD+N Total Harmonic Distortion Plus Noise PSRR Power Ripple Rejection Ratio PO=125mW, RL=16Ω, Fin=1kHz 0.09 PO=65mW, RL=32Ω, Fin=1kHz 0.09 % VIN=0.1Vrms, RL=8Ω, CB=1µF, Fin=120Hz 60 dB Xtalk Channel Separation CB=1µF, RL=32Ω, Fin=1kHz 60 dB S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_wieght 100 dB Pin Description SHUTDOWN BYPASS RINGND 1 2 3 4 APA2069 GND 5 LIN- 6 VOLUME 7 SE/BTL 8 16 15 14 13 ROUTVDD ROUT+ GND 12 11 10 9 GND LOUT+ VDD LOUT- Pin Function Description Pin Config Function Description I It will be into shutdown mode when pull low. ISD = 1µA Bias voltage generator Right channel input terminal Ground connection, Connected to thermal pad. Left channel input terminal Input signal for internal volume gain setting. Output mode control input, high for SE output mode and low for BTL mode. Left channel positive output in BTL mode and SE mode. Supply voltage Left channel negative output in BTL mode and high impedance in SE mode. Right channel negative output in BTL mode and high impedance in SE mode. Right channel positive output in BTL mode and SE mode. No. 1 Name SHUTDOWN 2 3 4,5,12,13 6 7 BYPASS RINGND LINVOLUME SE/BTL I I I I 9 10,15 LOUTVDD O - 11 LOUT+ O 14 ROUT+ O 16 ROUT- O 8 Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 I 5 www.anpec.com.tw APA2069 Typical Application Circuit VDD 0.1 µF V DD 100 µF GND LOUT+ L-CH Input 220 µ F 1 µF LIN- 4Ω Volume Control 1 µF R-Ch Input RIN- ROUT+ 100k Ω Shutdow n Signal 2.2 µF 220 µF VOLUME 50kΩ Sleeve Tip Headphone Jack BYPASS VDD Control Pin Ring SE/BTL Signal LOUT- BYPASS V DD 1kΩ 1k Ω 4Ω 100k Ω SE/BTL SHUTDOWN ROUT- SE/BTL Shutdown ckt A2069_AppCkt Volume Control Table_BTL Mode Supply Voltage Vdd=5V Gain(dB) 20 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 High(V) 0.12 0.23 0.34 0.46 0.57 0.69 0.80 0.91 1.03 1.14 1.25 1.37 1.48 1.59 1.71 Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 Low(V) 0.00 0.17 0.28 0.39 0.51 0.62 0.73 0.84 0.96 1.07 1.18 1.29 1.41 1.52 1.63 Hysteresis(mV) 52 51 50 49 47 46 45 44 43 41 40 39 38 37 6 Recommended Voltage(V) 0 0.20 0.31 0.43 0.54 0.65 0.77 0.88 0.99 1.10 1.22 1.33 1.44 1.56 1.67 www.anpec.com.tw APA2069 Volume Control Table_BTL Mode (Cont.) Supply Voltage Vdd=5V Gain(dB) -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -80 High(V) 1.82 1.93 2.05 2.16 2.28 2.39 2.50 2.62 2.73 2.84 2.96 3.07 3.18 3.30 3.41 3.52 5.00 Low(V) 1.74 1.85 1.97 2.08 2.19 2.30 2.42 2.53 2.64 2.75 2.87 2.98 3.09 3.20 3.32 3.43 3.54 Hysteresis(mV) 35 34 33 32 30 29 28 27 26 24 23 22 21 20 18 17 16 Recommended Voltage(V) 1.78 1.89 2.01 2.12 2.23 2.35 2.46 2.57 2.69 2.80 2.91 3.02 3.14 3.25 3.36 3.48 5 Typical Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD = 5V Av =14dB f = 1KHz SE RL = 4Ω RL = 3Ω 1 RL = 32Ω 1 THD+N (%) THD+N (%) V DD = 5V Av =20dB f = 1KHz RL = 8Ω BTL 0.1 RL = 16Ω 0.1 0.01 0.01 0 0.5 1 1.5 2 2.5 3 0 3.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 40m 80m 120m 160m 200m 240m Output Power (W) 7 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD = 5V Av =20dB RL =3Ω BTL VDD = 5V F =1KHz RL =3Ω BTL THD+N (%) THD+N (%) 1 Av = 20dB 0.1 1 f = 20KHz f = 20Hz f = 1KHz Av = 6dB 0.1 0.05 10m 0.01 0 1 0.5 1.5 2 2.5 3 3.5 100m Output Power (W) THD+N vs. Frequency 5 THD+N vs. Frequency 10 10 V DD = 5V Av = 6dB RL =3Ω BTL V DD = 5V RL =3Ω Po = 1.8W BTL 1 1 THD+N (%) THD+N (%) 1 Output Power (W) Av = 20dB 0.1 0.1 Po = 0.9W Av = 6dB Po = 1.8W 0.01 20 100 1k 10k 0.01 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 8 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD = 5V F =1KHz RL =4Ω BTL V DD = 5V Av =20dB RL =4Ω BTL F = 20KHz 1 THD+N (%) THD+N (%) 1 Av = 20dB 0.1 F = 20Hz 0.1 F = 1KHz Av = 6dB 0.01 0.01 0 0.5 1 1.5 2 2.5 3 10m 3.5 100m Output Power (W) 5 Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 10 V DD = 5V Av= 6dB RL=4Ω BTL V DD = 5V RL=4Ω Po=1.5W BTL 1 1 THD+N (%) THD+N (%) 1 Av = 6dB 0.1 Po = 0.8W 0.1 Po = 1.5W Av = 20dB 0.01 20 100 1k 10k 0.01 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 9 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD = 5V Av = 20dB RL=8Ω BTL 1 1 THD+N (%) THD+N (%) VDD = 5V F= 1KHz RL=8Ω BTL Av = 6dB F = 20KHz F = 20Hz 0.1 0.1 F = 1KHz Av = 20dB 0.01 0 0.5 1 1.5 2 2.5 3 0.01 10m 3.5 100m Output Power (W) THD+N vs. Frequency 10 VDD=5V RL=8Ω Po=0.9W BTL V DD = 5V Av = 6dB RL=8Ω BTL 1 Po = 0.5W 1 Av = 6dB 0.1 0.1 Av = 20dB Po = 0.9W 0.01 20 5 THD+N vs. Frequency THD+N (%) THD+N (%) 10 1 Output Power (W) 0.01 100 1k 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 20 100 1k 10k 20k Frequency (Hz) 10 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD=5V Av=14dB RL=16Ω Co=1000µ f SE 1 1 THD+N (%) THD+N (%) V DD=5V F=1KHz RL=16Ω SE Av = 0dB 0.1 F = 20Hz F = 20KHz 0.1 Av = 14dB F = 1KHz 0.01 0.01 0 40m 80m 120m 160m 200m 10m 240m 50m Output Power (W) THD+N vs. Frequency 200m 300m THD+N vs. Frequency 10 10 V DD=5V RL=16 Ω Po=125mW Co=1000µ f SE V DD=5V Av=0dB RL=16 Ω Co=1000µ f SE 1 1 THD+N (%) THD+N (%) 100m Output Power (W) Av = 0dB 0.1 Po = 125mW 0.1 Po = 60mW Av = 14dB 0.01 20 100 1k 10k 0.01 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 11 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 V DD=5V Av=14dB RL =32 Ω Co=1000 µ f SE 1 1 THD+N (%) THD+N (%) V DD=5V F=1KHz R L=32 Ω SE Av = 0dB 0.1 F = 20KHz 0.1 Av = 14dB F = 1KHz 0.01 10m 0.01 0 40m F = 20Hz 80m 120m 160m 200m 240m 50m Output Power (W) 200m 300m Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 10 V DD=5V R L =32Ω Po=65mW Co=1000 µ f SE 1 THD+N (%) THD+N (%) 100m Av = 0dB 0.1 V DD=5V Av=14dB RL=32 Ω Co=1000µ f SE 1 Po = 30mW 0.1 Av = 14dB Po = 65mW 0.01 20 100 1k 10k 0.01 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 12 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) Frequency Response Frequency Response +20 +20 +330 +330 Amplitude( 20dB) Amplitude( 20dB) +320 +320 +16 +16 +190 +8 Phase( 6dB) +4 Amplitude( 6dB) V DD=5V RL=4Ω Po=0.8W BTL +0 10 +180 Amplitude(dB) +300 +12 10k +190 Phase( 6dB) +180 +4 +170 1k +300 +8 +160 100 V DD=5V RL=8Ω Po=0.5W BTL +0 10 100k 200k Amplitude( 6dB) +170 100 Frequency (Hz) +280 +10 +200 Amplitude(dB) Amplitude(dB) +220 Amplitude(0dB) VDD=5V RL=16Ω Co=1000µf Po=60mW SE 100 Phase(0dB) Phase(14dB) +6 +2 +160 -6 10k +120 100k 200k -10 20 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 +190 Amplitude(0dB) +140 1k +200 -2 +180 -2 +210 Phase(Degress) +240 Phase(Degress) Phase(14dB) +2 -10 20 +220 Amplitude(14dB) +260 -6 +160 100k 200k +14 +10 +6 10k Frequency Response +300 Amplitude(14dB) 1k Frequency (Hz) Frequency Response +14 +310 Phase(Degress) Phase( 20dB) +12 Phase( 20dB) Phase(Degress) Amplitude(dB) +310 Phase(0dB) VDD=5V RL=32Ω Co=1000µf Po=30mW SE 100 +180 +170 1k +165 100k 200k 10k Frequency (Hz) 13 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) Crosstalk vs. Frequency Crosstalk vs. Frequency +0 +0 V DD=5V RL=4Ω Po=1.5 W BTL -10 -20 -30 -30 -40 -40 Crosstalk(dB) Crosstalk(dB) VDD=5V -10 RL=8Ω -20 Po=0.9 W BTL -50 -60 -70 -80 -50 -60 -70 Right to Left -80 Right to Left -90 -90 -100 -100 Left to Right -110 -120 20 100 1k Left to Right -110 10k -120 20k 20 100 Frequency (Hz) -10 -20 Crosstalk vs. Frequency +0 V DD=5V RL=16 Ω Co=1000µ f Po=125mW SE -10 -20 Crosstalk(dB) Crosstalk(dB) V DD=5V RL=32Ω Co=1000 µ f Po=65mW SE -30 -30 -40 -50 Right to Left -60 Left to Right -70 -40 -50 Right to Left -60 Left to Right -70 -80 -80 -90 -90 -100 20 10k 20k Frequency (Hz) Crosstalk vs. Frequency +0 1k -100 100 1k 10k 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 14 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 100u Filter BW<22KHz Output Noise Voltage(V) Output Noise Voltage(V) 100u 20u A-Weight 10u V DD=5V Av=6dB RL=4Ω BTL 20 1k 100 10k 10u A-Weight 1u 20 1u 20k Filter BW<22KHz 20u V DD=5V Av=0dB RL=32 Ω SE 100 Frequency (Hz) 10k 20k Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency +0 +0 V DD=5V RL=4Ω Vin=200mV Av=20dB BTL -10 -20 -10 -20 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 V DD=5V RL=32Ω Vin=200mV Av=14dB SE -30 PSRR(dB) -30 PSRR(dB) 1k 100 1k 10k -100 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 100 1k 10k 20k Frequency (Hz) 15 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) Shutdown Attenuation vs. Frequency Gain vs. DC volume Voltage 20 +0 -20 -30 10 0 -10 Dow n -40 Gain (dB) Shutdown Attenuation(dB) -10 V DD=5V RL =8Ω Vin=1V RMS Av=6dB BTL -50 -60 -70 -80 -20 Up -30 -40 -50 -90 -60 -100 -70 -110 -120 20 100 10k 1k V DD=5V No Load BTL -80 0.0 20k 0.5 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DC volume (V) Frequency (Hz) Power Dissipation vs. Output Power Supply Current vs. Supply Voltage 10.0 1.5 2.0 No Load RL =3Ω 1.8 9.0 BTL Power Dissipation(W) Supply Current(mA) 1.6 8.0 7.0 6.0 5.0 SE 4.0 3.0 2.0 3.0 RL =4Ω 1.4 1.2 1.0 RL=8Ω 0.8 0.6 V DD =5V THD<1% BTL 0.4 0.2 3.5 4.0 4.5 5.0 0.0 0.00 5.5 Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 0.50 1.00 1.50 2.00 2.50 Output Power(W) 16 www.anpec.com.tw APA2069 Typical Characteristics (Cont.) Power Dissipation vs. Output Power 200 RL=8Ω 180 Power Dissipation(W) 160 140 RL=16Ω 120 100 80 RL=32Ω 60 40 V DD=5V THD<1% SE 20 0 0 50 100 150 200 250 Output Power(W) Application Descriptions BTL Operation The power amplifier’s OP1 gain is setting by internal unity-gain and input audio signal is come from internal volume control amplifier, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). The APA2069 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations. OUT+ Volume Control amplifier output signal OP1 By driving the load differentially through outputs OUT+ RL and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation OUTVbias Circuit is different from the classical single-ended SE amplifier configuration where one side of its load is connected OP2 to ground. Figure 1: APA2069 internal configuration (each channel) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 A BTL amplifier design has a few distinct advantages 17 www.anpec.com.tw APA2069 Application Descriptions (Cont.) BTL Operation (Cont.) over the SE configuration, as it provides differentialdrive to the load, thus doubling the output swing for aspecified supply voltage. controls the operation of the follower amplifier that drives LOUT- and ROUT-. • When SE/BTL is held low, the OP2 is turn on and the APA2069 is in the BTL mode. Four times the output power is possible as compared toa SE amplifier under the same conditions. A BTL • When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2069 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode. configuration, such as the one used in APA2069, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit. Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor).The rules described still hold with the addition of the following relationship: 1 << 1 1 ≤ (1) Cbypass x 125kΩ RiCi RLCC 1kΩ VDD 100kΩ Tip Sleeve Headphone Jack Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows : When the phonejack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connnected from the signal pin, the voltage divider set up by resistors 100kΩ and 1kΩ.Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. The ability of the APA2069 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA2069, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input Rev. A.1 - Aug., 2005 Ring SE/BTL Output SE/BTL Operation Copyright ANPEC Electronics Corp. Control Pin 18 www.anpec.com.tw APA2069 Application Descriptions (Cont.) Volume Control Function Input Resistance, Ri APA2069 has an internal stereo volume control whose setting is a function of the DC voltage applied to the VOLUME input pin. The APA2069 volume control consists of 32 steps that are individually selected by a variable DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 20dB to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to half of the step width, as shown in volume control graph. The gain for each audio input of the APA2069 is set by the internal resistors (Ri and Rf) of volume control amplifier in inverting configuration. RF (2) SE Gain = AV = Ri RF (3) BTL Gain = -2 x Ri BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. For the varying gain setting, APA2069 generates each input resistance on figure 4. The input resistance will affect the low frequency performance of audio signal. The minmum input resistance is 10kΩ when gain setting is 20dB and the resistance will ramp up when close loop gain below 20dB. The input resistance has wide variation (+/-10%) caused by process variation. APA2069 DC Volume Control Curve (BTL) 20 10 Ri vs Gain(BTL) Ri(kΩ) 120 0 Forw ard -10 Gain(dB) 100 -20 Backw ard 80 -30 -40 60 -50 40 -60 -70 -80 0.0 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 DC volume (V) -40 -30 -20 Figure 3: Gain setting vs VOLUME pin voltage -10 0 10 20 Gain(dB) Figure 4: Input resistance vs Gain setting For highest accuracy, the voltage shown in the ‘recommended voltage’column of the table is used to Input Capacitor, Ci select a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this The gain levels are 2dB/step from 20dB to -40dB in BTL mode, and the last step at -80dB as mute mode. Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 19 www.anpec.com.tw APA2069 Application Descriptions (Cont.) does not eliminate the need for bypassing the supply nodes of the APA2069. The selection of bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (6) should be maintained. 1 1 << (6) Cbypass x 125kΩ 100kΩ x Ci Input Capacitor, Ci (Cont.) case, Ci and the minimum input impedance Ri (10kΩ) form a high-pass filter with the corner frequency determined in the follow equation: 1 FC(highpass)= (4) 2πx10kΩxCi The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10kΩ and the specification calls for a flat bass response down to 100Hz. Equation is reconfigured as follow : 1 Ci= (5) 2πx10kΩxf C The bypass capacitor is fed thru from a 125kΩ resistor inside the amplifier and the 100kΩ is maximum input resistance of (Ri+ Rf). Bypass capacitor, Cb, values of 3.3µF to 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. Consider to input resistance variation, the Ci is 0.16µF so one would likely choose a value in the range A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstart up = 5 x (Cbypass x 125KΩ) Output Coupling Capacitor, Cc In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. Effective Bypass Capacitor, Cbypass FC(highpass)= As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. Rev. A.1 - Aug., 2005 1 2πRLCC (8) For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. The capacitors located on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typical applications employ a 5V regulator with 1.0µF and a 0.1µF bypass capacitor as supply filtering. This Copyright ANPEC Electronics Corp. (7) 20 www.anpec.com.tw APA2069 Application Descriptions (Cont.) Power Supply Decoupling, Cs size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. The APA2069 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33µF to 1µF, Cb being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resistor should produce a virtually clickless and popless turn-on. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Optimizing Depop Circuitry Shutdown Function Circuitry has been included in the APA2069 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. In order to reduce power consumption while not in use, the APA2069 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to provide maximum device performance. The value of Ci will also affect turn-on pops (Refer to Effective Bypass Capacitance). The bypass voltage ramp up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, I DD<1µA. APA2069 is in shutdown mode. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to av oid unwanted state changes. Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power 21 www.anpec.com.tw APA2069 Application Descriptions (Cont.) BTL Amplifier Efficiency (Cont.) Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. PO (9) Efficiency = PSUP Where : PO = V ORMS × V ORMS RL VORMS = = VP × VP 2RL VP √2 PSUP = VDD x IDDAVG = VDD Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) (10) x 2VP πRL (11) Efficiency of a BTL configuration : PO VPxVP ) / (VDD x 2VP ) = πV P =( 4VDD PSUP πRL 2RL (12) 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL Systems Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation13 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. VDD 2 (13) SE mode : PD,MAX= 2 2π RL Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 3W. In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 4VDD 2 (14) 2π2RL Since the APA2069 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2069 does not require extra heatsink. The power dissipation from equation14, assuming a 5V-power supply and an 8Ω load, must not BTL mode : PD,MAX= A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Rev. A.1 - Aug., 2005 31.25 **High peak voltages cause the THD to increase. Table 1 calculates efficiencies for four different output power levels. Copyright ANPEC Electronics Corp. 0.25 22 www.anpec.com.tw APA2069 Application Descriptions (Cont.) BTL Amplifier Efficiency (Cont.) protection that turns the device off when the junction be greater than the power dissipation that results from the equation15 : TJ,MAX - TA (15) PD,MAX= θJA temperature surpasses 150°C to prevent damaging the IC. For PDIP16 package with thermal pad, the thermal resistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX) of APA2069 is 150οC and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation15. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Considerations Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJMAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2069 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. TAMax = TJMax -θJAPD (16) 150 - 45(0.8*2) = 78°C The APA2069 is designed with a thermal shutdown Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 23 www.anpec.com.tw APA2069 Packaging Information PDIP-16 pin ( Reference JEDEC Registration MS-001) D E c E1 α eB s Q1 A2 A A1 A3 e b2 Dim A A1 A2 A3 b b2 b3 c D E E1 e eB Q1 s α Millimeters Min. 0.38 3.17 2.92 0.36 1.14 0.76 0.20 18.632 Inches Max. 5.32 3.42 3.80 0.56 1.78 1.14 0.36 19.646 Min. 0.015 0.125 0.115 0.014 0.045 0.030 0.008 0.735 6.477 0.245 9.506 1.651 0.84 8° 0.335 0.055 0.023 3° 7.605BSC 6.223 Max. 0.210 0.135 0.150 0.022 0.070 0.045 0.014 0.775 0.300BSC 2.54BSC 8.492 1.397 0.58 3° Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 b3 b 0.255 0.100BSC 24 0.375 0.065 0.033 8° www.anpec.com.tw APA2069 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Time Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 25 www.anpec.com.tw APA2069 Classification Reflow Profiles (Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 ≥350 <2.5 mm 240 +0/-5°C 225 +0/-5°C ≥2.5 mm 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 Volume mm 3 <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2005 26 www.anpec.com.tw