APA2173

APA2173
Stereo, Differential Input Cap-Free Line Driver
Features
•
•
•
General Description
The APA2173 is a stereo, differential input, single supply,
and cap-free line driver, which is available in MSOP-10P
Operating Voltage: 2.3V~5.5V
Differential Input
package.
The APA2173 is ground-reference output, and doesn’t
Ground Reference Output
- No Output Capacitor Required (for DC Blocking)
- Save the PCB Space
need the output capacitors for DC blocking. The advantages of eliminating the output capacitor are saving the
- Reduce the BOM Costs
•
cost, eliminating component height, and improving the
low frequency response.
- Improve the Low Frequency Response
Low Noise and THD+N
The external gain setting is recommended using from
±1V/V to ±10V/V. High PSRR provides increased immu-
- SNR > 108dB
- Noise < 8µVrms
•
•
•
•
•
•
•
nity to noise and RF rectification. APA2173 has shutdown
and under-voltage detector function for Depop solution.
- THD+N < 0.02% at 20Hz~20kHz
Output Voltage Swing Can Reach 2.1Vrms/Ch into
2.5kΩ at VDD=3.3V
The APA2173 is capable of driving 2.1Vrms at 3.3V into
2.5kΩ load, and provides short-circuit and thermal pro-
High PSRR: 80dB at 217Hz
tection.
Fast Start-up Time: 500µs
Integrate the De-Pop Circuitry
Simplified Application Circuit
Thermal and Short-Circuit Protection
Surface-Mount Packaging
-MSOP-10P
Lead Free and Green Devices Available
(RoHS Compliant)
Stereo Input
Signal
Applications
•
•
•
•
APA2173
Stereo
Line-Out
Signal
Set-Top Boxes
CD/DVD Players
LCD TVs
HTIBs (Home Theater in Box)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
1
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APA2173
Pin Configuration
RINN 1
10 LINN
ROUT 2
9 LOUT
SDN 3
GND
8 UVP
VSS 4
7 VDD
CPN 5
6 CPP
MSOP-10
(Top View)
Ordering and Marking Information
Package Code
XA: MSOP-10P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA2173
Assembly Material
Handling Code
Temperature Range
Package Code
APA2173 XA :
APA2173
XXX
XX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VPGND_GND
(Note 1)
Parameter
Rating
PGND to GND Voltage
VDD
Supply Voltage (VDD to GND and PGND)
VSDN
Input Voltage (SDN to GND)
Unit
-0.3 to 0.3
-0.3 to 6.0
VGND-0.3 to VDD+0.3
V
VSS
VSS to GND and PGND Voltage
-6.0 to 0.3
VOUT
ROUT and LOUT to GND Voltage
VSS-0.3 to VDD+0.3
VCPP
CPP to PGND Voltage
VPGND-0.3 to VDD+0.3
VCPN
CPN to PGND Voltage
VSS-0.3 to VPGND+0.3
TJ
Maximum Junction Temperature
150
TSTG
Storage Temperature Range
TSDR
Maximum Soldering Temperature Range, 10 Seconds
PD
o
C
-65 to +150
Power Dissipation
260
Internally Limited
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
2
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APA2173
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Unit
Thermal Resistance - Junction to Ambient (Note 2)
O
MSOP-10P
60
C/W
Note 2: Please refer to “Thermal Pad Consideration”. 2 layered 5 in2 printed circuit boards with 2oz trace and copper through several
thermal vias. The thermal pad is soldered on the PCB.
Recommended Operating Conditions
Symbol
Range
Parameter
VDD
Supply Voltage
VIH
High Level Threshold Voltage
SDN
VIL
Low Level Threshold Voltage
SDN
TA
Operating Ambient Temperature Range
Unit
Min.
Max.
2.3
5.5
1.0
-
-
0.35
-40
85
o
o
V
C
TJ
Operating Junction Temperature Range
-40
125
RL
Load Resistance
16
100k
C
Ω
Electrical Characteristics
o
VDD=3.3V, VGND=VPGND=0V, VSDN=VDD, CCPF=CCPO=1µF, Ci=2.2µF, RL=2.5kΩ, TA=25 C, Ri=10kΩ, Rf=20kΩ (unless otherwise noted)
Symbol
Parameter
APA2173
Test Conditions
Unit
Min.
Typ.
Max.
-
10
15
mA
IDD
VDD Supply Current
ISD
VDD Shutdown Current
VSDN=0V
-
1
5
µA
Input Current
SDN
-
0.1
-
µA
400
500
600
kHz
-
21
25
Ω
Il
CHARGE PUMP
fOSC
Switching Frequency
Req
Equivalent Resistance
DRIVERS
AVO
Open Loop Voltage Gain
80
100
-
dB
GW
Unity Gain Bandwidth
8
10
-
MHz
VSR
Slew Rate
-
4.5
-
V/µs
VOS
Output Offset Voltage
VDD=2.3V to 5.5V, RL = 2.5kΩ
-5
-
5
mV
VN
Output Noise
Ri=10kΩ, Rf=10kΩ
-
8
15
µVrms
Tstart-up
Start-up Time
-
500
-
µs
-80
-80
-50
-60
-60
-45
-
220
-
pF
-
8
-
kV
PSRR
CL
VESD
Power Supply Rejection Ratio
VDD=2.3V to 5.5V, Vrr=200mVrms
fin= 217Hz
fin= 1kHz
fin= 20kHz
Maximum Capacitive Load
ESD Protection
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
OUTR, OUTL
3
-
dB
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APA2173
Electrical Characteristics (Cont.)
o
VDD=3.3V, VGND=VPGND=0V, VSDN=VDD, CCPF=CCPO=1µF, Ci=2.2µF, RL=2.5kΩ, TA=25 C, Ri=10kΩ, Rf=20kΩ (unless otherwise noted)
Symbol
VO
Parameter
Output Voltage (Stereo, In
Phase)
THD+N=1%, fin=1kHz
RL=2.5kΩ
RL=100kΩ
THD+N=1%, fin=1kHz
RL=32Ω
PO
THD+N
APA2173
Test Conditions
Unit
Min.
Typ.
Max.
2.0
-
2.1
2.3
-
-
20
-
Output Power (Stereo, In
Phase)
Total Harmonic Distortion Plus
Noise
V
mW
VDD=5V
THD+N=1%, fin=1kHz
RL=32Ω
-
VO=2Vrms, RL=2.5kΩ
fin=20Hz
fin=1kHz
fin=20kHz
-
Po=10mW, RL=32Ω,fin=1kHz
60
-
0.02
0.001
0.02
0.002
-
-
0.03
-
VDD=5V, Po=30mW, RL=32Ω,
fin=1kHz
-
0.03
-
-
Crosstalk
Channel Separation
VO=2Vrms, RL=2.5kΩ
fin=20Hz
fin=1kHz
fin=20kHz
S/N
Signal to Noise Ratio
VO=2Vrms, RL=2.5kΩ, Ri=10kΩ,
Rf=10kΩ,
With A-weighting Filter
TSD
Thermal Shutdown Protection
Temperature
100
100
90
%
-
dB
102
108
-
dB
-
150
-
o
C
UVP FUNCTION
VUVP
External Under Voltage
Detection
-
1.25
-
V
IHYS
External Under Voltage
Detection Hysteresis Current
-
5.0
-
µA
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
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APA2173
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
10
1
VDD=3.3V
VDD=5V
0.1
0.01
0
THD+N (%)
THD+N (%)
1
In Phase
RL=32Ω
Cin=2.2µF
fin=1kHz
Av=2V/V
20
40
60
80
100
VDD=3.3V
0.1
Out Phase
RL=32Ω
Cin=2.2µF
fin=1kHz
Av=2V/V
0.01
0
120
Output Power (mW)
40
60
80
100
120
THD+N vs. Output Voltage
THD+N vs. Output Voltage
10
In phase
RL=600Ω
Cin=2.2µF
fin=1kHz
Av=2V/V
0.1
In phase
RL=10kΩ
Cin=2.2µF
fin=1kHz
Av=2V/V
1
VDD=3.3V
THD+N (%)
1
THD+N (%)
20
Output Power (mW)
10
VDD=2.3V
0.01
0.1
VDD=3.3V
VDD=2.3V
0.01
VDD=5V
VDD=5V
0.001
0.001
0
2
1
3
0
4
1
0.1
0.1
VDD=3.3V
THD+N (%)
1
VDD=2.3V
0.01
3
4
THD+N vs. Frequency
THD+N vs. Output Voltage
10
In phase
RL=100kΩ
Cin=2.2µF
fin=1kHz
Av=2V/V
2
1
Output Voltage (V)
Output Voltage (V)
THD+N (%)
VDD=5V
In phase
VDD=3.3V
RL=32Ω
Cin=2.2µF
Av=2V/V
AES-17(20kHz)
Po=1mW
0.01
Po=10mW
VDD=5V
Po=5mW
0.001
0
1
2
3
0.001
20
4
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
100
1k
10k 20k
Frequency (Hz)
Output Voltage (V)
5
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APA2173
Typical Operating Characteristics
THD+N vs. Frequency
1
In phase
VDD=3.3V
RL=600Ω
Cin=2.2µF
Av=2V/V
AES-17(20kHz)
0.1
THD+N (%)
0.1
THD+N (%)
THD+N vs. Frequency
1
In phase
VDD=5V
RL=32Ω
Cin=2.2µF
Av=2V/V
AES-17(20kHz)
Po=3mW
0.01
Po=30mW
Vo=2Vrms
0.01
Vo=1Vrms
Po=15mW
0.001
0.001
20
100
1k
10k 20k
20
Frequency (Hz)
1k
THD+N vs. Frequency
THD+N vs. Frequency
1
In phase
VDD=3.3V
RL=10kΩ
Cin=2.2µF
Av=2V/V
AES-17(20kHz)
In phase
VDD=3.3V
RL=100kΩ
Cin=2.2µF
Av=2V/V
AES-17(20kHz)
0.1
THD+N (%)
0.1
0.01
0.01
Vo=2Vrms
Vo=1Vrms
Vo=2Vrms
Vo=1Vrms
0.001
0.001
20
100
1k
10k 20k
20
100
Frequency (Hz)
+10
-50
+0
-50
+8
Gain
Gain
-100
+2
+0
-2
10
VDD=3.3V
RL=600Ω
Vo=2Vrms
Cin=2.2µF
Av=2V/V
100
-200
Gain(dB)
Phase
-150
+4
+2
-250
-300
+0
-350
1k
10k
-2
10
200k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
-200
Phase
VDD=3.3V
RL=10kΩ
Vo=2Vrms
Cin=2.2µF
Av=2V/V
100
Phase(Deg)
-150
-100
+6
Phase(Deg)
+6
+4
10k 20k
Frequency Response
+0
+8
1k
Frequency (Hz)
Frequency Response
+10
Gain(dB)
10k 20k
Frequency (Hz)
1
THD+N (%)
100
-250
-300
-350
1k
10k
200k
Frequency (Hz)
6
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APA2173
Typical Operating Characteristics (Cont.)
Frequency Response
Crosstalk vs. Frequency
+10
+8
+0
-60
-50
-70
-100
-80
VDD=3.3V
RL=600Ω
Vo=2Vrms
Cin=2.2µF
Av=2V/V
Gain
-200
Phase
+2
VDD=3.3V
RL=100kΩ
Vo=2Vrms
Cin=2.2µF
Av=2V/V
+0
-2
10
Crosstalk(dB)
Gain(dB)
-150
+4
Phase(Deg)
+6
-90
-100
-250
Left to Right
-110
-300
-120
Right to Left
-350
100
1k
10k
-130
200k
Frequency (Hz)
20
100
Output Noise Voltage(Vrms )
-80
Crosstalk(dB)
20µ
VDD=3.3V
RL=100kΩ
Vo=2Vrms
Cin=2.2µF
Av=2V/V
-70
-90
-100
Left to Right
-110
-120
-130
16 µ
12µ
Left channel
8µ
Right channel
V DD=3.3V
R L=600Ω
C in =2.2µF
A v=1V/V
A -Weighting
4µ
Right to Left
0µ
20
100
1k
10k 20k
0
10
20
30
Time (Sec)
Frequency (Hz)
Output Noise Voltage vs. Time
PSRR vs. Frequency
0
Power Supply Rejection Ratio(dB)
20µ
Output Noise Voltage(Vrms )
10k 20k
Output Noise Voltage vs. Time
Crosstalk vs. Frequency
-60
1k
Frequency (Hz)
16 µ
12µ
Left channel
8µ
Right channel
V DD=3.3V
R L=100kΩ
C in =2.2µF
A v=1V/V
A -Weighting
4µ
0µ
0
10
20
-40
-60
-80
Left channel
Right channel
-100
-120
20
30
100
1k
10k 20k
Frequency (Hz)
Time (Sec)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
-20
VDD=3.3V
RL=600Ω
Cin=2.2µF
Av=1V/V
Vrr=0.2Vpp
7
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APA2173
Typical Operating Characteristics (Cont.)
PSRR vs. Frequency
Supply Current vs. Supply Voltage
-20
-40
10
VDD=3.3V
RL=100kΩ
Cin=2.2µF
Av=1V/V
Vrr=0.2Vpp
No Load
Av=2V/V
8
Supply Current(mA)
Power Supply Rejection Ratio(dB)
0
-60
-80
Left channel
Right channel
-100
-120
20
100
1k
4
2
0
10k 20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
6
0
1
2
3
4
5
Supply Voltage(V)
8
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APA2173
Pin Description
PIN
I/O/P
FUNCTION
NO.
NAME
1
RINN
I
Right channel inverting input.
2
ROUT
O
Right channel output.
3
SDN
I
Shutdown mod control input signal, pull low for shutdown headphone driver. This
pin should be connect a 100Ω Protection Resistor.
4
VSS
P
Headphone driver negative power supply.
5
CPN
I/O
6
CPP
I/O
7
VDD
P
Supply voltage input.
8
UVP
I
Under voltage protection input. Floating or Pull “H” to disable this function.
Charge pump flying capacitor negative connection.
Charge pump flying capacitor positive connection.
9
LOUT
O
Left channel output.
10
LINN
I
Left channel inverting input.
Exposed Pad
GND
P
Signal ground.
Block Diagram
RINN
ROUT
LOUT
LINN
Under Voltage
Detection Circuit
Thermal
and Over
Current
Protection
SDN
Shutdown
Circuit
VDD
Power
and
Depop
Circuit
CPP
Charge
Pump
CPN
VSS
GND
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
UVP
9
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APA2173
Typical Application Circuit
Line Driver Amplifier
RFB
R-CH
Input
CIN
1µF
RFB
RIN
R-CH
Output
RINN
ROUT
System
Power
CIN
1µF
L-CH
Input
L-CH
Output
LOUT
RIN
R1
3kΩ
LINN
Under Voltage
Detection Circuit
Thermal
and Over
Current
Protection
Shutdown SDN
Control
UVP
VDD
Power
and
Depop
Circuit
Shutdown
Circuit
LDO
CPP
Charge
Pump
R2
1kΩ
R3
50kΩ
10µF
1µF
CCPF
1µF
CPN
VSS
CCPO
1µF
GND
Second-Order Active Low-Pass Filter
R2
C3
R1
C1
R3
RINN
R-CH
Input
ROUT
COUT
220pF
C2
R2
C2
L-CH
Input
R1
R-CH
Output
COUT
220pF
C1
R3
LOUT
LINN
C3
Under Voltage
Detection Circuit
Thermal
and Over
Current
Protection
Shutdown SDN
Control
Shutdown
Circuit
L-CH
Output
UVP
VDD
Power
and
Depop
Circuit
System
Power
R3
50kΩ
CCPF
R2
1kΩ
LDO
CPP
Charge
Pump
R1
3kΩ
1µF
10µF
1µF
CPN
VSS
CCPO
1µF
GND
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
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APA2173
Function Description
Line Driver Operation
Shutdown Function
In order to reduce power consumption while not in use,
the APA2173 contains shutdown controllers to externally
VDD
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the
VOUT
VDD/2
SDN pins for the APA2173. The trigger point between a
logic high is 1.0V and logic low level is 0.35V. It is recomGND
mended to switch between ground and the supply voltage VDD to provide maximum device performance. By
Conventional Line Driver
switching the SDN pins to a low level, the amplifier enters
a low-consumption current circumstance, charge pump
VDD
is disabled, and IDD for the APA2173 is in shutdown mode.
In normal operating, the APA2173’s SDN pins should be
pulled to a high level to keep the IC out of the shutdown
mode. The SDN pins should be tied to a definite voltage
VOUT
GND
to avoid unwanted circumstance changes.
Under-Voltage Protection
External under voltage detection can be used to shutdown the APA2173 before an input device can generate a
VSS
pop. The shutdown threshold at the UVP pin is 1.25V.
The user selects a resistor divider to obtain the shut-
Cap-free Line Driver
down threshold and hysteresis for the specific application.
The thresholds can be determined as below:
Figure 1. Cap-free Operation
The APA2173’s line drivers use a charge pump to invert
the positive power supply (VDD) to negative power supply
VUVP = (1.25-6µAxR3) x (R1+R2)/R2
Hysteresis = 5µA x R3 x (R1+R2)/R2
(VSS), see figure1. The headphone drivers operate at this
bipolar power supply (VDD and VSS) and the outputs refer-
With the condition: R3>>R1//R2
For example, to obtain VUVP=3.8V and 1V hysteresis, R1=
ence refers to the ground. This feature eliminates the
output capacitor that is using in conventional single-ended
3kΩ, R2=1kΩ and R3=50kΩ.
headphone drive amplifier. Compare with the single
power supply amplifier, the power supply range has al-
Vsystem
most doubled.
R1
3kΩ
Thermal Protection
The thermal protection circuit limits the junction temperature of the APA2173. When the junction temperature exceeds TJ=+150OC, a thermal sensor turns off the driver,
R2
1kΩ
R3
50kΩ
UVP Pin
1.25V
6µA
allowing the devices to cool. The thermal sensor allows
the driver to start-up after the junction temperature down
about 125OC. The thermal protection is designed with a
25OC hysteresis to lower the average TJ during continu-
Figure 2. Under-Voltage Protection
ous thermal overload conditions, increasing lifetime of
the ICs.
Copyright  ANPEC Electronics Corp.
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APA2173
Application Information
Input Capacitor, Ci
Using The APA2173 As A Second-Order Filter
Several audio DACs used today require an external lowpass filter to remove out-of-band noise. This is possible
Ri
Ci
Rf
with the APA2173, as it can be used like a standard Operational Amplifier. Several filter topologies can be
implemented, both single-ended and differential. In Figure 3, a multi-feedback (MFB) with differential input and
Figure 4. Typical Application Circuit
single-ended input is shown.
An ac-coupling capacitor to remove dc content from the
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
source is shown; it serves to block any dc content from
the source and lowers the dc-gain to 1, helping reducing
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri from a high-pass filter with
the output dc-offset to minimum.
R2
Cx
C3 R1 R3
Cy 6pF
In
C2 C1
the corner frequency are determined in the following
equation:
Differential Input
R2
Cx
C3 R1 R3
Cy 6pF
In C2 C1
Inverting Input
Out
C3 R1 R3
Cout
In +
220pF
C1
fc (highpass ) =
Out
Cout
220pF
circuit. Ri is the external input resistance that typical value
is 10kΩ and the specification calls for a flat bass re-
Figure 3. Second-Order Active Low-Pass Filter
sponse down to 20Hz. Equation is reconfigured as below:
Table 1: Filter Specifications.
High Low
Gain
C1
Pass Pass
(V/V)
(pF)
(Hz) (kHz)
Ci =
C2
(pF)
C3
(µF)
R1
(kΩ)
R2
(kΩ)
R3
(kΩ)
-1
1.6
40
100
680
10
10
10
24
-1.5
1.3
40
68
680
15
8.2
12
30
-2
1.6
60
33
150
6.8
15
30
47
-2
1.6
30
47
470
6.8
15
30
43
-3.33
1.2
30
33
470
10
13
43
43
-10
1.5
30
22
1000
22
4.7
47
27
leakage path from the input source through the input network (Ri + Rf, Ci) to the load.
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low
leakage tantalum or ceramic capacitor is the best choice.
When polarized capacitors are used, the negative side of
the capacitor should face the amplifiers’ input in most
(1)
1
2πR1C3
applications because the DC level of the amplifiers’ input is held at GND. Please note that it is important to
(2)
confirm the capacitor polarity in the application.
Input Resistor, Ri
The low pass filter’s cutoff frequency is:
fc(lowpass) =
1
2π R2R3C1C2
(5)
is 0.8µF, so a value in the range of 1µF to 2.2µF would be
chosen. A further consideration for this capacitor is the
The high pass filter’s cutoff frequency is:
fc(highpass) =
1
2πRifc(highpass)
When the input resistance variation is considered, the Ci
For Inverting Input, The overall gain is:
R2
AV = −
R1
(4)
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the
R2
Cx+Cy=C1
Cy:internal Capacitance(6pF)
Cx+Cy=C1
Cy:internal Capacitance(6pF)
1
2πRiCi
The gain of the APA2173 is be set by the external input
resistor (Ri) and external feedback resistor (Rf). Please
(3)
see the figure 4.
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12
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APA2173
Application Information (Cont.)
Input Resistor, Ri (Cont.)
Gain ( A V ) =
Rf
Ri
Charge Pump Output Capacitor, CCPO
The output capacitor’s value affects the power ripple di-
(6)
rectly at CVSS (VSS). Increasing the value of output capacitor reduces the power ripple. The ESR of output capacitor
The external gain setting is recommended using from
-1V/V to -10V/V, and the Ri is in the range from 1kΩ to
affects the load transient of CVSS (VSS). Lower ESR and
greater than 1µF ceramic capacitor is a recommendation.
47kΩ. It’s recommended to use 1% tolerance resistor or
better. Keep the input trace as short as possible to limit
the noise injection.
The gain is recommended to set -1V/V, and Ri is 10kΩ,
and Rf is 10kΩ.
Feedback Resistor, Rf
Refer the figure 4, the external gain is setting by Ri and Rf;
and the gain setting is recommended using from -1V/V to
-10V/V. The Rf is in the range from 4.7kΩ to 100kΩ. It’s
recommended to use 1% tolerance resistor or better.
Power Supply Decoupling, Cs
The APA2173 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length
between the amplifier and the speaker.
The optimum decoupling is achieved by using two different types of capacitors that target on different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1µF, is placed as close as possible to the device VDD and PVDD lead for the best performance. For
filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near
the audio power amplifier is recommended.
Charge Pump Flying Capacitor, CCPF
The flying capacitor affects the load transient of the charge
pump. If the capacitor’s value is too small, then that will
degrade the charge pump’s current driver capability and
the performance of line drive amplifier.
Increasing the flying capacitor’s value will improve the
load transient of charge pump. It is recommended using
the low ESR ceramic capacitors (X7R type is recommended) above 1µF.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
13
www.anpec.com.tw
APA2173
Package Information
MSOP-10P
D
SEE
VIEW A
E
E2
EXPOSED
PAD
E1
D1
c
e
0.25
A
GAUGE PLANE
SEATING PLANE
A1
L
VIEW A
S
Y
M
B
O
L
0
A2
b
MSOP-10P
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.10
0.043
A1
0.00
0.15
0.000
0.006
A2
0.75
0.95
0.030
0.037
b
0.17
0.33
0.007
0.013
c
0.08
0.23
0.003
0.009
D
2.90
3.10
0.114
0.122
D1
1.50
2.50
0.059
0.098
E
4.70
5.10
0.185
0.201
E1
2.90
3.10
0.114
0.122
E2
1.50
2.50
0.059
e
0.50 BSC
0.098
0.020 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 BA-T.
2. Dimension “D”does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not flash or protrusions.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 6 mil per side.
Copyright  ANPEC Electronics Corp.
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APA2173
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
MSOP-10P
A
H
330.0±2.00
50 MIN.
P0
P1
T1
12.4+2.00
-0.00
P2
4.00±0.10
8.00±0.10
2.00±0.05
C
13.0+0.50
-0.20
D0
1.5+0.10
-0.00
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
D1
T
0.6+0.00
-0.40
A0
B0
K0
5.30±0.20
3.30±0.20
1.40±0.20
1.5 MIN.
(mm)
Devices Per Unit
Package Type
Unit
Quantity
MSOP-10P
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
15
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APA2173
Taping Direction Information
MSOP-10P
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
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APA2173
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Rev. A.1 - Mar., 2014
17
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APA2173
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Mar., 2014
18
www.anpec.com.tw