ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 • • • • • • • • • • 8-Bit Resolution Easy Microprocessor Interface or StandAlone Operation Operates Ratiometrically or With 5-V Reference 4- or 8-Channel Multiplexer Options With Address Logic Shunt Regulator Allows Operation With High-Voltage Supplies Input Range 0 to 5 V With Single 5-V Supply Remote Operation With Serial Data Link Inputs and Outputs are Compatible With TTL and MOS Conversion Time of 32 µs at fclock = 250 kHz Designed to Be Interchangeable With National Semiconductor ADC0834 and ADC0838 DEVICE TOTAL UNADJUSTED ERROR A SUFFIX B SUFFIX ADC0834 ± 1 LSB ± 1/2 LSB ADC0838 ± 1 LSB ± 1/2 LSB AD0834 . . . N PACKAGE (TOP VIEW) V+ CS CH0 CH1 CH2 CH3 DGTL GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC DI CLK SARS DO REF ANLG GND ADC0838 . . . N PACKAGE (TOP VIEW) CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGTL GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC V+ CS DI CLK SARS DO SE REF ANLG GND ADC0838 . . . FN PACKAGE description CH2 CH1 CH0 VCC V+ (TOP VIEW) COM DGTL GND ANLG GND REF SE These devices are 8-bit successive- approximation analog-to-digital converters, each with an input-configurable multichannel multi3 2 1 20 19 CH3 18 CS 4 plexer and serial input/output. The serial input/ CH4 17 DI 5 output is configured to interface with standard shift CH5 16 CLK 6 registers or microprocessors. Detailed informaCH6 15 SARS 7 tion on interfacing with most popular microproces14 DO CH7 8 sors is readily available from the factory. 9 10 11 12 13 The ADC0834 (4-channel) and ADC0838 (8-channel) multiplexer is software configured forsingle-ended or differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows for commonmode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation from 0°C to 70°C. The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from – 40°C to 85°C. Copyright 1986, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CS CLK CS DI (see Note A) SARS R D S 5-Bit Shift Register R CLK SELECT0 SELECT1 ADC0838 Only SE POST OFFICE BOX 655303 ADC0834 ADC0838 ODD\EVEN SGL\DIF START To Internals Circuits CLK CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog MUX S Time Delay • DALLAS, TEXAS 75265 EN CS Comparator EN REF Ladder and Decoder 7V CS CS R R SAR Logic and Latch Bits 0–7 To Internal Circuits VCC R One Shot CS CS CLK Bits 0–7 Bit 1 MSB First V+ 7V NOTE A: For the ADC0834, DI is input directly to the D input of SELECT 1; SELECT 0 is forced to a high. LSB First 9-Bit Shift Register EOC R CLK DO D ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL Start Flip-Flop CLK SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 2 functional block diagram ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 functional description The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal and is compared to ground (single-ended), to an adjacent input (differential), or to a common terminal (pseudo-differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–) polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer address is shifted into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single-ended or differential. When the input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage on the common input is considered to be the negative differential input for all channel inputs. This voltage can be any reference potential common to all channel inputs. Each channel input can then be selected as the positive differential input. This feature is useful when all analog circuits are biased to a potential other than ground. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR Status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is disabled the duration of the conversion. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. The data output DO comes out of the high-impedance state and provides a leading low for this one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive ladder output. As the conversion proceeds, conversion data is simultaneously output from the DO output pin, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete and the SARS output goes low. The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If SE is held high on the ADC0838, the value of the least significant bit (LSB) will remain on the data line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 functional description (continued) DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer addressing interval and DO is still in a high-impedance state. Detailed information on interfacing to most popular microprocessors is readily available from the factory. sequence of operation ADC0834 1 2 3 4 5 6 7 10 11 12 13 14 18 15 19 20 21 CLK tconv tsu CS Start Bit tsu +Sign Select Bit CH Bit 1 SGL Odd Don’t Care DI DIF Even 1 Hi-Z SARS Max Settling Time DO MSB-First Data LSB-First Data Hi-Z Hi-Z MSB 7 LSB 6 2 1 MSB 0 1 2 6 ADC0834 MUX ADDRESS CONTROL LOGIC TABLE MUX ADDRESS SGL/DIF ODD/EVEN CHANNEL NUMBER SELECT BIT 1 L L L L L L H H L H L H H H H H L L H H L H L H O 1 + – – + + POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 + – – + + + H = high level, L = low level, – or + = polarity of selected input pin 4 2 + 7 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 sequence of operation ADC0838 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 CLK tconv tsu CS MUX Addressing tSU Start Bit DI SGL + Sign Odd DIF Even SEL SEL Bit1 Bit0 1 0 Dont Care 1 0 HI-Z HI-Z SARS SE MUX Settling Time HI-Z DO LSB-First Data MSB-First Data HI-Z 7 MSB LSB MSB 6 2 1 0 1 2 3 4 5 6 7 SE Used to Control LSB First Data SE MUX Settling Time LSB-Held MSB-First Data DO MSB 7 LSB-First Data MSB LSB 6 2 1 POST OFFICE BOX 655303 0 1 • DALLAS, TEXAS 75265 2 3 4 5 6 7 5 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 ADC0838 MUX ADDRESS CONTROL LOGIC TABLE SELECTED CHANNEL NUMBER MUX ADDRESS SGL/DIF ODD/EVEN L L L L L SELECT 1 0 0 0 1 L L + – L H L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H – 1 2 3 + – 2 4 5 + – 3 6 7 + – – + COM + – + – + + – + – + – + – + – + – + – + – H = high level, L = low level, – or + = polarity of selected input absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC+ 0.3 V Input current: V+ input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Any other input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Total input current for package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating free-air temperature range: AC and BC suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C AI and BI suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal. 2. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less than the zener breakdown voltage. A series resist or is recommended to limit current into the V+ input. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 recommended operating conditions VCC VIH Supply voltage VIL fclock Low-level input voltage TA NOM MAX 4.5 5 6.3 High-level input voltage 2 UNIT V V 0.8 V Clock frequency 10 400 kHz Clock duty cycle (see Note 3) 40 60 % twH(CS) Pulse duration, CS high tsu Setup time, CS low, SE low, or data valid before clock↑ th MIN Hold time, data valid after clock↑ Operating O erating free-air temperature tem erature 220 ns 350 ns 90 AC and BC suffixes AI and BI suffixes ns 0 70 – 40 85 °C NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended duty cycle range, the minimum pulse duration (high or low) is 1 µs. electrical characteristics over recommended range of operating free-air temperature, VCC = V+ = 5 V, fclock = 250 kHz (unless otherwise noted) digital section PARAMETER VOH High levl output voltage High-levl VOL IIH Low-levl output voltage IIL IOH Low-level input current IOL Low-level output (sink) current IOZ High-impedance-state output g current (DO or SARS) Ci High-level input current High-level output (source) current TEST CONDITIONS† VCC = 4.75 V, VCC = 4.75 V, IOH = – 360 µA IOH = – 10 µA VCC = 5.25 V, VIH = 5 V IOH = 1.6 mA VIL = 0 VOH = 0, VOL = VCC, VO = 5 V, VO = 0, TA = 25°C TA = 25°C AC, BC SUFFIX TYP‡ MAX AI, BI SUFFIX TYP‡ MAX MIN MIN 2.8 2.4 4.6 4.5 V 0.34 0.005 1 – 0.005 –1 – 6.5 8 TA = 25°C TA = 25°C Input capacitance – 14 – 6.5 16 8 0.4 V 0.005 1 µA – 0.005 –1 – 14 16 • DALLAS, TEXAS 75265 mA 3 0.01 3 – 0.01 –3 – 0.01 –3 5 µA mA 0.01 Co Output capacitance 5 † All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified). ‡ All typical values are at VCC = V+ = 5 V, TA = 25°C. POST OFFICE BOX 655303 UNIT µA pF pF 7 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 electrical characteristics over recommended range of operating free-air temperature, VCC = V + = 5 V, fclock = 250 kHz (unless otherwise noted) (continued) analog and converter section TEST CONDITIONS† PARAMETER MIN TYP‡ MAX UNIT – 0.05 VICR Common-mode input voltage range See Note 3 to V VCC+ 0.05 On-channel II(stdby) Standby input current (see Note 4) ri(REF) Input resistance to reference ladder Off-channel On-channel Off–channel VI = 5 V VI = 0 1 –1 VI = 0 VI = 5 V –1 µA 1 1.3 2.4 5.9 kΩ total device PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT VZ Internal zener diode breakdown voltage II = 15 mA at V+ pin, See Note 2 6.3 7 8.5 V ICC Supply current 1 2.5 mA † All parameters are measured under open-loop conditions with zero common-mode input voltage. ‡ All typical values are at VCC = 5 V, V+ = 5 V, TA = 25°C. NOTES: 4. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input. 5. If channel IN– is more positive than channel IN+, the digital output code will be 0000 0000. Connected to each analog input are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC .Care must be taken during testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode to conduct and cause errors for analog input s that are near full-scale. As long as the analog voltage does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input voltage range requires a minimum VCC of 4.950 V for all variations of temperature and load. 6. Standby input currents are currents going into or out of the on or off channels when the A/D converter is not performing conversion and the clock is in a high or low steady-state condition. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 operating characteristics V + = 5 V, fclock = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise noted) PARAMETER MAX VCC = 4.75 V to 5.25 V Vref = 5 V, TA = MIN to MAX ± 1/16 ± 1/4 Common-mode error Differential mode ± 1/16 Change in zero-error from VCC = 5 V to internal zener diode operation (see Note 2) II = 15 mA at V+ pin, Vref = 5 V, VCC open Total unadjusted error (see Note 6) tdos Propagation delay time, output MSB-first data data after CLK↓, (see Note 7) LSB-first data MIN BI, BC SUFFIX TYP Supply-voltage variation error tpd AI, AC SUFFIX TEST CONDITIONS MIN MAX ± 1/16 ± 1/4 LSB ± 1/2 LSB ± 1/4 LSB 1 LSB ±1 ± 1/4 ± 1/16 1 CL = 100 pF Output disable time, CL = 10 pF, RL = 10 kΩ DO or SARS after CS↑ CL = 100 pF, RL = 2 kΩ 650 1500 650 1500 250 600 250 600 125 250 125 250 500 UNIT TYP 500 ns ns clock tconv Conversion time (multiplexer addressing 8 8 time not included) periods † All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTES:2. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each zener diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input. 6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow for comparator response time. PARAMETER MEASUREMENT INFORMATION VCC CLK 50% 50% GND tsu tsu VCC CS 0.4 V GND th th 2V VCC 2V DI 0.4 V 0.4 V GND Figure 1. Data Input Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 PARAMETER MEASUREMENT INFORMATION VCC 50% 50% CLK GND tpd tpd VCC 50% DO 50% GND tsu VCC 50% SE GND Figure 2. Data Output Timing VCC Test Point S1 RL From Output Under Test CL (see Note A) S2 LOAD CIRCUIT tr CS 50% tr VCC 90% 10% CS 10% GND S1 open S2 closed 90% VCC DO and SARS S1 open S2 closed GND –VCC 10% VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Output Disable Time Test Circuit and Voltage Waveforms 10 GND tdis tdis DO and SARS VCC 90% 50% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GND ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 TYPICAL CHARACTERISTICS UNADJUSTED OFFSET ERROR vs REFERENCE VOLTAGE LINEARITY ERROR vs REFERENCE VOLTAGE 16 1.5 VI(+) = VI(–) = 0 V VCC = 5 V fclock = 250 kHz TA = 25°C 14 1.25 Linearity Error – LSB Offset Error – LSB 12 10 8 6 1 0.75 0.5 4 0.25 2 0 0.01 0.1 1 0 10 1 0 Vref – Reference Voltage – V 2 5 Figure 5 LINEARITY ERROR vs FREE-AIR TEMPERATURE LINEARITY ERROR vs CLOCK FREQUENCY 0.5 3 Vref = 5 V fclock = 250 kHz Vref = 5 V VCC = 5 V 2.5 Linearity Error – LSB 0.45 Linearity Error – LSB 4 Vref – Reference Voltage – V Figure 4 0.4 0.35 0.3 0.25 –50 3 2 1.5 85°C 1 25°C – 40°C 0.5 –25 0 25 50 75 100 0 0 100 TA – Free-Air Tempertature – °C 200 300 400 500 600 fclock – Clock Frequency – kHz Figure 6 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 ADC0834A, ADC0838A, ADC0834B, ADC0838B A/D PERIPHERALS WITH SERIAL CONTROL SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.5 1.5 VCC = 5 V TA = 25°C I CC – Supply Current – mA I CC – Supply Current – mA fclock = 250 kHz CS = High VCC = 5.5 V VCC = 5 V 1 VCC = 4.5 V 0.5 –50 –25 0 25 50 75 1 0.5 0 100 0 100 TA – Free-Air Temperature — °C 200 Figure 9 OUTPUT CURRENT vs FREE-AIR TEMPERATURE 25 VCC = 5 V I O – Output Current – mA 20 IOL (VOL = 5 V) 15 – IOH (VOH = 0 V) 10 – IOH (VOH = 2.4 V) 5 IOL (VOL = 0.4 V) – 25 0 25 50 75 TA – Free-Air Temperature – °C Figure 10 12 400 fclock – Clock Frequency – kHz Figure 8 0 – 50 300 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 500 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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