TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 FEATURES • • • • • • • • • • • • • • (1) Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Open-Drain Power-Good (PG) Status Output Available in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5-V Fixed-Output and Adjustable Versions Dropout Voltage Typically 200 mV at 250 mA Ultralow 92-µA Quiescent Current (Typ) 8-Pin MSOP (DGK) Package Low Noise (55 µVrms) Without an External Filter (Bypass) Capacitor 2% Tolerance Over Specified Conditions For Fixed-Output Versions Fast Transient Response Thermal Shutdown Protection See the TPS779xx Family of Devices for Active-High Enable Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DGK PACKAGE (TOP VIEW) FB/SENSE PG EN GND 1 8 2 7 3 6 4 5 OUT OUT IN IN DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 250 VDO − Dropout Voltage − mV • IO = 250 mA 200 150 100 IO = 10 mA 50 IO = 0 A 0 −50 −40 0 40 80 120 160 TJ − Junction Temperature − °C DESCRIPTION The TPS77401 is a low-dropout (LDO) regulator with power good (PG) function. This device is capable of supplying 250 mA of output current with a dropout of 200 mV. Quiescent current is 92 µA at full load dropping down to 1 µA when device is disabled. This device is optimized to be stable with a wide range of output capacitors including low-ESR ceramic (10-µF) or low-capacitance (1 µF) tantalum capacitors. This device has extremely low noise output performance (55 µVrms) without using any added filter capacitors. The TPS77401 is designed to have fast transient response for larger load current changes. The TPS77401 is offered in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS77401 device is available in an 8-pin mini small-outline package (MSOP) (DGK). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 DESCRIPTION (CONTINUED) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3-V option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 µA over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the enable (EN) pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = 25°C. For the TPS77401, the power good (PG) terminal is an active-high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS77401 monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG goes to a low-impedance state. PG goes to a high-impedance state when OUT is above 82% of its regulated voltage. AVAILABLE OPTIONS (1) OUTPUT VOLTAGE (V) TJ –55°C to 125°C (1) PACKAGED DEVICE MSOP (DGK) TYP ORDERABLE PART NUMBER SYMBOL Adjustable 1.5 V to 5.5 V TPS77401MDGKREP BYQ The TPS77401 is programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. VI 5 IN OUT 6 OUT IN SENSE 0.1 µF 3 PG EN 7 VO 8 1 2 PG Output + GND 10 µF 4 Figure 1. Typical Application Configuration (for Fixed-Output Options) 2 Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 FUNCTIONAL BLOCK DIAGRAMS ADJUSTABLE VERSION IN EN PG _ + OUT + _ R1 220 ms Delay Vref = 1.183 V FB/SENSE R2 External to the Device GND FIXED-VOLTAGE VERSION IN EN PG _ + OUT + _ SENSE 220 ms Delay R1 Vref = 1.183 V R2 GND TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options) PG 2 O Power good EN 3 I Enable GND 4 Regulator ground IN 5, 6 I Input voltage OUT 7, 8 O Regulated output voltage Submit Documentation Feedback 3 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 PG TIMING DIAGRAM VI Vres† Vres† t VO VIT +‡ VIT +‡ Threshold Voltage VIT −‡ VIT −‡ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ t PG Output Output Undefined 4 Output Undefined t † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡ VIT − Trip voltage is typically 18% lower than the output voltage (82%VO) VIT− to VIT+ is the hysteresis voltage. Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VI MIN MAX UNIT Input voltage range (2) –0.3 13.5 V Voltage range at EN –0.3 16.5 V 16.5 V Maximum PG voltage Peak output current Internally limited Continuous total power dissipation See Dissipation Rating Table VO Output voltage (OUT, FB) 5.5 V Tj Operating virtual junction temperature range (3) –55 125 °C Tstg Storage temperature range –65 150 °C 2 kV ESD rating, Human-Body Model (HBM) (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional infomation on enhanced plastic packaging Dissipation Ratings – Free-Air Temperatures PACKAGE AIR FLOW (CFM) θJA (°C/W) θJC (°C/W) TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW DGK 150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW 250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VI Input voltage (1) 2.7 10 V VO Output voltage range 1.5 5.5 V 0 250 mA –55 125 °C current (2) IO Output TJ Operating virtual junction temperature (2) (1) (2) UNIT To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. Submit Documentation Feedback 5 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 Electrical Characteristics over recommended operating junction temperature range (TJ = –55°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) PARAMETER TEST CONDITIONS Adjustable voltage 1.5 V ≤ VO ≤ 5.5 V TJ = Full range TJ = 25°C, 1.5-V output 1.5 2.856 3.366 5.0 4.9 TJ = 25°C 5.1 92 TJ = Full range 135 VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.005 VO + 1 V < VI ≤ 10 V Load regulation TJ = 25°C Output noise voltage BW = 300 Hz to 100 kHz, Output current limit VO = 0 V Peak output current 2 ms pulse width, TJ = 25°C 55 µVrms Adjustable voltage 3 1 2 Enable input current (2) (3) f = 1 kHz, TJ = 25°C 55 Minimum input voltage for valid PG I(PG) = 300 µA, V(PG) ≤ 0.8 V 1.1 Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, Leakage current V(PG) = 5 V µA 0.7 V 1 µA dB V 85 0.5 0.15 %VO 0.4 V 1 µA Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output current 1 mA. IO = 1 mA to 250 mA If VO < 1.8 V, then VI(max) = 10 V, VI(min) = 2.7 V: ǒ Ǔ VO V I(max) * 2.7 V 100 If VO > 2.5 V, then VI(max) = 10 V, VI(min) = VO + 1 V: Line regulation (mV) + ǒ%ńVǓ Line regulation (mV) + ǒ%ńVǓ 6 79 I(PG) = 1 mA µA V –1 PSRR Power-supply rejection ratio (1) °C TJ = Full range FB = 1.5 V A mA 1 Low-level enable input voltage PG 1.3 400 TJ = 25°C High-level enable input voltage %/V mV 144 EN = VI µA 1 0.9 50% duty cycle V %/V 0.05 Thermal shutdown junction temperature Standby current V 3.3 6 V < VIN < 10 V 6.0 V < VIN < 10 V Output voltage line regulation (∆VO/VO) (3) FB input current 2.754 2.8 3.234 TJ = 25°C, V 2.7 4.3 V < VIN < 10 V 4.3 V < VIN < 10 V V 1.836 2.744 TJ = 25°C, UNIT 1.8 3.8 V < VIN < 10 V 3.8 V < VIN < 10 V Quiescent current (GND current) (1) (2) 1.530 2.646 TJ = 25°C, 5-V output 1.023VO 3.7 V < VIN < 10 V 3.7 V < VIN < 10 V 3.3-V output 0.977VO 1.764 TJ = 25°C, MAX 1.02VO 2.8 V < VIN < 10 V 2.8 V < VIN < 10 V 2.8-V output TYP 1.470 TJ = 25°C, 2.7-V output MIN 0.98VO 2.7 V < VIN < 10 V 2.7 V < VIN < 10 V 1.8-V output Output voltage (1) (2) TJ = 125°C ǒ ǒ 1000 ǓǓ VO V I(max) * VO ) 1 100 1000 Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 Electrical Characteristics (continued) over recommended operating junction temperature range (TJ = –55°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 µF (unless otherwise noted) PARAMETER 2.8-V output VDO Dropout voltage (4) 3.3-V output 5-V output (4) TEST CONDITIONS IO = 250 mA, MIN TYP TJ = 25°C 270 TJ = 25°C 200 IO = 250 mA IO = 250 mA IO = 250 mA, MAX UNIT 475 TJ = Full Range TJ = 25°C IO = 250 mA 350 mV 125 190 IN voltage equals VO(typ) – 100 mV; 1.5-V, 1.8-V, and 2.7-V dropout voltage limited by input voltage range limitations (i.e., 3.3-V input voltage needs to drop to 3.2-V for purpose of this test). Submit Documentation Feedback 7 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Output voltage vs Output current 2, 3 vs Junction temperature 4, 5 Ground current vs Junction temperature 6 Power-supply rejection ratio vs Frequency 7 Output spectral noise density vs Frequency 8 Output impedance vs Frequency 9 vs Input voltage 10 vs Junction temperature 11 Dropout voltage Line transient response 12, 14 Load transient response 13, 15 Output voltage and enable pulse vs Time 16 Equivalent series resistance vs Output current 18–21 TPS77x18 TPS77x33 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.802 3.301 VO − Output Voltage − V VO − Output Voltage − V 3.302 3.3 1.801 1.800 1.799 3.299 1.798 3.298 0 50 100 150 200 IO − Output Current − mA 250 0 Figure 2. 8 50 100 150 200 IO − Output Current − mA Figure 3. Submit Documentation Feedback 250 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 TPS77x33 TPS77x18 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.86 3.35 VI = 2.8 V VI = 4.3 V 1.84 VO − Output Voltage − V VO − Output Voltage − V 3.33 IO = 250 mA 3.31 3.29 1.80 IO = 1 mA IO = 50 mA IO = 250 mA 1.78 3.27 3.25 −40 1.82 0 40 80 120 1.76 −40 160 0 TJ − Junction Temperature − °C 40 160 Figure 5. TPS77xxx TPS77x33 GROUND CURRENT vs JUNCTION TEMPERATURE POWER SUPPLY REJECTION RATIO vs FREQUENCY 115 PSRR − Power Supply Rejection Ratio − dB 100 110 Ground Current − µ A 120 TJ − Junction Temperature − °C Figure 4. 105 100 IO = 1 mA 95 90 85 IO = 250 mA 80 −40 80 90 IO = 1 mA CO = 10 µF TJ = 25 °C 80 70 60 50 40 30 IO = 250 mA 20 10 0 10 60 110 160 10 TJ − Junction Temperature − °C Figure 6. 100 1k 10k 100k 1M 10M f − Frequency − Hz Figure 7. Submit Documentation Feedback 9 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 TPS77x33 TPS77x33 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 10 CO = 10 µF TJ = 25 °C TJ = 25 °C IO = 250 mA IO = 1 mA Zo − Output Impedance − Ω Output Spectral Noise Density − µV Hz 10 1 IO = 1 mA 0.1 0.01 100 1k 10k 1 0.1 IO = 250 mA 0.01 10 100k f − Frequency − Hz 100 1k 10k 100k f − Frequency − Hz Figure 8. 1M 10M Figure 9. TPS77x01 TPS77x33 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 400 300 IO = 250 mA TJ = 125 °C 250 TJ = 25 °C 300 VDO − Dropout Voltage − mV VDO − Dropout Voltage − mV 350 TJ = −40 °C 250 200 150 100 200 150 100 IO = 10 mA 50 3.2 3.7 4.2 VI − Input Voltage − V 4.7 −50 −40 Figure 10. 10 IO = 0 A 0 50 0 2.7 IO = 250 mA 0 40 80 120 TJ − Junction Temperature − °C Figure 11. Submit Documentation Feedback 160 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com TPS77x18 TPS77x18 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO − Output Current − mA VI − Input Voltage − V SLVS702 – OCTOBER 2006 3.8 2.8 250 0 +50 ∆ VO − Change in Output Voltage − mV ∆ VO − Change in Output Voltage − mV 10 0 −10 CO = 10 µF TJ = 25 °C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t − Time − ms 0.9 0 −50 CO = 10 µF TJ = 25 °C IO = 250 mA 0 1 0.2 0.4 0.6 1.4 1.6 1.8 2 Figure 13. TPS77x33 TPS77x33 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO − Output Current − mA VI − Input Voltage − V Figure 12. 0.8 1 1.2 t − Time − ms 5.3 4.3 250 0 ∆ VO − Change in Output Voltage − mV ∆ VO − Change in Output Voltage − mV 10 0 −10 CO = 10 µF TJ = 25 °C IO = 250 mA 0 0.1 0.2 0.3 0.4 0.5 0.6 t − Time − ms 0.7 0.8 0.9 1 0 −50 CO = 10 µF TJ = 25 °C IO = 250 mA −100 0 Figure 14. 0.1 0.2 0.3 0.4 0.5 0.6 t − Time − ms 0.7 0.8 0.9 1 Figure 15. Submit Documentation Feedback 11 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 TPS77x33 VO − Output Voltage − V Enable Pulse − V OUTPUT VOLTAGE AND ENABLE PULSE vs TIME (AT STARTUP) CO = 10 µF TJ = 25 °C EN 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t − Time − ms 1.6 1.8 2.0 Figure 16. VI To Load IN OUT + EN CO RL GND ESR Figure 17. Test Circuit for Typical Regions of Stability (Figure 18 through Figure 21) (Fixed-Output Options) 12 Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 ESR − Equivalent Series Resistance − Ω ESR − Equivalent Series Resistance − Ω 10 Region of Instability VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 25°C 1 Region of Stability Region of Instability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 25°C Region of Instability Region of Instability 0.1 0 50 100 150 200 0.01 250 0 50 100 150 IO − Output Current − mA IO − Output Current − mA Figure 18. Figure 19. 200 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 250 10 10 ESR − Equivalent Series Resistance − Ω ESR − Equivalent Series Resistance − Ω Region of Instability Region of Instability VO = 3.3 V CO = 1 µF VI = 4.3 V TJ = 125 °C 1 Region of Stability 1 Region of Stability 0.1 VO = 3.3 V CO = 10 µF VI = 4.3 V TJ = 125°C Region of Instability Region of Instability 0.01 0.1 0 50 100 150 200 250 0 50 100 150 IO − Output Current − mA IO − Output Current − mA Figure 20. Figure 21. Submit Documentation Feedback 200 250 13 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 APPLICATION INFORMATION Pin Functions Enable (EN) The EN terminal is an input that enables or shuts down the device. If EN is a logic high, the device is in shutdown mode. When EN goes to logic low, the device is enabled. Power Good (PG) The PG terminal is an open-drain, active-high output that indicates the status of Vout (output of the LDO). When Vout reaches 82% of the regulated voltage, PG goes to a high-impedance state. It goes to a low-impedance state when Vout falls below 82% (i.e., overload condition) of the regulated voltage. The open-drain output of the PG terminal requires a pullup resistor. Sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. Feedback (FB) FB is an input terminal used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and Vout to filter noise is not recommended because it may cause the regulator to oscillate. External Capacitor Requirements An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load transient response and noise rejection if the device is located more than a few inches from the power supply. A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Most low-noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board space. The TPS77401 have very low noise specification requirements without using any external components. Like all LDO regulators, the TPS77401 requires an output capacitor connected between OUT (output of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended capacitance value is 1 µF, provided the ESR meets the requirement in Figure 19 and Figure 21. In addition, a low-ESR capacitor can be used if the capacitance is at least 10 µF and the ESR meets the requirements in Figure 18 and Figure 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements previously described. Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are, therefore, acceptable to use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature; therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type of capacitor is used, one must make certain that at the worst-case condition, the capacitance/ESR meets the requirements specified in Figure 18 through Figure 21. Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. 14 Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 APPLICATION INFORMATION (continued) IO LDO − VESR RESR + + VI RLOAD VO − CO Figure 22. LDO Output Stage With Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (VCout = Vout). This means no current is flowing into the Cout branch. If Iout suddenly increases (transient condition), the following occurs: • The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore, capacitor Cout provides the current for the new load condition (dashed arrow). Cout now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 22. • When Cout is conducting current to the load, initial voltage at the load is Vout = VCout – VESR. Due to the discharge of Cout, the output voltage Vout drops continuously until the response time t1 of the LDO is reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 23. The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs, where number 1 displays the lowest ESR and number 3 displays the highest ESR. • The higher the ESR, the larger the droop at the beginning of load transient. • The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. Conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Submit Documentation Feedback 15 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 APPLICATION INFORMATION (continued) Iout Vout 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to the Regulation of Vout at a Load Step From Low-to-High Output Current 16 Submit Documentation Feedback TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 APPLICATION INFORMATION (continued) Programming the TPS77401 Adjustable LDO Regulator The output voltage of the TPS77401 adjustable regulator is programmed using an external resistor divider as shown in Figure 24. The output voltage is calculated using: V O +V ref ǒ1 ) R1 Ǔ R2 (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower-value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using: R1 + ǒ Ǔ V V O *1 ref R2 (2) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS77401 VI 0.1 µF PG IN OUTPUT VOLTAGE PG Output 250 kΩ EN OUT VO R1 FB/SENSE GND CO R1 R2 UNIT 2.5 V 33.5 30.1 kΩ 3.3 V 53.8 30.1 kΩ 3.6 V 61.5 30.1 kΩ NOTE: To reduce noise and prevent oscillation, R1 and R2 need to be as close as possible to the FB/SENSE terminal. R2 Figure 24. TPS77401 Adjustable LDO Regulator Programming Regulator Protection The TPS77401 PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The device also features internal current limiting and thermal protection. During normal operation, the TPS77401 limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C (typ), regulator operation resumes. Submit Documentation Feedback 17 TPS77401-EP 250-mA LDO VOLTAGE REGULATOR WITH POWER-GOOD OUTPUT www.ti.com SLVS702 – OCTOBER 2006 APPLICATION INFORMATION (continued) Power Dissipation and Junction Temperature Specified regulator operation is ensured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined using the following equation: T max * T A P + J D(max) R qJA Where: TJmax = Maximum allowable junction temperature RθJA = Thermal resistance, junction to ambient, for the package, i.e., 266.2°C/W for the 8-terminal MSOP with no airflow TA = Ambient temperature The regulator dissipation is calculated using: P D ǒ + V *V I O Ǔ I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS77401MDGKREP ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06663-01XE ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TPS77401-EP : • Catalog: TPS77401 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS77401MDGKREP Package Package Pins Type Drawing MSOP DGK 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS77401MDGKREP MSOP DGK 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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