UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 BiCMOS ADVANCED PHASE-SHIFT PWM CONTROLLER Check for Samples: UCC2895-EP FEATURES 1 • • • • • • • • • • Programmable Output Turn-On Delay Adaptive Delay Set Bidirectional Oscillator Synchronization Capability for Voltage-Mode or Current-Mode Control Programmable Soft Start/Soft Stop and Chip Disable Via a Single Pin 0% to 100% Duty-Cycle Control 7-MHz Error Amplifier Operation to 1 MHz Low Active Current Consumption (5 mA Typ at 500 kHz) Very Low Current Consumption During Undervoltage Lock Out (150 μA Typ) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability DW PACKAGE (TOP VIEW) EAN EAOUT RAMP REF GND SYNC CT RT DELAB DELCD (1) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 EAP SS/DISB OUTA OUTB PGND VDD OUTC OUTD CS ADS Additional temperature ranges available - contact factory DESCRIPTION The UCC2895-EP is a phase-shift pulse-width modulation (PWM) controller that implements control of a full-bridge power stage by phase shifting the switching of one half bridge with respect to the other. It allows constant frequency PWM in conjunction with resonant zero-voltage switching to provide high efficiency at high frequencies. The device can be used either as a voltage-mode or current-mode controller. While the UCC2895-EP maintains the functionality of the UC2875/6/7/8 family, it improves on that controller family with additional features, such as enhanced control logic, adaptive delay set, and shutdown capability. Since the device is built in BCDMOS, it operates with dramatically less supply current than its bipolar counterparts. The UCC2895-EP can operate with a maximum clock frequency of 1 MHz. The M-temp UCC2895-EP device is offered in the 20-pin SOIC (DW) package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2009, Texas Instruments Incorporated UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com SIMPLIFIED APPLICATION DIAGRAM UCC3895 1 EAN 2 EAOUT 3 Q1 EAP 20 7 SS/DISB 19 RAMP OUTA 18 4 REF OUTB 17 5 GND PGND 16 6 SYNC VCC 15 7 CT OUTC 14 VOUT AC VIN VBIAS B 8 RT 9 10 OUTD 13 DELAB CS 12 DELCD ADS 11 D UDG−98139 ORDERING INFORMATION TA –55°C to 125°C (1) 2 PACKAGE SOIC – DW (1) ORDERABLE PART NUMBER UCC2895MDWREP TOP-SIDE MARKING UCC2895MEPG4 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 Table 1. PIN DESCRIPTION NAME ADS DESCRIPTION Adaptive delay set.This function sets the ratio between the maximum and minimum programmed output delay dead time. When ADS is connected directly to CS, no delay modulation occurs. Maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2 V (the peak current threshold). ADS changes the output voltage on the delay (DELAB and DELCD) pins by: VDEL + [0.75 (VCS * VADS)] ) 0.5 V where VCS and VADS are in volts. ADS must be limited to between 0 V and 2.5 V and must be less than, or equal to, CS. DELAB and DELCD also are clamped to a minimum of 0.5 V. CS Current sense. CS is the inverting input of the current-sense comparator, and the noninverting input of the overcurrent comparator and the ADS amplifier. The CS signal is used for cycle-by-cycle current limiting in peak current-mode control and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called soft stop, with full soft start. Oscillator timing capacitor (see Figure 3). The UCC2895-EP oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of 2.35 V. The approximate oscillator period is calculated by: tOSC + CT 5 RT 48 CT ) 120 ns where CT is in farads, RT is in ohms, and tOSC is in seconds. CT can range from 100 pF to 880 pF. Note that a large CT and a small RT combination results in extended fall times on the CT waveform. The increased fall time increases the SYNC pulse width, thus, limiting the maximum phase shift between OUTA/ OUTB and OUTC/ OUTD outputs, which limits the maximum duty cycle of the converter. Delay programming between complementary outputs. DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the external bridge. The UCC2895-EP allows the user to select the delay in which the resonant switching of the external power stages takes place. Separate delays are provided for the two half bridges to accommodate differences in resonant capacitor charging currents. The delay in each stage is set according to the formula: DELAB, DELCD tDELAY + (25 10*12) VDEL RDEL ) 25 ns where VDEL is in volts, RDEL is in ohms, and tDELAY is in seconds. DELAB and DELCD can source approximately 1 mA maximum. Delay resistors must be chosen so that this maximum is not exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For optimum performance, keep stray capacitance on these pins at <10 pF. EAN Error amplifier negative. Inverting input to the error amplifier. Keep below 3.6 V for proper operation. EAOUT Error amplifier output. EAOUT also is connected internally to the noninverting input of the PWM comparator and the no-load comparator. EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages when EAOUT falls below 500 mV and allows the outputs to turn on again when EAOUT rises above 600 mV. EAP Error amplifier positive. Noninverting input to the error amplifier. Keep below 3.6 V for proper operation. GND Ground. Chip ground for all circuits except the output stages. OUTA OUTB OUTC OUTD Outputs. These outputs are 100-mA complementary MOS drivers and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD drive the other half bridge and have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD, with respect to OUTA and OUTB, requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients PGND Output stage ground. To keep output switching noise from critical analog circuits, the UCC2895-EP has two different ground connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since PGND carries high current, board traces must be low impedance. RAMP Inverting input of PWM comparator. RAMP receives either the CT waveform in voltage and average current-mode controls, or the current signal (plus slope compensation) in peak current-mode control. An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead time. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 3 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com Table 1. PIN DESCRIPTION (continued) NAME DESCRIPTION Oscillator timing resistor (see Figure 3). The oscillator in the UCC2895-EP operates by charging an external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as: RT IRT (A) + 3 V RT (W) RT can range from 40 kΩ to 120 kΩ. Soft-start charging and discharging current also are programmed by IRT. REF 5 V ± 1.2% voltage reference. REF supplies power to internal circuitry, and also can supply up to 5 mA to external loads. The reference is shut down during undervoltage lockout, but is operational during all other disable modes. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor to ground. Do not use more than 1.0 μF. SS/DISB Soft start/disable. SS/DISB combines two independent functions: • Disable mode. A rapid shutdown of the chip is accomplished by any one of the following: externally forcing SS/DISB below 0.5 V, externally forcing REF below 4 V, VDD dropping below the UVLO threshold, or an overcurrent fault is sensed (CS = 2.5 V). In the case of REF pulled below 4 V or an UVLO condition, SS/DISB actively is pulled to ground via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB sinks a current of 10 × IRT until SS/DISB falls below 0.5 V. Note that, if SS/DISB is externally forced below 0.5 V, the pin starts to source current equal to IRT. Also note that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout. • Soft-start mode. After a fault or disable condition has passed and VDD is above the start threshold and/or SS/DISB falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin now sources current equal to IRT. A user-selected capacitor on SS/DISB determines the soft start and soft-start time. In addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB actively clamps the EAOUT voltage to approximately the SS/DISB voltage during both soft-start, soft-stop, and disable conditions. SYNC Synchronization (see Figure 3). SYNC is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator and acts as its clock signal. This bidirectional feature allows synchronization of multiple power supplies. SYNC also internally discharges the CT capacitor and any filter capacitors that are present on RAMP. The internal SYNC circuitry is level sensitive, with an input low threshold of 1.9 V and an input high threshold of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the synchronization pulse width. VDD Power supply. VDD must be bypassed with a minimum of a 1.0-μF low ESR, low ESL capacitor to ground. Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN Supply voltage IDD < 10 mA MAX UNIT 17 V Supply current 30 mA REF current 15 mA OUT current 100 mA Analog inputs EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB –0.3 REF + 0.3 Drive outputs OUTA, OUTB, OUTC, OUTD –0.3 to VCC + 0.3 Power dissipation (at TA = 25°C) N package 1 DW package V W 650 mW Tstg Storage temperature range –65 150 °C TJ Junction temperature range –55 150 °C 300 °C Lead temperature (1) (2) 4 Soldering, 10 s Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Currents are positive into and negative out of the specified terminal. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) MIN VDD Supply voltage (2) CVDD Supply voltage bypass capacitor CREF Reference bypass capacitor (3) CT Timing capacitor (for 500-KHz switching frequency) RT Timing resistor (for 500-KHz switching frequency) RDEL_AB RDEL_CD Delay resistor TJ (1) (2) (3) (4) NOM 10 Operating junction temperature MAX UNIT 16.5 V 10 x CREF µF 0.1 (4) 4.7 µF 200 pF 82 2.5 40 kΩ –55 125 °C It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a seperate ground plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located over this ground plane. Any connections associated with these pins to ground should be connected to this ground plane. The VDD capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor should belocated as physically close as possible to the VDD pins. The VREF capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired for the VREF then it should be located near the VREF capacitor and connected to the VREF pin with a resistor of 51 Ω or greater. The bulk capacitor on VDD must be a factor of 10 greater than the total VREF capacitance. It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. Electrical Characteristics VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs, TA = TJ, TA = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start threshold 10.2 11 11.8 V Stop threshold 8.2 9 9.8 V 1 2 3 V 150 250 μA 5 6 mA UVLO Hysteresis Supply Current Start-up current VDD = 8 V IDD active VCC clamp voltage IDD = 10 mA 16.5 17.5 18.5 TJ = 25°C 4.94 5 5.06 10 V < VDD < 17.5 V, 0 mA < IREF < 5 mA 4.85 5 5.15 10 20 V Voltage Reference Output voltage Short-circuit current REF = 0 V, TJ = 25°C V mA Error Amplifier Common-mode input voltage –0.1 3.6 V Offset voltage –7 7 mV Input bias current (EAP, EAN) –1 1 μA V EAOUT VOH EAP–EAN = 500 mV, IEAOUT = –0.5 mA 4 4.5 5 EAOUT VOL EAP–EAN = 500 mV, IEAOUT = 0.5 mA 0 0.2 0.4 EAOUT source current EAP–EAN = 500 mV, EAOUT = 2.5 V 1 1.5 mA EAOUT sink current EAP–EAN = –500 mV, EAOUT = 2.5 V 2.5 4.5 mA 75 85 dB 5 7 MHz 1.5 2.2 V/μs No-load comparator turn-off threshold 0.45 0.5 0.55 V No-load comparator turn-on threshold 0.55 0.6 0.69 V 0.035 0.1 0.165 V Open-loop DC gain Unity gain bandwidth (1) Slew rate EAN from 1 V to 0 V, EAP = 500 mV, EAOUT from 0.5 V to 3 V (1) No-load comparator hysteresis (1) V Specified by design. Not production tested. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 5 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com Electrical Characteristics (continued) VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs, TA = TJ, TA = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 473 500 527 kHz 2.5 5 % Oscillator Frequency TJ = 25°C Total variation Line, Temperature (1) SYNC VIH 2.05 2.1 2.32 V SYNC VIL 1.85 1.9 1.95 V 4.1 4.5 5 V 0 0.5 1 V 85 135 ns 2.9 3 3.1 V 2.25 2.35 2.55 V 0 0.2 0.65 V 0.72 0.85 1.05 V 0 0.85 1.50 % 70 120 ns SYNC VOH ISYNC = –400 μA, CT = 2.6 V SYNC VOL ISYNC = 100 μA, CT = 0 V SYNC output pulse width SYNC load = 3.9 kΩ and 30 pF in parallel RT voltage CT peak voltage CT valley voltage PWM Comparator EAOUT to RAMP/input offset voltage RAMP = 0 V, DELAB = DELCD = REF Minimum phase shift (OUTA to OUTC, OUTB to OUTD) RAMP = 0 V, EAOUT = 650 mV (2) RAMP to OUTC/OUTD delay RAMP from 0 V to 2.5 V, EAOUT = 1.2 V, DELAB = DELCD = REF (3) RAMP bias current RAMP < 5 V, CT < 2.2 V –5 RAMP sink current RAMP = 5 V, CT < 2.6 V 12 5 19 μA mA Current Sense 20 μA Peak current threshold 1.9 2 2.1 V Overcurrent threshold 2.4 2.5 2.6 V 75 110 ns –40 –35 –30 μA CS bias current CS to output delay 0 < CS< 2.5 V, 0 < ADS < 2.5 V –4.5 CS from 0 to 2.3 V, DELAB = DELCD = REF Soft Start/Shutdown Soft-start source current SS/DISB = 3 V, CS = 1.9 V Soft-start sink current SS/DISB = 3 V, CS = 2.6 V Soft-start/disable comparator threshold 325 350 375 μA 0.44 0.5 0.56 V 0.45 0.5 0.55 V Delay Set DELAB/DELCD output voltage ADS = CS = 0 V ADS = 0 V, CS = 2 V 1.9 2 2.1 V Output delay ADS = CS = 0 V (3) 450 525 600 ns ADS bias current 0 V < ADS < 2.5 V, 0 V < CS < 2.5 V 20 μA (2) (3) (4) 6 (4) –20 Minimum phase shift is defined as: t f(OUTA) * t f(OUTC) F + 200 tPERIOD or t f(OUTB) * t f(OUTD) F + 200 tPERIOD where: tf(OUTA) = falling edge of OUTA signal tf(OUTB) = falling edge of OUTB signal tf(OUTC) = falling edge of OUTC signal tf(OUTD) = falling edge of OUTD signal t(PERIOD) = period of OUTA or OUTB signal Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is shown in Figure 1 and Figure 2 , where: tf(OUTA) = falling edge of OUTA signal tr(OUTB) = rising edge of OUTB signal Specified by design. Not production tested. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 Electrical Characteristics (continued) VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 1 μF, No load at outputs, TA = TJ, TA = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output VOH (all outputs) IOUT = –10 mA, VDD to output 250 400 mV VOL (all outputs) IOUT = 10 mA 150 270 mV Rise time CLOAD = 100 pF (5) 20 35 ns Fall time CLOAD = 100 pF (5) 20 35 ns (5) Specified by design. Not production tested. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 7 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com tPERIOD OUTA(1) OUTA(1) tDELAY = tf(OUTA) – tr(OUTB) tDELAY = tf(OUTA) – tf(OUTC) OUTB(2) OUTC(2) (1) Also applies to OUTB (2) Also applies to OUTD Figure 1. OUTA/OUTC Output Delay 8 (1) Also applies to OUTC (2) Also applies to OUTD Figure 2. OUTA/OUTB Output Delay Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 APPLICATION INFORMATION Programming DELAB, DELCD, and Adaptive Delay Set (ADS) The UCC2895-EP allows the user to set the delay between switch commands within each leg of the full-bridge power circuit, according to the formula from the data sheet: t DELAY + (25 10 *12) V DEL R DEL ) 25 ns For this equation, VDEL is determined in conjunction with the desire to utilize (or not utilize) the ADS feature from: V DEL + [0.75 (V CS * V ADS)] ) 0.5 V Figure 3 shows the resistors needed to program the delay periods and the ADS function. UCC2895−EP 9 DELAB 10 DELCD CS 12 ADS 11 RDELAB RDELCD Figure 3. Resistors Needed in Programming The ADS allows the user to vary the delay times between switch commands within each of the converter’s two legs. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive divider from CS to GND to set VADS. From the previous equation for VDEL, if ADS is tied to GND, VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this condition, the maximum value of VDEL is 2 V. If ADS is connected to a resistive divider between CS and GND, the term (VCS – VDS) becomes smaller, reducing the level of VDEL. This decreases the amount of delay modulation. In the limit of ADS tied to CS, VDEL = 0.5 V and no delay modulation occurs. In the case with maximum delay modulation (ADS = GND) when the circuit goes from light load to heavy load, the variation of VDEL is from 0.5 V to 2 V. This causes the delay times to vary by a 4:1 ratio as the load is changed. The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of the current flowing in the primary winding of the transformer, and can change by a factor of 10:1 or more as circuit loading changes. Reference [1] delves into the many interrelated factors for choosing the optimum delay times for the most efficient power conversion and illustrates an external circuit to enable ADS using the UC2879. Implementing this adaptive feature is simplified in the UCC2895-EP controller, giving the user the ability to tailor the delay times to suit a particular application, with a minimum of external parts. [1] L. Balogh, "Design Review: 100W, 400 kHz, DC/DC Converter With Current Doubler Synchronous Rectification Achieves 92% Efficiency," Unitrode Power Supply Design Seminar Manual, Unitrode Corporation, 1996, Topic 2. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 9 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com A = VADS/VCS RDELAY = 10 kW A = 1.0 DELAY TIME (ns) 500 400 A = 0.8 300 A = 0.6 200 100 A = 0.4 A = 0.2 A = 0.1 0 0.5 1 1.5 2.0 2.5 CURRENT SENSE VOLTAGE (V) Figure 4. Resistors Needed for Programming CLOCK RAMP AND COMP PWM SIGNAL OUTPUT A OUTPUT B OUTPUT C OUTPUT D UDG−98138 Figure 5. UCC2895-EP Timing (No Output Delay Shown) 10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 IRT RT Q 8 CT 7 Q R SYNC RAMP 3 EAN R Q DELAY B D S Q DELAY C OUTA 9 DELAB 17 OUTB + ERROR AMP 20 + 1 + CURRENT−SENSE COMPARATOR 14 NO−LOAD COMPARATOR R Q DELAY D + 12 2.5 V IRT + HI = ON 10 DELCD 13 OUTD 16 PGND 11 ADS 4 REF 5 GND ADAPTIVE DELAY SET AMPLIFIER + REF OUTC 0.5 V / 0.6 V OVERCURRENT COMPARATOR SS 18 DELAY A 2 2V CS D S Q VDD + EAP Q 6 0.8 V EAOUT 15 D S Q OSC 8(IRT ) Q S Q R + 11 V/9 V DISABLE COMPARATOR 0.5 V + 19 HI = ON 0.5 V UVLO COMPARATOR REF REFERENCE OK COMPARATOR + 4V 10(IRT ) UDG−98140 Figure 6. Block Diagram Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 11 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com CIRCUIT DESCRIPTION REF 8IRT RT RT VREF IRT CT 2.5 V S CLOCK Q + CT + 0.2 V R SYNC CLOCK UDG−98141 Figure 7. Oscillator Block Diagram REF 0.5 V 100 kΩ 75 kΩ TO DELAY A AND DELAY B BLOCKS + CS DELAB + 100 kΩ ADS 75 kΩ REF + TO DELAY C AND DELAY D BLOCKS DELCD UDG−98142 Figure 8. ADS Block Diagram 12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP UCC2895-EP www.ti.com SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 CIRCUIT DESCRIPTION (continued) BUSED CURRENT FROM ADS CIRCUIT VREF 3.5 V DELAB/CD FROM PAD DELAYED CLOCK SIGNAL 2.5 V CLOCK UDG−98143 Figure 9. Delay Block Diagram (One Delay Block Per Output) Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP 13 UCC2895-EP SCBS809F – DECEMBER 2005 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS Vcs = 0 V Vcs = 2 V GAIN (dB) 2000 200 80 160 1400 1200 1000 800 60 120 40 80 20 40 600 400 PHASE MARGIN (DEGREES) 1600 GAIN (dB) OUTPUT DELAY (ns) 1800 PHASE MARGIN (5C) 100 200 0 10 0 20 30 0 40 0 1 RDEL (kW) 100 1000000 FREQUENCY (Hz) Figure 10. Delay Programming (Characterizes Output Delay Between A/B, C/D) Figure 11. Error Amplifier Gain/Phase Margin 1 RT = 47 K RT = 62 k RT = 82 k RT = 100 k 1600 0.95 FREQUENCY (kHz) EAOUT TO RAMP OFFSET (V) 10000 0.9 0.85 1400 1200 1000 800 600 400 200 0.8 −60 −40 −20 0 20 40 60 80 100 0 120 100 TEMPERATURE (5C) Figure 12. EAOUT to RAMP Offset Over Temperature VDD = 10 V VDD = 12 V 1000 CT (pF) VDD = 15 V Figure 13. Frequency vs RT/CT (Oscillator Frequency) VDD = 10 V VDD = 17 V VDD = 12 V VDD = 15 V VDD = 17 V 13 9 12 11 IDD (mA) IDD (mA) 8 7 6 10 9 8 7 6 5 5 4 4 0 400 800 1200 1600 0 400 OSCILLATOR FREQUENCY (kHz) Figure 14. IDD vs VDD/Oscillator Frequency (No Output Loading) 14 800 1200 1600 OSCILLATOR FREQUENCY (kHz) Figure 15. IDD vs VDD/Oscillator Frequency (With 0.1-nf Output Loads) Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): UCC2895-EP PACKAGE OPTION ADDENDUM www.ti.com 26-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC2895MDWREP ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06614-01XE ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF UCC2895-EP : UCC2895 • Catalog: • Automotive: UCC2895-Q1 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC2895MDWREP Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.1 2.65 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2895MDWREP SOIC DW 20 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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