REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish on last page. - CFS 05-12-07 Thomas M. Hess B Make change to VC pin description as specified under figure 2. Update boilerplate paragraphs to current requirements. - ro 11-09-07 Charles F. Saffle CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY TOM HESS 04-11-19 TITLE MICROCIRCUIT, DIGITAL-LINEAR, PHASE SHIFT RESONANT CONTROLLER, MONOLITHIC SILICON APPROVED BY RAYMOND MONNIN SIZE A REV AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CODE IDENT. NO. DWG NO. V62/04752 16236 B PAGE 1 OF 16 5962-V066-11 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance phase shift resonant controller microcircuit, with an operating temperature range of -25C to +110C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04752 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function UC2875-EP Phase shift resonant controller 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 28 JEDEC PUB 95 Package style MS-013 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 2 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage ( VC,VIN ) ........................................................................................... 20 V Output current (sink or source), IO DC ....................................................................... 0.50 A Pulse (0.5 s) ........................................................... 3 A Analog I/O voltage ...................................................................................................... -0.3 V to 5.3 V Power dissipation (PD) ............................................................................................... 1.488 W Operating junction temperature range (TJ) ................................................................ Storage temperature range (TSTG) .............................................................................. Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds ............... Thermal resistance, junction to ambient (JC): X package ............................................................................................................ Thermal resistance, junction to ambient (JA): X package ............................................................................................................ -55C to +150C -65C to +150C +300C 20.6C/W (high K board) 45.5C/W (high K board) 1.4 Recommended operating conditions. 3/ Supply voltage range ( VC,VIN ) ................................................................................. 12 V Operating free-air temperature range ( TA ) ............................................................... -25C to +110C 1/ 2/ 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Undervoltage lockout (UVLO) section. Start threshold -25C to +110C 01 11.75 V UVLO hysteresis -25C to +110C 01 2 V -25C to +110C 01 600 A -25C to +110C 01 100 A Supply current, IIN -25C to +110C 01 44 mA Supply current, IC -25C to +110C 01 30 mA TJ = +25C 01 5.08 V 0.5 Supply current section. Supply current, IIN startup VIN = 8 V, VC = 20 V, Supply current, IC startup VIN = 8 V, VC = 20 V, RSLOPE open, IDELAY = 0 RSLOPE open, IDELAY = 0 Voltage reference section. Output voltage 4.92 Line regulation voltage VLN VIN = 11 V to 20 V -25C to +110C 01 10 mV Load regulation voltage VLD IVREF = -10 mA -25C to +110C 01 20 mV Total variation Line, load, temperature -25C to +110C 01 5.1 V Noise voltage 10 Hz to 10 kHz -25C to +110C 01 50 typical Vrms Long term stability 1000 hours TJ = +125C 01 2.5 typical mV Short circuit current VREF = 0 V TJ = +25C 01 60 typical mA Offset voltage -25C to +110C 01 15 mV Input bias current -25C to +110C 01 3 A 4.9 Error Amplifier section. Open loop voltage gain AVOL VE/AOUT = 1 V to 4 V -25C to +110C 01 60 dB Common mode rejection ratio CMRR VCM = 1.5 V to 5.5 V -25C to +110C 01 75 dB See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Error Amplifier section – continued. Power supply rejection ratio PSRR VIN = 11 V to 20 V -25C to +110C 01 85 dB Output sink current VE/AOUT = 1 V -25C to +110C 01 1 mA Output source current VE/AOUT = 4 V -25C to +110C 01 -0.5 mA High level output voltage VOH IE/AOUT = -0.5 mA -25C to +110C 01 4 5 V Low level output voltage VOL IE/AOUT = 1 mA -25C to +110C 01 0 1 V Unity gain bandwidth UGBW -25C to +110C 01 7 MHz -25C to +110C 01 6 V/sec 1.3 typical Slew rate Pulse Width Modulator (PWM) comparator section. Ramp offset voltage 3/ TJ = +25C 01 Zero phase shift voltage 4/ -25C to +110C 01 0.55 VE/AOUT (Ramp peak + Ramp offset) -25C to +110C 01 98 102 0 2 PWM phase shift 5/ VE/AOUT Zero phase shift voltage Output skew 5/ Ramp to output delay V V % VE/AOUT 1 V -25C to +110C 01 ±20 ns 6/ -25C to +110C 01 125 ns TJ = +25C 01 1.15 MHz 2 % 1.20 MHz Oscillator section. Initial accuracy Voltage stability VIN = 11 V to 20 V -25C to +110C 01 Total variation Line, temperature -25C to +110C 01 0.85 0.80 See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Oscillator section – continued. Sync pin threshold TJ = +25C 01 3.8 typical V Clock out peak TJ = +25C 01 4.3 typical V Clock out low TJ = +25C 01 3.3 typical V Clock out pulse width RCLOCKSYNC = 3.9 k -25C to +110C 01 Maximum frequency RFREQSET = 5 k -25C to +110C 01 -25C to +110C 01 -25C to +110C 01 -25C to +110C 01 RFREQSET = 100 k -25C to +110C 01 4.1 V VCS+ = 3 V -25C to +110C 01 5 A Threshold voltage -25C to +110C 01 2.6 V Delay to output -25C to +110C 01 150 ns -3 A 100 2 ns MHz Ramp generator/slope compensation section. Minimum ramp current ISLOPE = 10 A, -14 A VFREQSET = VREF Maximum ramp current ISLOPE = 1 mA, -0.8 mA VFREQSET = VREF Ramp valley Ramp peak – clamping level 0 typical V Current limit section. Input bias current IIB 2.4 Soft start/reset delay section. Charge current VSOFTSTART = 0.5 V -25C to +110C 01 -20 Discharge current VSOFTSTART = 1 V -25C to +110C 01 120 A Restart threshold -25C to +110C 01 4.3 V Discharge level -25C to +110C 01 300 typical mV See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Output drivers section. Output low level 01 -25C to +110C IOUT = 50 mA 0.4 2.6 IOUT = 500 mA Output high level V 01 -25C to +110C IOUT = -50 mA 2.5 V 2.6 IOUT = -500 mA Delay set section. Delay set voltage IDELAY = -500 A Delay time IDELAY = -250 A 7/ 8/ -25C to +110C 01 2.3 2.6 V -25C to +110C 01 150 600 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VC = VIN = 12 V, RFREQSET = 12 k, CFREQSET = 330 pF, RSLOPE = 12 k, CRAMP = 200 pF, CDELAYSET A-B = CDELAYSET C-D = 0.01 F, IDELAYSET A-B = IDELAYSET C-D = -500 A, and TA = TJ. 3/ Ramp offset voltage has a temperature coefficient of about 0.4 mV/C. 4/ Zero phase shift voltage has a temperature coefficient of about 0.2 mV/C. 5/ Phase shift percentage (0% = 0, 100% = 180) is defined as = 200/T %, where is the phase shift, and and T are defined in figure 4. At 0% phase shift, is the output skew. 6/ Ramp delay to output time is defined in NO TAG. 7/ Delay time is defined as delay = T (1/2 – (duty cycle)), where T is defined in figure 4. 8/ Delay time can be programmed via resistors from the delay set pins to ground. -12 Delay time (62.5 x 10 ) / IDELAY sec where IDELAY = delay set voltage / RDELAY. The recommended range for IDELAY is 25 A IDELAY 1 mA. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 8 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 9 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.104 --- 2.65 A1 0.004 0.012 0.10 0.30 b 0.012 0.020 0.31 0.51 c 0.008 0.013 0.20 0.33 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 E1 0.393 0.419 9.97 10.63 e L n 0.050 BSC 0.016 1.27 BSC 0.050 0.40 28 1.27 28 NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MS-013 variation AE. 3. All linear dimensions are shown in inches (millimeters). Millimeter equivalents are given for general information only. 4. Body dimensions do not include mold protrusion not to exceed 0.006 inch (0.15 millimeters). FIGURE 1. Case outline - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 VREF 2 E/AOUT 3 EA- 4 EA+ 5 CS+ 6 SOFTSTART 7 GND 8 GND 9 GND 10 DELAYSET C-D 11 NC 12 OUTD 13 OUTC 14 VC 15 VIN 16 PWRGND 17 OUTB 18 OUTA 19 NC 20 GND 21 GND 22 GND 23 DELAYSET A-B 24 FREQSET 25 CLOCKSYNC 26 SLOPE 27 RAMP 28 GND FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 11 Pin Description CLOCKSYNC Bi-directional clock and synchronization pin. Used as an output, this pin provides a clock signal. As an input, this pin provides a synchronization point. In its simplest useage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator. This pin may also used to synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width. E/AOUT Error amplifier output. This is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0 phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. CS+ Current sense. The non-inverting input to the current fault comparator whose reference is set internally to a fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V the current fault latch is set, the outputs are forced OFF and a SOFT-START cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled from switching and held in a low state until the CS+ pin is brought below 2.5 V. The outputs may begin switching at 0 degrees phase shift before the SOFTSTART pin begins to rise – this condition will not prematurely deliver power to the load. FREQSET Oscillator frequency set pin. A resistor and a capacitor from FREQSET to GND will set the oscillator frequency. DELAYSET A-B, DELAYSET C-D Output delay control. The user programmed current flowing from these pins to GND set the turn-on delay for the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents. EA- Error amplifier inverting input. This is normally connected to the voltage divider resistors which sense the power supply output voltage level. EA+ Error amplifier non-inverting input. This is normally connected to a reference voltage used for comparison with the sensed power supply output voltage level at he EA+ pin. GND Signal ground. All voltages are measured with respect to GND. The timing capacitor, on the FREQSET pin, any bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin. OUTA – OUTD Outputs A-D. The outputs are 2 A totem pole drivers optimized for both MOSFET gates and level shifting transformers. The outputs operate as pairs with a nominal 50% duty cycle. The A-B pair is intended to drive one half-bridge in the external power stage and is synchronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs. PWRGND Power ground. VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a signal point to optimize noise rejection and minimize DC drops. FIGURE 2. Terminal connections – Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 12 Pin Description RAMP Voltage ramp. This pin is the input to the PWM comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope: dV/dT = (Sense Voltage / (RSLOPE x CRAMP )). Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin provides slope compensation. Because of the 1.3 V offset between the ramp input and the PWM comparator, the error amplifier output voltage can not exceed the effective ramp peak voltage and duty cycle clamping is easily achievable with appropriate values of RSLOPE and CRAMP. SLOPE Set ramp slope / slope compensation. A resistor from this pin to VCC will set the current used to generate the ramp. Connecting this resistor to the DC input line voltage will provide voltage feed-forward. SOFTSTART VC VIN Soft start. SOFTSTART will remain at GND as long as VIN is below the UVLO threshold. SOFTSTART will be pulled up to a about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current fault (CS+ voltage exceeding 2.5 V), SOFTSTART will be pulled to GND and then ramp to 4.8 V. If a fault occurs during the SOFTSTART cycle, the outputs will be immediately disabled and SOFTSTART must charge fully prior to resetting the fault latch. For paralleled controllers, the SOFTSTART pins may be paralleled to a single capacitor, but the charge currents will be additive. Output switch supply voltage. This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWRGND pin with low equivalent series resistance (ESR), low equivalent series inductance (ESL) capacitors. Primary chip supply voltage. This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should be bypassed directly to the GND pin with low ESR, low ESL capacitors. NOTE: When VIN exceeds the UVLO threshold the supply current (IIN) will jump from about 100 µA to a current in excess of 20 µA. If the device is not connected to a well bypassed supply, it may immediately enter UVLO again. This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. VREF VREF is disabled while VIN is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR, low ESL, capacitor to the GND pin. FIGURE 2. Terminal connections – Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 13 FIGURE 3. Logic diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 14 NOTES: Phase shift, output skew, and delay time definitions. Duty cycle = t/T. Period = T. TDHL(A to C) = TDHL(B to D) = . FIGURE 4. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 15 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code V62/04752-01XE 01295 Package 2/ SOP - DW Tape and reel Vendor part number Top side marking UC2875SDWREP UC2875SEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/04752 PAGE 16