UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver Check for Samples: UCC27531 , UCC27533, UCC27536 , UCC27537, UCC27538 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • • • • • • • • • Low Cost Gate Driver (offering optimal solution for driving FET and IGBTs) Superior Replacement to Discrete Transistor Pair Drive (providing easy interface with controller) TTL and CMOS Compatible Input Logic Threshold, (independent of supply voltage) Split Output Options Allow for Tuning of TurnOn and Turn-Off Currents Inverting and Non-Inverting Input Configurations Enable with Fixed TTL Compatible Threshold High 2.5-A Source and 2.5-A or 5-A Sink Peak Drive Currents at 18-V VDD Wide VDD Range From 10 V up to 35 V Input and Enable Pins Capable of Withstanding up to -5-V DC Below Ground Output Held Low When Inputs are Floating or During VDD UVLO Fast Propagation Delays (17-ns typical) Fast Rise and Fall Times (15-ns and 7-ns typical with 1800-pF Load) Under Voltage Lockout (UVLO) Used as a High-Side or Low-Side Driver (if designed with proper bias and signal isolation) Low Cost, Space Saving 5-Pin or 6-Pin DBV (SOT-23) Package Options UCC27536 and UCC27537 Pin-to-Pin compatible to TPS2828 and TPS2829 Operating Temperature Range of -40°C to 140°C Switch-Mode Power Supplies DC-to-DC Converters Solar Inverters, Motor Control, UPS HEV and EV Chargers Home Appliances Renewable Energy Power Conversion SiC FET Converters DESCRIPTION The UCC2753x family of devices are single-channel, high-speed, gate drivers capable of effectively driving MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turn-on effect. The UCC2753x device can also feature a split-output configuration where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This pin arrangement allows the user to apply independent turn-on and turn-off resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates. The driver has rail-to-rail drive capability and extremely small propagation delay typically 17 ns. The input threshold of UCC2753xDBV is based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of VDD supply voltage. The 1-V typical hysteresis offers excellent noise immunity. The driver has EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN, IN+, IN1, and IN2 pins. UCC2753x (top view) UCC27531 UCC27533 EN 1 6 OUTH VDD 1 IN 2 5 OUTL GND 2 VDD 3 4 GND IN+ 3 UCC27536 5 OUT 4 IN- EN 1 GND 2 IN- 3 UCC27537 5 VDD EN 1 5 VDD VDD 1 6 OUTH 2 IN1 2 5 IN2 IN+ 3 4 OUT GND 3 4 OUTL GND 4 OUT UCC27538 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION(CONT.) Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the application diagram, timing diagram and input and output logic truth table. Internal circuitry on VDD pin provides an under voltage lockout function that holds output low until VDD supply voltage is within operating range. The UCC2753x driver is offered in a 5-pin or 6-pin standard SOT-23 (DBV) package. The device operates over wide temperature range of -40°C to 140°C. ORDERING INFORMATION (1) (1) (2) PART NUMBER PACKAGE (2) PEAK CURRENT (SOURCE AND SINK) UCC27531DBV SOT-23, 6-PIN 2.5 A and 5 A UCC27533DBV SOT-23, 5-PIN 2.5-A/5-A UCC27536DBV SOT-23, 5-PIN 2.5-A/2.5-A UCC27537DBV SOT-23, 5-PIN 2.5-A/5-A UCC27538DBV SOT-23, 6-PIN 2.5-A/5-A INPUT THRESHOLD LOGIC OPERATING TEMPERATURE RANGE TA TTL/CMOS –Compatible (low-voltage, independent of VDD bias voltage) -40°C to +140°C DBV package uses Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. For the most up-to-date packaging information see the TI web site. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage range, VDD -0.3 35 Continuous OUTH, OUTL, OUT -0.3 VDD +0.3 Pulse OUTH, OUTL, OUT (200 ns) -2 VDD +0.3 -5 27 -6.5 27 Continuous IN, EN, IN+, IN-, IN1, IN2 Pulse IN, EN, IN+, IN-, IN1, IN2 (1.5 µs) Human body model, HBM (ESD) 1000 Operating virtual junction temperature range, TJ -40 150 Storage temperature range, Tstg -65 150 (1) (2) (3) 2 V 4000 Charged device model, CDM (ESD) Lead temperature V Soldering, 10 sec. 300 Reflow 260 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages. These devices are sensitive to electrostatic discharge; follow proper device handling procedures. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 THERMAL INFORMATION THERMAL METRIC UCC27533, UCC27536, UCC27537 UCC27531, UCC27538 DBV DBV (1) 5 PINS 6 PINS θJA Junction-to-ambient thermal resistance (2) 178.3 178.3 θJCtop Junction-to-case (top) thermal resistance (3) 109.7 109.7 (4) θJB Junction-to-board thermal resistance 28.3 28.3 ψJT Junction-to-top characterization parameter (5) 14.7 14.7 ψJB Junction-to-board characterization parameter (6) 27.8 27.8 (1) (2) (3) (4) (5) (6) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage range, VDD TYP 10 MAX UNIT 32 V -40 140 °C Input voltage, IN, IN+, IN-, IN1, IN2 -5 25 Enable, EN -5 25 Operating junction temperature range Copyright © 2012–2013, Texas Instruments Incorporated 18 V Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 3 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition specifications are at 25°C. PARAMETER TEST CONDITION MIN TYP MAX UNITS Bias Currents IDDoff Startup current (UCC25731) IDDoff Startup current (UCC27533) IDDoff Startup current (UCC27536) IDDoff Startup current (UCC27537) IDDoff Startup Current (UCC27538) VDD = 7.0, IN, EN=VDD 100 200 300 IN, EN = GND 100 217 300 VDD = 7.0, IN+ = GND, IN- = VDD 100 200 300 IN+ = VDD, IN- = GND 100 217 300 VDD = 7.0, IN- = GND, EN = VDD 100 217 300 IN- = VDD, EN = GND 100 217 300 VDD =7.0, IN+, EN = VDD 100 200 300 IN+, EN = GND 100 217 300 VDD = 7.0, IN1, IN2=VDD 100 200 300 IN1, IN2=GND 100 200 300 μA Under Voltage Lockout (UVLO) VON Supply start threshold 8.0 8.9 9.8 VOFF Minimum operating voltage after supply start 7.3 8.2 9.1 VDD_H Supply voltage hysteresis V 0.7 Input (IN, IN+, IN1, IN2) VIN_H Input signal high threshold, output high Output High, IN- = LOW, EN=HIGH, IN2 or IN1 = HIGH (other is INPUT) 1.8 2.0 2.2 VIN_L Input signal low threshold, output low Output Low, IN- = LOW, EN=HIGH, IN2 or IN1 = HIGH (other is INPUT) 0.8 1.0 1.2 VIN_HYS Input signal hysteresis V 1.0 Input (IN-) VIN_H Input signal high threshold, output low Output low, IN+ = HIGH, EN = High 1.7 1.9 2.1 VIN_L Input signal low threshold, output high Output high,, IN+ = HIGH, EN = High 0.8 1.0 1.2 VIN_HYS Input signal hysteresis V 0.9 Enable (EN) VEN_H Enable signal high threshold Output High 1.7 1.9 2.1 VEN_L Enable signal low threshold Output Low 0.8 1.0 1.2 VEN_HYS Enable signal hysteresis 4 Submit Documentation Feedback V 0.9 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition specifications are at 25°C. PARAMETER TEST CONDITION MIN TYP MAX UNITS Outputs (OUTH/OUTL) ISRC/SNK Source peak current (OUTH)/ sink peak current (OUTL)(13) CLOAD = 0.22 µF, f = 1 kHz VOH OUTH, high voltage IOUTH = -10 mA VOL OUTL, low voltage VOL OUTL, Low Voltage UCC27536 ROH OUTH, pull-up resistance (15) ROL OUTL, pull-down resistance ROL OUTL, pull-down resistance UCC27536 -2.5/+5 A VDD 0.12 VDD 0.07 IOUTL = 100 mA 0.065 0.125 IOUTL = 100 mA 0.130 0.23 12 12.5 TA = 25°C, IOUT = -10 mA TA = -40°C to 140°C, IOUT = -10 mA VDD -0.2 11 7 12 20 0.45 0.65 0.85 TA = -40°C to 140°C, IOUT = 100 mA 0.3 0.65 1.25 TA = 25°C, IOUT = 100 mA 0.9 1.3 1.7 TA = -40°C to 140°C, IOUT = 100 mA 0.6 1.3 2.3 TA = 25°C, IOUT = 100 mA V Ω Switching Time tR Rise time CLOAD = 1.8 nF tF Fall time CLOAD = 1.8 nF tF Fall Time UCC27536DBV CLOAD = 1.8 nF 10 tD1 Turn-on propagation delay CLOAD = 1.8 nF, IN, IN+ = 0 V to 5 V 17 26 tD2 Turn-off propagation delay CLOAD = 1.8 nF, IN, IN+ = 5 V to 0 V 17 26 tD3 Inverting turn-off propagation delay CLOAD = 1.8 nF, IN- = 0 V to 5 V 17 28 tD4 Inverting turn-on propagation delay CLOAD = 1.8 nF, IN- = 5 V to 0 V 20 28 Copyright © 2012–2013, Texas Instruments Incorporated 15 7 Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 ns 5 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Timing Diagram Figure 1. UCC27531: (OUTPUT = OUTH tied to OUTL) INPUT = IN, (EN = VDD), or INPUT = EN, (IN = VDD) UCC27537: (OUTPUT = OUT) INPUT = IN+, (EN = VDD), or INPUT = EN, (IN+ = VDD) UCC27538: (OUTPUT = OUTH tied to OUTL) INPUT = IN1, (IN2 = VDD), or INPUT = IN2, (IN1 = VDD) High INPUT (IN+ pin) Low High IN- pin Low 90% OUTPUT 10% tD1 t r tD2 tf Figure 2. UCC27533: (OUTPUT = OUT) INPUT = IN+ UCC27536: (OUTPUT = OUT) INPUT = EN High INPUT (IN- pin) Low High Enable pin Low 90% OUTPUT 10% tD2 tf tD2 tr Figure 3. UCC27533: (OUTPUT = OUT) ENABLE = IN+ UCC27536: (OUTPUT = OUT) ENABLE = EN 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION Block Diagram IN VDD 2 VREF EN 1 3 VDD 6 OUTH 5 OUTL VDD GND 4 UVLO Figure 4. UCC27531 (EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, in pull-down resistance to GND = 230 kΩ) IN+ VDD 3 VREF IN- 4 1 VDD 5 OUT VDD GND 2 UVLO Figure 5. UCC27533 (IN- pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ pull-down resistance to GND = 230 kΩ) EN VDD 1 VREF 5 VDD 4 OUT VREF IN- 3 VDD GND 2 UVLO Figure 6. UCC27536 (EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN- pull-up resistance to VREF = 500 kΩ) Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 7 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 EN www.ti.com VDD 1 5 VDD 4 OUT VREF IN+ 3 VDD UVLO GND 2 Figure 7. UCC27537 (EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ pull-down resistance to GND = 230 kΩ) IN1 IN2 VDD 2 5 1 VDD 6 OUTH 4 OUTL VDD UVLO GND 3 Figure 8. UCC27538 (IN1 pull-down resistance to GND = 230 kΩ, IN2 pull-down resistance to GND = 230 kΩ) 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION Typical Application Diagrams UCC27531 EN OUTH 1 6 IN OUTL + 2 5 VDD GND 3 + – 4 GND Bouncing Up to -6.5 V 18 V ISENSE Controller VCE(sense) VCC + – Figure 9. Driving IGBT Without Negative Bias UCC27531 EN OUTH 1 IN 6 OUTL + 2 5 3 4 VDD + – GND 18 V + – 13 V Figure 10. Driving IGBT With 13-V Negative Turn-Off Bias Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 9 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com UCC27533 IN4 OUT 5 IN+ + 3 VDD GND 1 + – 2 18 V + – 13 V Figure 11. Single Output Driver E/2 + – Isol. UCC2753x Isol. UCC2753x Controller Isol. UCC2753x Isol. UCC2753x E/2 + – Figure 12. Using UCC2753x Drivers in an Inverter 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION UCC2753x Product Matrix Table 1. UCC2753x Product Matrix UCC27531 UCC27533 UCC27536 UCC27537 UCC27538 2.5 A ION PEAK 2.5 A 2.5 A 2.5 A 2.5 A IOFF PEAK 5A 5A 2.5 A 5A 5A PACKAGE SOT-23-6 SOT-23-5 SOT-23-5 SOT-23-5 SOT-23-6 IN Single Dual Single Single Dual IN LOGIC TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS EN Yes No Yes Yes No OUTPUT Split Single Single Single Split INVERTING No Inverting/NonInverting Yes No No MAX VDD 35 V 35 V 35 V 35 V 35 V UCC27531 UCC27533 EN 1 6 OUTH VDD 1 IN 2 5 OUTL GND 2 VDD 3 4 GND PIN OUT Copyright © 2012–2013, Texas Instruments Incorporated IN+ 3 UCC27536 5 OUT 4 IN- EN 1 GND 2 IN- 3 UCC27537 5 VDD EN 1 2 IN+ 3 GND 4 OUT UCC27538 5 VDD VDD 1 6 OUTH IN1 2 5 IN2 4 OUT GND 3 4 OUTL Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 11 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O FUNCTION EN I Enable (Pull EN to GND in order to disable output, pull it high or leave open to enable output) 2 IN I Driver non-inverting input 3 VDD I Bias supply input 4 GND - Ground (all signals are referenced to this node) 5 OUTL O 5-A sink current output of driver 6 OUTH O 2.5-A Source Current Output of driver PIN NUMBER NAME UCC27531DBV 1 UCC27533DBV 1 VDD I Bias supply input 2 GND - Ground (All signals are referenced to this node) 3 IN+ I Driver non-inverting input 4 IN- I Driver inverting input 5 OUT O 2.5-A source and 5-A sink current output of driver 1 EN I Enable (pull EN to GND in order to disable output, pull it high or leave open to enable output) 2 GND - Ground (all signals are referenced to this node) 3 IN- I Driver inverting input 4 OUT O 2.5-A source and 2.5-A sink current output of driver 5 VDD I Bias supply input 1 EN I Enable (Pull EN to GND in order to disable Output, Pull it high or leave open to enable Output) 2 GND - Ground (All signals are referenced to this node) 3 IN+ I Driver non-inverting input 4 OUT O 2.5-A source and 5-A sink current output of driver 5 VDD I Bias supply input VDD I Bias supply input UCC27536DBV UCC27537DBV UCC27538DBV 1 12 2 IN1 I Driver non-inverting input 3 GND - Ground (all signals are referenced to this node) 4 OUTL O 5-A sink current output of driver 5 IN2 I Driver non-inverting input 6 OUTH O 2.5-A source current output of driver Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 INPUT/OUTPUT LOGIC TRUTH TABLE (for single output driver) UCC27531DBV IN PIN EN PIN OUTH PIN OUTL PIN OUT (OUTH and OUTL pins tied together) L L High-impedance L L L L H High-impedance L H L High-impedance L L H H H High-impedance H H FLOAT H High-impedance H FLOAT H High-impedance L L INPUT/OUTPUT LOGIC TRUTH TABLE UCC27533DBV IN+ PIN IN- PIN OUT PIN L L L L H L H L H H H L FLOAT X L X FLOAT L IN- PIN EN PIN OUT PIN L L L L H H H L L L UCC27536DBV H H FLOAT X L L FLOAT H IN+ PIN EN PIN OUT PIN L L L L UCC27537DBV L H H L L H H H FLOAT X L FLOAT H H INPUT/OUTPUT LOGIC TRUTH TABLE (for single output driver) UCC27538DBV IN2 PIN OUTH PIN OUTL PIN OUT (OUTH and OUTL pins tied together) L L High-Impedance L L L H High-Impedance L L H L High-Impedance L L H H H High-Impedance H X FLOAT High-Impedance L L FLOAT X High-Impedance L L IN1 PIN Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 13 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS If not specified, INPUT refers to non-inverting input 12 25 10 Fall Time (ns) Rise Time (ns) 20 15 10 8 6 4 Cload = 1.8nF Cload = 1.8nF 2 5 0 10 20 30 Supply Voltage (V) 0 40 20 30 Supply Voltage (V) Figure 13. Rise Time vs. Supply Voltage 40 C002 Figure 14. Fall Time vs. Supply Voltage Input To Output Propagation Delay (ns) 20 16 Fall Time UCC27536 (ns) 10 C001 12 8 Cload = 1.8nF 21 TurnOn TurnOff 19 17 15 0 4 10 20 30 Supply Voltage (V) 40 C003 0 0 10 20 30 40 Supply Voltage (V) C001 Figure 15. UCC27536 Fall Time vs. Supply Voltage 14 Submit Documentation Feedback Figure 16. Propagation Delay vs. Supply Voltage Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 30 OUT RISING, IN- 5V to 0V OUT FALLING, IN- 0V to 5V 25 VDD = 10V VDD = 18V VDD = 32V 25 23 Supply Current (mA) IN- Input To Output Propagation Delay (ns) 27 21 19 20 15 10 17 5 15 0 Cload = 1.8nF 0 10 20 30 40 0 100 200 Supply Voltage (V) 300 400 500 Frequency (kHz) C001 C001 Figure 17. IN- Propagation Delay vs. Supply Figure 18. Operating Supply Current vs. Frequency 300 IN- = VDD, IN+ = GND EN=IN=Vdd IN+ = VDD, IN- = GND EN=IN=GND 250 250 Startup Current (µA) UCC27533 Startup Current (µA) 300 200 150 200 150 Vdd = 7V Vdd = 7V 100 -50 0 50 100 150 Temperature (Ü& 100 C002 -50 0 50 100 150 7HPSHUDWXUH Û& C005 Figure 19. UCC27533 Start-Up Current vs. Temperature Copyright © 2012–2013, Texas Instruments Incorporated Figure 20. UCC27531 Start-Up Current vs. Temperature Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 15 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 300 IN- = GND, EN = VDD IN1 = IN2 = VDD IN- = VDD, EN = GND IN1 = IN2 = GND 250 UCC27538 Startup Current (µA) UCC27536 Startup Current (µA) 300 200 Vdd = 7V 150 100 250 200 Vdd = 7V 150 100 -50 0 50 100 150 -50 0 Temperature (Ü& 50 100 150 Temperature (Ü& C004 C005 Figure 21. UCC27536 Start-Up Current vs. Temperature Figure 22. UCC27538 Start-Up Current vs. Temperature 4.5 300 IN+ = EN = Vdd 4.3 4.1 Idd (mA) UCC27537 Startup Current (µA) IN+ = EN = GND 250 200 3.9 150 Vdd = 7V 3.7 Vdd = 18V Cload = 1.8nF fsw = 100kHz 100 -50 0 50 100 150 Temperature (Ü& 3.5 C003 -50 0 50 100 150 7HPSHUDWXUH Û& C006 Figure 23. UCC27537 Start-Up Current vs. Temperature 16 Submit Documentation Feedback Figure 24. Operating Supply Current vs. Temperature (output switching) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 2.4 9.6 Turn-On UVLO Rising UVLO Falling 2 Input Threshold (V) 9.2 Vdd UVLO Threshold (V) Turn-Off 2.2 8.8 1.8 1.6 1.4 1.2 8.4 1 8 0.8 -50 0 50 100 -50 150 0 50 7HPSHUDWXUH Û& 100 C007 C008 Figure 25. UVLO Threshold Voltage vs. Temperature Figure 26. Input Threshold vs. Temperature 2.4 2.4 Enable OUT FALL 2.2 OUT RISE Disable 2.2 2 2 1.8 Enable Threshold (V) IN- Input Threshold (V) 150 7HPSHUDWXUH Û& 1.6 1.4 1.2 1.8 1.6 1.4 1.2 1 1 0.8 -50 0 50 100 150 Temperature (Ü& C002 0.8 -50 0 50 100 150 7HPSHUDWXUH Û& C009 Figure 27. IN- Input Threshold vs. Temperature Copyright © 2012–2013, Texas Instruments Incorporated Figure 28. Enable Threshold vs. Temperature Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 17 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 1.2 25 ROH ROL Output Pull-Down Resistance (Ÿ) Output Pull-Up Resistance (Ÿ) 1 20 15 10 0.8 0.6 0.4 Vdd = 18V Vdd = 18V 5 0.2 -50 0 50 100 -50 150 0 7HPSHUDWXUH Û& 50 100 C010 Figure 29. Output Pull-Up Resistance vs. Temperature C011 Figure 30. Output Pull-Down Resistance vs. Temperature 0.6 30 IN=HIGH Turn-On IN=LOW Turn-Off 0.5 25 Propagation Delay (ns) Operating Supply Current (mA) 150 7HPSHUDWXUH Û& 0.4 0.3 20 15 Vdd = 18V Vdd = 18V 0.2 10 -50 0 50 100 150 7HPSHUDWXUH Û& -50 0 50 100 C012 Figure 31. Operating Supply Current vs. Temperature (output in DC on/off condition) 18 Submit Documentation Feedback 150 7HPSHUDWXUH Û& C013 Figure 32. Input-to-Output Propagation Delay vs. Temperature Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 16 30 OUT RISING, IN- 5V to 0V OUT FALLING, IN- 0V to 5V 15 22 Rise Time (ns) IN- Propagation Delay (ns) 26 18 14 13 Vdd = 18V Cload = 1.8nF Vdd = 18V 14 12 10 -50 0 50 100 150 Temperature (Ü& 11 C003 -50 0 50 100 150 7HPSHUDWXUH Û& C014 Figure 33. IN- Input-to-Output Propagation Delay vs. Temperature Figure 34. Rise Time vs. Temperature 9 20 15 Fall Time UCC27536 (ns) Fall Time (ns) 8 7 6 Vdd = 18V Cload = 1.8nF 10 Vdd = 18V Cload = 1.8nF 5 5 0 -50 0 50 100 150 Temperature (Ü& 4 -50 0 50 100 C003 150 7HPSHUDWXUH Û& C015 Figure 35. Fall Time vs. Temperature Copyright © 2012–2013, Texas Instruments Incorporated Figure 36. UCC27536 Fall Time vs. Temperature Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 19 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 10 140 8 120 Rise Time (ns) Supply Current (mA) If not specified, INPUT refers to non-inverting input 6 4 100 80 Cload = 10nF fsw = 20kHz 2 60 Cload = 10nF 0 40 0 10 20 30 40 0 10 Supply Voltage (V) 20 30 C016 C017 Figure 37. Operating Supply Current vs. Supply Voltage (output switching) Figure 38. Rise Time vs. Supply Voltage 120 60 100 Fall Time UCC27536 (ns) 70 50 Fall Time (ns) 40 Supply Voltage (V) 40 80 60 Cload = 10nF 30 40 20 20 Cload = 10nF 0 10 20 30 40 Supply Voltage (V) 10 0 10 20 30 C002 40 Supply Voltage (V) C018 Figure 39. Fall Time vs. Supply Voltage 20 Submit Documentation Feedback Figure 40. UCC27536 Fall Time vs. Supply Voltage Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 APPLICATION INFORMATION High-current gate driver devices are required in switching power applications for a variety of reasons. In order to enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive the gates of the switching devices. The situation will be often encountered since the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the logic-level signal to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar, (or p- n-channel MOSFET), transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate for this since they lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses into itself. The UCC2753x is very flexible in this role with a strong current drive capability and wide supply voltage range up to 32 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and -5-V (relative to Source) SiC FET applications, 15-V and -15-V(relative to Emitter) IGBT applications and many others. As a singlechannel driver, the UCC2753x can be used as a low-side or high-side driver. To use as a low-side driver, the switch ground is usually the system ground so it can be connected directly to the gate driver. To use as a highside driver with a floating return node however, signal isolation is needed from the controller as well as an isolated bias to the UCC2753x. Alternatively, in a high-side drive configuration the UCC2753x can be tied directly to the controller signal and biased with a non-isolated supply. However, in this configuration the outputs of the UCC2753x need to drive a pulse transformer which then drives the power-switch to work properly with the floating source and emitter of the power switch. Further, having the ability to control turn-on and turn-off speeds independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining system reliability. These requirements coupled with the need for low propagation delays and availability in compact, lowinductance packages with good thermal capability makes gate driver devices such as the UCC2753x extremely important components in switching power combining benefits of high-performance, low cost, component count and board space reduction and simplified system design. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 21 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Table 2. UCC2753x Features and Benefits FEATURE BENEFIT High source and sink current capability, 2.5 A and 5 A (asymmetrical). High current capability offers flexibility in employing UCC2753x device to drive a variety of power switching devices at varying speeds. Low 17 ns (typ) propagation delay. Extremely low pulse transmission distortion. Wide VDD operating range of 10 V to 32 V. Flexibility in system design. Can be used in split-rail systems such as driving IGBTs with both positive and negative(relative to Emitter) supplies. Optimal for many SiC FETs. VDD UVLO protection. Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at power-up and power-down. High UVLO of 8.9V typical ensures that power switch is not on in high-impedance state which could result in high power dissipation or even failures. Outputs held low when input pin (INx) in floating condition. Safety feature, especially useful in passing abnormal condition tests during safety certification Split output structure option (OUTH, OUTL). Allows independent optimization of turn-on and turn-off speeds using series gate resistors. Strong sink current (5 A) and low pull-down impedance (0.65 Ω). High immunity to high dV/dt Miller turn-on events. CMOS and TTL compatible input threshold logic with wide hysteresis. Enhanced noise immunity, while retaining compatibility with microcontroller logic level input signals (3.3 V, 5 V) optimized for digital power. Input capable of withstanding -6.5 V. Enhanced signal reliability in noisy environments that experience ground bounce on the gate driver. VDD Under Voltage Lockout The UCC2753x device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si MOSFETs, IGBTs, and emerging SiC FETs. VDD Threshold VDD IN OUT Figure 41. Power Up 22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 Input Stage The input pins of UCC2753x device are based on a TTL and CMOS compatible input threshold logic that is independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold voltage levels which eases system design considerations and guarantees stable operation across temperature. The very low input capacitance , typically 20 pF, on these pins reduces loading and increases switching speed. The device features an important safety function wherein, whenever the input pin is in a floating condition, the output is held in the low state. This is achieved using pull-up or pull-down resistors on the input pins as shown in the block diagrams. The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be exercised whenever the driver is used with slowly varying input signals, especially in situations where the device is located in a separate daughter board or PCB layout has long input connection traces: • High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since the device features just one GND pin which may be referenced to the power ground, this may interfere with the differential voltage between Input pins and GND and trigger an unintended change of output state. Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which increases power dissipation and poses risk of damage • 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers. If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate charge related power dissipation in the gate driver device package and transferring it into the external resistor itself. Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable pins, caution must be used in the following applications: • Input or Enable pins are switching to amplitude > 15 V • Input or Enable pins are switched at dV/dt > 2 V/ns If both of these conditions occur, it is advised to add a series 150-Ω resistor for the pin(s) being switched to limit the current through the input structure. Enable Function The Enable (EN) pin of the UCC2753x has an internal pull-up resistor to an internal reference voltage so leaving Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also be driven by low-voltage logic to enable and disable the driver. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 23 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Output Stage The output stage of the UCC2753x device is illustrated in Figure 42. The UCC2753x device features a unique architecture on the output stage which delivers the highest peak source current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pull-up structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak sourcing current enabling fast turn on. VDD R OH R NMOS, Pull Up OUTH Input Signal Anti Shoot Through Circuitry Narrow Pulse at each Turn On OUTL R OL Figure 42. UCC27531 Gate Driver Output Stage Split output depicted in Figure 42. For devices with single OUT pin, OUTH and OUTL are connected internally and then connected to OUT. The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of the P-Channel device only, since the N-Channel device is turned-on only during output change of state from low to high. Thus the effective resistance of the hybrid pull-up stage is much lower than what is represented by ROH parameter. The pull-down structure is composed of a N-Channel MOSFET only. The ROL parameter (see ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true impedance of the pull-down stage in the device. In UCC2753x, the effective resistance of the hybrid pull-up structure is approximately 3 x ROL. 24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 The UCC2753x is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability results in a very low pull-down impedance in the driver output stage which boosts immunity against the parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches . An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application, the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current charging the CGD Miller capacitance during this high dV/dt is shunted by the pull-down stage of the driver. If the pull-down impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can result in spurious turn on. This phenomenon is illustrated in Figure 43. VDS VIN Miller Turn -On Spike in V GS C GD Gate Driver RG COSS ISNK ROL CGS VTH VGS of MOSFET ON OFF VIN VDS of MOSFET Figure 43. Low Pull-Down Impedance in UCC2753x (output stage mitigates Miller turn-on effect) The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode clamps may be eliminated. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 25 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Power Dissipation Power dissipation of the gate driver has two portions as shown in equation below: PDISS = PDC + PSW (1) The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections etc and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shootthrough). The UCC2753x features very low quiescent currents (less than 1 mA) and contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible. In practice this is the power consumed by driver when its output is disconnected from the gate of power switch. The power dissipated in the gate driver package during switching (PSW) depends on the following factors: • Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage VDD due to low VOH drop-out) • Switching frequency • Use of external gate resistors When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: 1 EG = CLOAD VDD2 2 where • CLOAD is load capacitor and VDD is bias voltage feeding the driver. (2) There is an equal amount of energy dissipated when the capacitor is discharged. During turn off the energy stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given by the following: PG = CLOAD VDD2 fsw where • ƒSW is the switching frequency (3) The switching load presented by a power FET and IGBT can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence, Qg = CLOADVDD, to provide the following equation for power: PG = CLOAD VDD2 fsw = Qg VDD fsw (4) This power PG is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the driver and MOSFET and IGBT, this power is completely dissipated inside the driver package. With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated as follows: æ ö ROFF RON PSW = 0.5 ´ Qg ´ VDD ´ fsw ç + ÷ ç (ROFF + RGATE ) (RON + RGATE ) ÷ è ø where • 26 ROFF = ROL and RON (effective resistance of pull-up structure) = 3 x ROL Submit Documentation Feedback (5) Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the package. In order for a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package is summarized in the ‘Thermal Information’ section of the datasheet. For detailed information regarding the thermal information table, please refer to Application Note from Texas Instruments entitled “IC Package Thermal Metrics” (SPRA953A). PCB Layout Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device operation and design robustness. The UCC2753x gate driver incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even higher (2.5-A and 5-A peak current is at VDD = 18 V). Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers. • Locate the driver device as close as possible to power device in order to minimize the length of high-current traces between the driver Output pins and the gate of the power switch device. • Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD during turn-on of power switch. The use of low inductance SMD components such as chip resistors and chip capacitors is highly recommended. • The turn-on and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established in these loops at two instances – during turn-on and turn-off transients, which induces significant voltage transients on the output pins of the driver device and gate of the power switch. • Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux cancellation • Separate power traces and signal traces, such as output and input signals. • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM controller etc at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 27 UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (December 2012) to Revision A • Page Changed Block Diagram. ...................................................................................................................................................... 7 Changes from Revision A (December 2012) to Revision B • Page Added UCC27533, UCC27536, UCC27537 and UCC27538 parts to the datasheet. .......................................................... 1 Changes from Revision B (April 2013) to Revision C • Page Added additional DESCRIPTION information. ...................................................................................................................... 1 Changes from Revision C (April, 2013) to Revision D Page • Added Startup Current UCC27537 Bias Current Parameters to the ELECTRICAL CHARACTERISTICS. ......................... 4 • Added UCC27531 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 15 • Added UCC27537 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 16 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UCC27531DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7531 UCC27531DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7531 UCC27533DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7533 UCC27533DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7533 UCC27536DBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7536 UCC27536DBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7536 UCC27537DBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7537 UCC27537DBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7537 UCC27538DBVR PREVIEW SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7538 UCC27538DBVT PREVIEW SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 140 7538 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 3-May-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. 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