ESMT M24D16161ZA

ESMT
M24D16161ZA
Revision History :
Revision 1.0 (Jul. 06, 2007)
- Original
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
1/15
ESMT
PSRAM
M24D16161ZA
16-Mbit (1M x 16)
Pseudo Static RAM
Features
Features
•Wide voltage range: 1.7V–1.95V
•Access Time: 70 ns
•Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
•Ultra low standby power
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Deep Sleep Mode
•Available in Lead-Free 48-ball BGA Package
•Operating Temperature: –40°C to +85°C
Functional Description[1]
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled ( BHE , BLE HIGH), or during a
write operation ( CE LOW and WE LOW).
To write to the device, take Chip Enable ( CE LOW) and
Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is
LOW, then data from I/O pins (I/O0 through I/O7), is written
into the location specified on the address pins (A0 through
A19).
If Byte High Enable ( BHE ) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).To read from the device, take
Chip Enables ( CE LOW) and Output Enable ( OE ) LOW
while forcing the Write Enable ( WE ) HIGH. If Byte Low
The M24D16161ZA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
Enable ( BLE ) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0through I/O15) are placed in a
Deep Sleep Mode is enabled by driving ZZ LOW. See the
Truth Table for a complete description of Read, Write, and
Deep Sleep mode.
high-impedance state when: deselected ( CE HIGH), outputs
Byte High Enable ( BHE ) is LOW, then data from memory will
appear on I/O8 to I/O15. Refer to the truth table for a complete
description of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
2/15
ESMT
M24D16161ZA
Pin Configuration[2, 3]
48-ball VFBGA
Top View
Product Portfolio
VCC Range (V)
Product
M24D16161ZA
Min.
1.7
Typ.
1.8
Speed(ns)
Max.
1.95
70
Low-Power Modes
At power-up, all four sections of the die are activated and the
PSRAM enters into its default state of full memory size and
refresh space. This device provides four different Low-Power
Modes.
1.Reduced Memory Size Operation
2.Partial Array Refresh
3.Deep Sleep Mode
4.Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16 Mb PSRAM can be operated as a
12-Mbit,8-Mbit or a 4-Mbit memory block. Please refer to
“Variable Address Space Register (VAR)” on page4 for the
protocol to turn on/off sections of the memory. The device
remains in RMS mode until changes to the Variable Address
Space register are made to revert back to a complete 16-Mbit
PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in the Stand-by mode (with ZZ
tied low) to reduce standby current. In this mode the PSRAM
will only refresh certain portions of the memory in the
Power Dissipation
Operating ICC(mA)
Standby ISB2(µA)
f = 1MHz
f = fMAX
Typ.[4]
Max.
Typ.[4]
Max.
Typ. [4]
Max.
3
5
18
20
55
70
Stand-By Mode, as configured by the user through the
settings in the Variable Address Register.
Once ZZ returns high in this mode, the PSRAM goes back
too perating in full address refresh. Please refer to “Variable
Address Space Register (VAR)” on page4 for the protocol to
turn off sections of the memory in Stand-By mode. If the VAR
register is not updated after the power up, the PSRAM will be
in its default state. In the default state the whole memory
array will be refreshed in the Stand-By Mode. The 16-Mbit is
divided into four 4-Mbit sections allowing certain sections to
be active (i.e., refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving ZZ
LOW. The device stays in the deep sleep mode until ZZ is
driven HIGH.
Notes:
2.Ball H6, E3 can be used to upgrade to 32M and 64M density respectively.
3.NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = VCC(typ.),
TA = 25°C. Tested initially and after any design changes that may affect the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
3/15
ESMT
M24D16161ZA
Variable Address Mode Register (VAR) Update[5, 6]
Deep Sleep Mode—Entry/Exit [7]
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter
Description
tZZWE
ZZ LOW to Write Start
tCDR
Chip deselect to ZZ LOW
Operation Recovery Time (Deep Sleep Mode only)
Deep Sleep Mode Time
tR[7]
tZZMIN
Min.
Max.
Unit
1
µs
0
ns
200
8
µs
µs
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6.All other timing parameters are as shown in the data sheets.
7.tR applies only in the deep sleep mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
4/15
ESMT
M24D16161ZA
Variable Address Space Register (VAR)
Variable Address Space—Address Patterns
Partial Array Refresh Mode (A3 = 0, A4 = 1)
A2
0
0
0
1
1
1
A1,A0
1 1
1 0
0 1
1 1
1 0
0 1
Refresh Section
Address
Size
Density
th
00000h-3FFFFh (A19 = A18 = 0)
256K x 16
4M
th
00000h-7FFFFh (A19 = 0)
512K x 16
8M
th
00000h-BFFFFh (A19:A18 not equal to 1 1)
768K x 16
12M
th
C0000h-FFFFFh (A19 = A18= 1)
256K x 16
4M
th
80000h-FFFFFh (A19 = 1)
512K x 16
8M
th
40000h-FFFFFh (A19:A18 not equal to 0 0)
768K x 16
12M
1/4 of the array
1/2 of the array
3/4 of the array
1/4 of the array
1/2 of the array
3/4 of the array
Reduced Memory Size Mode (A3 = 1, A4 = 1)
0
0
1 1
1 0
th
00000h-3FFFFh (A19 = A18 = 0)
256K x 16
4M
th
00000h-7FFFFh (A19 = 0)
512K x 16
8M
th
1/4 of the array
1/2 of the array
0
0 1
3/4 of the array
00000h-BFFFFh (A19:A18 not equal to 1 1)
768K x 16
12M
0
0 0
Full array
00000h-FFFFFh (Default)
1M x 16
16M
th
1
1 1
1/4 of the array
C0000h-FFFFFh (A19 = A18 = 1)
256K x 16
4M
1
1 0
1/2th of the array
80000h-FFFFFh (A19 = 1)
512K x 16
8M
th
1
0 1
3/4 of the array
40000h-FFFFFh (A19:A18 not equal to 0 0)
768K x 16
12M
1
0 0
Full array
00000h-FFFFFh (Default)
1M x 16
16M
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
5/15
ESMT
M24D16161ZA
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select ( CE ) should be HIGH for at least 200 µs after VCC has
reached a stable value. No access must be attempted during
this period of 200 µs. The state of ZZ has to be high (H) for
the duration of power-up.
Parameter
Description
Min.
Tpu
Chip Enable Low After Stable VCC
200
Elite Semiconductor Memory Technology Inc.
Typ.
Max.
Unit
µs
Publication Date : Jul. 2007
Revision : 1.0
6/15
ESMT
M24D16161ZA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential.–0.2V to VCCMAX + 0.3V
DC Voltage Applied to Outputs
in High Z State[8, 9, 10]......................–0.2V to VCCMAX + 0.3V
DC Input Voltage[8, 9, 10]..................–0.2V to VCCMAX + 0.3V
Output Current into Outputs (LOW).............................20 mA
Operating Range
Range
Operating
Temperature (TA)
VCC
Industrial
−40°C to +85°C
1.7V to 1.95V
DC Electrical Characteristics (Over the Operating Range) [8, 9, 10]
Parameter
VCC
Description
-70
Test Conditions
Min.
1.7
Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
IOH = −0.1 mA
VCC =1.7V to 1.95V
IOL = 0.1 mA
VCC =1.7V to 1.95V
1.7V ≤ VCC ≤ 1.95
VIL
Input LOW Voltage
IIX
Typ.[4]
1.8
Unit
Max.
1.95
V
VCC-0.2
V
0.2
V
0.8* VCC
VCC +0.3
V
VCC= 1.7V to 1.95V
-0.2
0.2* VCC
V
Input Leakage Current
GND ≤ VIN ≤ VCC
-1
+1
µA
IOZ
Output Leakage Current
GND ≤ VOUT ≤ VCC
-1
+1
µA
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
18
20
mA
f = 1 MHz
3
5
mA
CE > VCC−0.2V,
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMAX (Address and Data Only),
55
70
µA
55
70
µA
10
µA
ISB1
Automatic CE
Power-Down Current
—CMOS Inputs
VCC = VCCmax
IOUT = 0mA
CMOS levels
f = 0 ( OE , WE , BHE and BLE ),
VCC = 1.95V, ZZ ≥ VCC – 0.2V
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
CE ≥ VCC−0.2V,
VIN ≥ VCC − 0.2V or VIN ≤ 0.2V,
f = 0, VCC = VCCMAX
ZZ ≥ VCC – 0.2V
VCC = VCCMAX , ZZ ≤ 0.2V,
IZZ
Deep Sleep Current
CE = HIGH or BHE and BLE =
HIGH
Capacitance[11]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
Unit
8
pF
8
pF
Notes:
8.VIL(MIN) = –0.5V for pulse durations less than 20 ns.
9.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
10.Overshoot and undershoot specifications are characterized and are not 100% tested.
11.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
7/15
ESMT
M24D16161ZA
Thermal Resistance[11]
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance(Junction to Ambient)
56
°C/W
ΘJC
Thermal Resistance (Junction to Case)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
11
°C/W
AC Test Loads and Waveforms
Parameters
1.8V (VCC)
Unit
R1
14000
Ω
R2
14000
Ω
RTH
7000
Ω
VTH
0.9
V
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
8/15
ESMT
M24D16161ZA
Switching Characteristics Over the Operating Range [12, 13, 14, 15, 18]
Parameter
Read Cycle
tRC[17]
tCD
tAA
tOHA
tACE
Description
Read Cycle Time
Chip Deselect Time CE , BLE / BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
-70
Unit
Min.
Max.
70
15
40000
ns
ns
70
CE LOW to Data Valid
70
ns
ns
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z [13, 14, 16]
tHZOE
OE HIGH to High Z [13, 14, 16]
tLZCE
CE LOW Low Z [13, 14, 16]
tHZCE
CE HIGH to High Z [13, 14, 16]
25
ns
tDBE
BLE / BHE LOW to Data Valid
70
ns
tLZBE
BLE / BHE LOW to Low Z[13, 14, 16]
tHZBE
BLE / BHE HIGH to High Z[13, 14, 16]
Write Cycle[15]
tWC
tSCE
Write Cycle Time
CE LOW to Write End
10
ns
5
25
ns
10
ns
5
70
60
ns
25
ns
40000
ns
ns
WE Pulse Width
15
60
0
0
ns
ns
ns
ns
BLE / BHE LOW to Write End
50
ns
tSD
Data Set-Up to Write End
60
ns
tHD
Data Hold from Write End
25
ns
tHZWE
WE LOW to High-Z[13, 14, 16]
0
tLZWE
WE HIGH to Low-Z[13, 14, 16]
10
tAW
tHA
tSA
tPWE
Chip Deselect Time CE , BLE / BHE High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
tBW
25
ns
ns
Notes:
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and
Waveforms” section.
13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (1.8V).
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
16. High-Z and Low-Z parameters are characterized and are not 100% tested.
17. If invalid address signals shorter than min. tRC are continuously repeated for 40 µs, the device needs a normal read timing
(tRC) or needs to enter standby state at least once in every 40 µs.
18. In order to achieve 70 ns performance, the read access must be CE controlled. That is, the addresses must be stable prior
to CE going active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
9/15
ESMT
M24D16161ZA
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21]
Read Cycle 2 ( OE Controlled)[19, 21]
Notes:
19.Whenever CE , BHE / BLE are taken inactive, they must remain inactive for a minimum of 15 ns.
20.Device is continuously selected. OE , CE = VIL.
21. WE is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
10/15
ESMT
M24D16161ZA
Switching Waveforms (continued)
Write Cycle 1 ( WE Controlled) [15, 16, 19, 22, 23]
Notes:
22.Data I/O is high-impedance if OE ≥ VIH.
23.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
11/15
ESMT
M24D16161ZA
Write Cycle 2 ( CE Controlled) [15, 16, 19, 22, 23]
Write Cycle 3 ( WE Controlled, OE LOW)[ 19, 23]
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
12/15
ESMT
M24D16161ZA
Switching Waveforms (continued)
Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[15, 19, 22, 23]
Truth Table[24, 25]
ZZ
H
H
H
H
CE
H
X
L
L
WE
X
X
X
H
OE
X
X
X
L
BHE
X
H
H
L
BLE
X
H
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
H
H
L
L
L
H
H
H
H
H
H
L
H
L
L
L
H
Inputs/Outputs
High Z
High Z
High Z
Data Out (I/O0-I/O15)
Data Out (I/O0-I/O7);
I/O8-I/O15 In High Z
Data Out (I/O8-I/O15);
I/O0-I/O7 In High Z
High Z
High Z
High Z
H
L
L
X
L
L
Data In (I/O0-I/O15)
H
L
L
X
H
L
H
L
L
X
L
H
L
H
X
X
H
H
L
H
X
X
X
X
Data In (I/O0-I/O7);
I/O8-I/O15 In High Z
Data In (I/O8-I/O15);
I/O0-I/O7 In High Z
Mode
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Read
Active (ICC)
Read
Active (ICC)
Output Disabled
Output Disabled
Output Disabled
Write (Upper Byte and Lower
Byte
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Write (Lower Byte Only)
Active (ICC)
Write (Upper Byte Only)
Active (ICC)
Data In (A0-A4)
Write (Variable Address
Mode Register)
Active (ICC)
High Z
Deep Power-down/PAR
Deep Sleep
(IZZ)/Stand by
Notes:
24.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
25.During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
13/15
ESMT
M24D16161ZA
Ordering Information
Speed (ns)
70
Ordering Code
M24D16161ZA-70BIG
Package Type
48-ball Fine Pitch VFBGA (6 mm × 8 mm × 1 mm) Lead-Free
Operating Range
Industrial
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
14/15
ESMT
M24D16161ZA
Important Notice
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any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
15/15