TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 High-Efficiency 6-Channel WLED Driver Supporting Single-Cell Li-Ion Battery Input Check for Samples: TPS61176 FEATURES DESCRIPTION • • • • • • • • • The TPS61176 is a highly integrated multi-channel WLED backlight driver for tablet or notebook PCs, which can support single-cell battery input directly. It comprises a high efficient boost converter with an integrated 2A/40V power MOSFET and six current sink regulators. In total, the device can drive up to 60 WLEDs with high current matching performance. In addition, the boost automatically adjusts its output voltage to the WLED forward voltage to improve efficiency. 1 • • • • • • • • • • • 2.7V to 6.5V VIN Voltage Range 2.7V to 24V Boost Input Voltage Range Integrated 2A/40V MOSFET 1MHz Switching Frequency Adaptive Boost Output to WLED Voltages Six Current Sinks of 35mA Capability Each ±2% (Max) Current Accuracy 1.3% (Typ) Current Matching Wide PWM Dimming Frequency Range – from 100Hz to 22kHz Mixed Dimming Mode: Automatic Switch between Analog Dimming and PWM Dimming – Programmable Switch Point: 25% / 12.5% – Programmable PWM Dimming Mode: 22kHz PWM Dimming / Direct PWM Dimming Up to 14-bit Dimming Resolution Support down to 1% Dimming Duty Cycle Input PWM Glitch Filter Up to 90% Efficiency Driver for Input / Output Isolation PFET for True Shutdown Built-in Soft Start Built-in WLED Open / Short Protection Thermal Shutdown Support 4.7µH Inductor 16L 3 mm x 3 mm QFN package APPLICATIONS • • • Tablet Backlight Notebook Backlight Backlight for Small and Media Form Factor LCD Display with Single-Cell or Multi-Cell Battery Input TPS61176 adopts mixed dimming mode. The automatic switch between PWM dimming at low dimming duty cycle and analog dimming at high dimming duty cycle increases the overall electrical-tooptical efficiency, reducing the power budget for backlight remarkably. The switch point can be programmed to 12.5% or 25% and the PWM dimming mode can be programmed to fixed frequency dimming or direct PWM dimming. TPS61176 supports up to 14-bit dimming resolution, which avoids potential flickering perception during the low brightness dimming. By providing a driver for an external isolation Pchannel MOSFET, TPS61176 can support true shutdown. When the IC is disabled or the boost output is short to ground, the isolation PFET can be turned off to cut off the power path from battery to the WLEDs, preventing any leakage current from the battery. TPS61176 also integrates soft start, WLED open and short protection and thermal shut down. TPS61176 is in a 16 pin 3mm x 3mm QFN package, providing a space-saving and high-performance WLED driver solution. TYPICAL APPLICATION L1 4.7uH 2.7V ~ 6.5V Up to 38V D1 VIN C1 2.2uF SW R2 1.3M MODE / FAULT PGND C2 4.7uF R3 1M OVP R4 43k VIN TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF PWM IFB5 IFB6 PWM / EN ISET R1 51k COMP GND C4 0.47uF 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) ORDERING PACKAGE PACKAGE MARKING TPS61176RTE 16-pin 3x3 QFN - RTE PZJI (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE MIN Voltage range (2) ESD rating UNIT MAX VIN, PWM/EN, MODE/FAULT –0.3 7 V SW –0.3 40 V IFB1 to IFB6 –0.3 20 V All other pins –0.3 3.6 V HBM 4 kV MM 200 V 2 kV CDM See Thermal Information Table Continuous power dissipation Operating junction temperature range –40 150 °C Storage temperature range –65 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION THERMAL METRIC (1) TPS61176 RTE (16 PINS) θJA Junction-to-ambient thermal resistance (2) θJCtop Junction-to-case (top) thermal resistance (3) 44.4 θJB Junction-to-board thermal resistance (4) 14.4 ψJT Junction-to-top characterization parameter (5) 0.6 ψJB Junction-to-board characterization parameter (6) 14.3 θJCbot Junction-to-case (bottom) thermal resistance (7) 3.3 (1) (2) (3) (4) (5) (6) (7) 2 UNITS 43 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT Bias voltage to IC (Application as Figure 18) 2.7 6.5 V Input voltage to inductor (Application as Figure 18) 2.7 24 V VOUT Output voltage range Vin 38 V L Inductor 4.7 6.8 10 µH CI Input capacitor 1.0 2.2 CO Output capacitor 2.2 4.7 CCOMP COMP capacitor FPWM_I TA TJ VIN µF 10 µF 0.47 1 µF Input PWM signal frequency range 0.1 22 KHz Operating ambient temperature –40 85 °C Operating junction temperature –40 125 °C ELECTRICAL CHARACTERISTICS VIN = 3.6V, PWM/EN=high, IFB current=20mA, IFB voltage=450mV, TA = -40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VIN Input voltage range VIN_UVLO VIN under voltage lockout threshold VIN_HYS VIN under voltage lockout hysteresis Iq_VIN Operating quiescent current into VIN ISD Shutdown current VLDO VLDO pin output voltage 2.7 VIN ramp down VIN ramp up 6.5 2.4 2.5 2.65 2.7 250 Device enable, switching 1 MHz and no load 3 1 4 PWM/EN = low, TA = 25°C 1 2 3.3 3.5 3 V mV PWM/EN = low VIN = 3.6 V V mA µA V PWM/EN VH PWM/EN Logic high VL PWM/EN Logic Low RPD PWM/EN pin internal pull-down resistor tSD PWM/EN logic low width to shutdown 1.2 V 0.4 400 PWM/EN from high to low 800 1600 20 V kΩ ms CURRENT REGULATION VISET ISET pin voltage PWM/EN logic high KISET Current multiplier IISET = 20 μA IFBx Current accuracy Km (Imax – Imin) / (2 x IAVG) IIFBx_leak IFBx pin leakage current IIFBx_max Current sink max output current IISET = 35 μA, each pin TFBx_MINON Current sink minimum on time IISET = 20 μA, each pin fdim PWM dimming frequency Mode 1 / Mode 3, 0°C to 70°C IISET = 20 μA, 0°C to 70°C IISET = 20 µA, –40°C to 85°C 1.02 1.04 1.06 V 1024 –2% 2% –2.3% IISET = 20 μA 2.3% 0.65% VIFBx = 10 V, each pin 1.5 5 VIFBx = 5 V, each pin 0.5 2 35 mA 0.5 20 µA 22 µs 27 kHz BOOST OUTPUT REGULATION VIFBx_min IFBx regulation voltage Measured on VIFB(min), IISET = 20 μA 450 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 mV 3 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6V, PWM/EN=high, IFB current=20mA, IFB voltage=450mV, TA = -40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 0.4 Ω 2 µA POWER SWITCH RDS(on) Switch MOSFET on-resistance VIN = 3.6 V ILEAK_SW Switch MOSFET leakage current VSW = 40 V OSCILLATOR fSW Oscillator frequency Dmax Maximum boost switch duty cycle 0.8 1 1.2 93 MHz % MODE / FAULT VMODE MODE/FAULT pin voltage during mode detection period Tested as VIN - VMODE when mode resistor is connected between VIN pin and MODE/FAULT pin; Tested as VMODE when mode resistor is connected between MODE/FAULT pin and GND IMODE_PD MODE/FAULT pin pull down current after mode detection VMODE = 0.5 V, mode resistor is connected between VIN pin and MODE/FAULT pin 0.6 50 80 0.9 V µA OC, SC, OVP and SS ILIM Switch MOSFET current limit VOVP_clamp Output over voltage clamp threshold 2 2.5 3 A 1.47 1.5 1.53 V OVP ramp up 1.568 1.6 1.632 OVP ramp down 1.519 1.55 1.581 VOVP_sd Output over voltage shutdown threshold VOVP_SC Output short to GND detection threshold VOVP_IFB 1st level IFB overvoltage threshold IFBx current sink on VOVP2_IFB 2nd level IFB overvoltage threshold IFBx current sink on or off OVP ramp up OVP ramp down 90 V mV 50 70 7 8.5 10 V 16 18 20 V THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold 160 °C Thys Thermal shutdown hysteresis 15 °C 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 DEVICE INFORMATION MODE / FAULT VIN SW PGND PIN ASSIGNMENT 16 PIN 3mm × 3mm RTE PACKAGE (TOP VIEW) 16 15 14 13 PWM / EN 1 12 OVP VLDO 2 11 IFB1 TPS61176 IFB2 COMP 4 9 IFB3 6 7 8 GND 5 IFB4 10 IFB5 3 IFB6 ISET PIN FUNCTIONS PIN NUMBER 1 PWM/EN PWM dimming signal input and IC enable / disable control (1) 2 VLDO Internal pre-regulator output. Connect a 1 µF ceramic capacitor to this pin 3 ISET Full-scale LED current setting pin. Connect a resistor to the pin to program the full-scale LED current 4 COMP Connect an external 0.47µF ceramic capacitor to this pin for the boost loop compensation. IFB4 to IFB6, IFB1 to IFB3 Regulated current sinks input pins 5~7, 9~11 (1) DESCRIPTION NAME 8 GND Analog ground 12 OVP This pin monitors the output voltage of the boost converter through external resistor divider 13 PGND Power ground 14 SW Drain of the internal power MOSFET 15 VIN Supply input pin, provides power supply to the IC 16 MODE/FAULT Multi-function pin. Use this pin to program the dimming mode. It also functions as a driver for external isolation P-channel MOSFET (1) See Detailed Description section for details. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 5 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS Table 1. TABLE OF GRAPHS TITLE DESCRIPTION FIGURE Dimming Efficiency VBAT = 3V, 3.6V, 4.2V, 5V; VO = 18V, 6s6p, 20mA/string; PWM Freq = 200Hz; Mode 1; L = 6.8µH Figure 1 Dimming Efficiency VBAT = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s6p, 20mA/string; PWM Freq = 200Hz; Mode 1; L = 6.8µH Figure 2 Dimming Efficiency VBAT = 3V, 3.6V, 4.2V, 5V; VO = 24V, 8s5p, 20mA/string; PWM Freq = 200Hz; Mode 1; L = 6.8µH Figure 3 Dimming Efficiency VBAT = 3V, 3.6V, 4.2V, 5V; VO = 27V, 9s4p, 20mA/string; PWM Freq = 200Hz; Mode 1; L = 6.8µH Figure 4 Dimming Efficiency VIN = 5V; VBAT = 3V, 3.6V, 4.2V, 5V, 7.2V, 9V, 12V, 15V; VO = 18V, 6s6p, 20mA/string; PWM Freq = 200Hz; Mode 1; L = 6.8µH (refer to Figure 18) Figure 5 Dimming Linearity VBAT = 3V, 3.6V, 4.2V, 5V; VO = 21V, 7s6p; RISET = 53kΩ ; PWM Freq = 200Hz; Mode 1 Figure 6 Current Limit vs Input Voltage VO = 30V; TA = 25°C Figure 7 Switching Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; Duty = 100%; L = 6.8µH Figure 8 Switching Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; PWM Freq = 200Hz; Duty = 50%; L = 6.8µH; Mode 1 Figure 9 Switching Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; PWM Freq = 200Hz; Duty = 10%; L = 6.8µH; Mode 1 Figure 10 Switching Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; PWM Freq = 200Hz; Duty = 50%; L = 6.8µH; Mode 2 Figure 11 Switching Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; PWM Freq = 200Hz; Duty = 10%; L = 6.8µH; Mode 2 Figure 12 Startup Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; Duty = 100%; L = 6.8µH Figure 13 Startup Waveform VBAT = 3.6V; VO = 18V, 6s6p; RISET = 53kΩ; PWM Freq = 200Hz; Duty = 10%; L = 6.8µH; Mode 1 Figure 14 EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 100 100 VBAT = 5 V VBAT = 5 V 90 80 VBAT = 3.6 V Efficiency (%) Efficiency (%) 90 VBAT = 4.2 V VBAT = 3 V 70 VO = 18 V, 6s6p, 20 mA/string 60 VBAT = 3.6 V 80 VBAT = 4.2 V VBAT = 3 V 70 VO = 21 V, 7s6p, 20 mA/string 60 50 50 0 20 40 60 Dimming Duty Cycle (%) 80 100 0 C001 Figure 1. 6 20 40 60 Dimming Duty Cycle (%) 80 100 C002 Figure 2. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 EFFICIENCY vs DIMMING DUTY CYCLE EFFICIENCY vs DIMMING DUTY CYCLE 100 100 VBAT = 5 V VBAT = 5 V 90 80 Efficiency (%) Efficiency (%) 90 VBAT = 3.6 V VBAT = 3 V VBAT = 4.2 V 70 VO = 24 V, 8s5p, 20 mA/string 60 80 70 VBAT = 3 V VO = 27 V, 9s4p, 20 mA/string 60 50 50 0 20 40 60 80 100 Dimming Duty Cycle (%) 0 20 40 100 100 C004 DIMMING LINEARITY 140 VBAT = 15 V 120 IO - Output Current (mA) 95 Efficiency (%) 80 Figure 4. EFFICIENCY vs DIMMING DUTY CYCLE 90 VBAT = 5 V 85 VBAT = 7.2 V VBAT = 4.2 V 80 VBAT = 9 V VBAT = 3.6 V VBAT = 12 V VO = 18 V, 6s6p, 20 mA/string, VIN = 5 V VBAT = 3 V VBAT = 5 V 100 80 VBAT = 4.2 V 60 40 VBAT = 3.6 V 20 70 VBAT = 3 V 0 0 20 40 60 80 100 Dimming Duty Cycle (%) 0 40 60 80 100 C006 Figure 6. SWITCH CURRENT LIMIT vs INPUT VOLTAGE SWITCHING WAVEFORM 2.7 Output Voltage 100mV/div AC VO = 30 V 2.5 20 Dimming Duty Cycle (%) C005 Figure 5. ILIM - Switch Current Limit (A) 60 Dimming Duty Cycle (%) C003 Figure 3. 75 VBAT = 4.2 V VBAT = 3.6 V 2.3 SW Voltage 10V/div DC 2.1 Inductor Current 1A/div DC 1.9 1.7 Output Current 100mA/div DC 1.5 2.7 3.0 3.3 3.6 3.9 4.2 VI - Input Voltage (V) 4.5 4.8 C007 Figure 7. DUTY = 100% t - Time - 1µs/div Figure 8. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 7 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com SWITCHING WAVEFORM SWITCHING WAVEFORM Output Voltage 100mV/div AC Output Voltage 100mV/div AC SW Voltage 10V/div DC SW Voltage 10V/div DC Inductor Current 1A/div DC Inductor Current 1A/div DC Output Current 100mA/div DC PWM FREQ = 200HZ; DUTY = 50%; MODE 1 Output Current 100mA/div DC t - Time - 1µs/div t - Time – 20µs/div Figure 9. Figure 10. SWITCHING WAVEFORM SWITCHING WAVEFORM Output Voltage 100mV/div AC Output Voltage 100mV/div AC SW Voltage 10V/div DC SW Voltage 10V/div DC Inductor Current 1A/div DC Inductor Current 1A/div DC Output Current 100mA/div DC Output Current 50mA/div DC PWM FREQ = 200HZ; DUTY = 50%; MODE 2 PWM FREQ = 200HZ; DUTY = 10%; MODE 2 t - Time - 2ms/div t - Time - 1µs/div Figure 11. Figure 12. STARTUP WAVEFORM PWM Voltage 2V/div DC Output Voltage 10V/div DC PWM Voltage 1V/div DC Output Voltage 10V/div DC STARTUP WAVEFORM PWM FREQ = 200HZ; DUTY = 10%; MODE 1 Inductor Current 500mA/div DC Inductor Current 500mA/div DC Output Current 100mA/div DC DUTY = 100% Output Current 50mA/div DC t - Time - 10ms/div t - Time - 10ms/div Figure 13. 8 PWM FREQ = 200HZ; DUTY = 10%; MODE 1 Figure 14. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 FUNCTIONAL BLOCK DIAGRAM Optional L VIN C1 2.2uF R2 82k Diode C6 2.2uF C5 100pF C3 4.7uF SW MODE/FAULT VIN VLDO C2 1uF VOUT R3 1M Dimming Mode Detection OVP Fault protection OVC UVLO / Internal Regulator R OVP Q S OCP Slope Compensation OSC R4 43k Short to GND Protection VOVP S PGND Detector Comp COMP regulation Error Amp VOVP IFB no use Open /Short LED OVP C4 0.47uF IFB1 IFB2 IFB3 IFB4 IFB5 IFB6 Shut Down IFB1 EN Disable Detection RSET Dimming Mode Selection LED Current Current Mirror Dimming Control Analog Dimming R1 51k PWM/EN PWM decoding circuit OSC Duty Control Circuit PWM dimming PWM Signal Generator EA Current Sink GND Current Sink IFB2 Current Sink IFB3 Current Sink IFB4 Current Sink IFB5 Current Sink IFB6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 9 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com DETAILED DESCRIPTION TPS61176 is a high-efficiency, multi-channel WLED driver for tablet and notebook backlighting applications. As more and more WLED diodes are required to provide high brightness backlighting for high resolution panels, the WLED diodes must be arranged in parallel strings. Having more WLED diodes in a string reduces the number of parallel strings and thus improves overall current matching; however, the efficiency of the boost regulator drops due to the high output voltage. Therefore, six current sink regulators of high current matching capability are integrated in TPS61176 to provide the WLED connection flexibility and to improve the overall power efficiency. The six channels can also be combined as 2 or 3 channels to drive high brightness WLED diodes. TPS61176 has integrated all of the key function blocks to power and control up to 60 WLED diodes. The device consists of a boost converter with 2A/40V power MOSFET, six 35mA current sink regulators and protection circuit for over-current, over-voltage, open LED, short LED and output short circuit failures. TPS61176 accepts PWM dimming signal and implements mixed dimming mode. When the dimming duty cycle is high, analog dimming mode works, under which the IC controls the DC current of the WLED diodes to realize brightness dimming; when the dimming duty cycle is low, the IC switches to PWM dimming mode automatically, so the current of WLED diodes is turned on and off in a high frequency to realize dimming. The automatic switch between analog and PWM dimming modes can leverage the advantages of the two modes: increasing the electrical-to-optical efficiency by analog dimming and avoiding potential color shit issue. The switch point can be programmed to either 25% or 12.5% by the external resistor connected at MODE/FAULT pin. SUPPLY VOLTAGE TPS61176 can support single-cell Li-ion battery input directly. It has a built-in linear regulator to generate supply for internal analog and logic circuits. The VLDO pin, output of the regulator, should be connected to a 1 µF bypass capacitor for the regulator to be controlled in a stable loop. VLDO pin does not have current sourcing capability for external use. If TPS61176 is used in a multi-cell battery system, the battery cannot be connected to VIN pin directly. In this case, connect a 3.3V or 5V power rail to bias the VIN pin and connect the battery voltage to the inductor. The VIN pin only consumes less than 3mA for normal operation. Please refer to APPLICATION INFORMATION section for more details. BOOST CONVERTER The boost converter of TPS61176 has a fixed switching frequency of 1MHz and uses current-mode control. A 2A/40V power MOSFET is integrated so TPS61176 has a strong output driving capability. A 0.47µF~1µF capacitor should be connected at COMP pin to ensure stable output over the full input and output voltage ranges assuming the recommended inductance and output capacitance values shown in the Recommended Operating Conditions section are used. COMP pin is very sensitive, so careful layout is required to make sure no noise is coupled to it. The output voltage of the boost is automatically set by the IC to minimize the voltage drop across the IFBx (IFB1 ~ IFB6) pins. Normally the voltage across each WLED string is not same, so the voltages at IFBx pins are different. The IC regulates the lowest IFBx voltage to 450mV, and consistently adjusts the boost output voltage to account for any change of WLED's forward voltage drop. If the input voltage is higher than the strings' forward voltage drop (e.g. at low duty cycles), the boost converter can’t regulate the output due to its minimum duty cycle limitation. In this case, increasing the number of WLED diodes in series is helpful to provide enough headroom for the converter to boost the voltage. CURRENT SINKS The six current sink regulators embedded in TPS61176 can output up to 35mA current each. By regulating the current sinks, TPS61176 controls the current of the WLED strings to realize brightness dimming. The full-scale current per channel is programmed by the resistor at ISET pin according to Equation 1. VISET _ full IFBx _ full = ´ KISET RISET (1) Where: IFBx_full, full-scale current per channel KISET = 1024 (Current multiple) 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 VISET_full = 1.04V (ISET pin voltage under 100% dimming duty cycle) RISET = ISET pin resistor IFBx PIN UNUSED If less than six channels are used, a user can easily disable the unused channel(s) by shorting the corresponding IFBx pin(s) to ground. TPS61176 detects IFBx pins' short status during startup process and will disable the unused channel(s) before the boost converter starts switching. ENABLE AND STARTUP TPS61176 receives PWM signal at PWM/EN pin to implement the dimming as well as to enable and disable the IC. When PWM signal (high logic or PWM pulse) is input, the IC is enabled automatically; when the PWM signal is pulled low for more than 20ms, the IC is disabled and enters into shutdown mode. In shutdown mode, the boost converter stops switching, and the MODE/FAULT pin is internally pulled to VIN to turn off external isolation MOSFET for true shutdown. The input supply current at VIN pin is 4µA (max) in shutdown mode. In order to avoid fault triggered shut down during dimming, PWM dimming signal should have a higher frequency than 100Hz. Once enabled by PWM input, TPS61176 enters startup process. The internal regulator is enabled first to supply current to internal circuits. Then TPS61176 detects the RMODE at MODE/FAULT pin to set the dimming mode. TPS61176 can detect if the mode resistor is connected between VIN pin and MODE/FAULT pin or connected between MODE/FAULT pin and GND pin. If the mode resistor is detected to be between VIN pin and MODE/FAULT pin, which indicates an external isolation P-channel MOSFET is connected, the MODE/FAULT pin will be pulled down by an internal current sink to turn on the isolation MOSFET after the detection process. The IC also checks the status of all IFBx pins (short to ground or not) to disable any unused channels. There is no special time sequence requirement of VIN and PWM signals for startup. If PWM signal is input first, TPS61176 starts up when VIN powers up. The dimming mode and IFBx status detection process lasts about 4ms, during which the MODE/FAULT pin outputs a high voltage (VIN – 0.6V typical) to keep the isolation MOSFET off. When the 4ms detection window ends, an internal current sink pulls MODE/FAULT pin low to turn on the isolation MOSFET. Then another 4ms time window starts and at the end of the window the IC detects the OVP pin voltage. If the OVP voltage VOVP is still lower than VOVP_SC ramp up threshold (90mV typ.), which normally indicates output short to ground issue happens, the boost remains off and the MODE/FAULT pin is pulled up to VIN immediately by an internal resistor to turn off the isolation MOSFET. In this case, the IC restarts only after a power-on reset (POR) toggling or PWM toggling. POR toggling means the VIN pin voltage is pulled below UVLO falling threshold first and then pulled above UVLO rising threshold to restart the IC; PWM toggling means pulling PWM/EN low for more than 20ms to disable the IC and then apply PWM signal (high logic or PWM pulse) to restart the IC. If OVP voltage VOVP is higher than VOVP_SC ramp up threshold, indicating no short to ground issue is detected, boost starts switching to raise the output voltage. Soft start is implemented by gradually ramping up the reference voltage of the error amplifier to prevent voltage over-shoot and in-rush current. The capacitor at COMP pin can adjust the soft start speed. Larger capacitance leads to slower start up. 0.47µF~1µF COMP capacitor is recommended. BRIGHTNESS DIMMING CONTROL TPS61176 receives the PWM dimming signal at PWM/EN pin. An internal PWM decoding circuit detects the on time and the period of the PWM signal and calculates the duty cycle information. Then the IC controls the current sink regulators' output current according to the duty cycle to realize the brightness dimming. TPS61176 supports mixed dimming mode, which leverages the advantages of both analog dimming and PWM dimming modes. When the dimming duty cycle is high, analog dimming mode is auto-implemented, increasing the electrical-to-optical efficiency and reducing the power budget for the backlight; when the dimming duty cycle is low, PWM dimming mode is auto-implemented, eliminating potential color shift effect which normally happens when the DC current of WLED diode goes low. The switch point between analog dimming mode and PWM dimming mode can be programmed by the mode resistor connected at MODE/FAULT pin. TPS61176 provides four dimming mode options as shown in Table 2. Besides two different switch point options: 25% or 12.5%, TPS61176 also offers two different PWM dimming mode options: direct PWM dimming or 22kHz fixed frequency PWM dimming. Please refer to DIMMING MODE for the details of different dimming modes. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 11 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com Different mode resistor values set the different dimming modes. 5% or higher precision resistor should be used for the mode resistor. When an isolation P-channel MOSFET is connected, the mode resistor must be connected between VIN pin and MODE/FAULT pin; when the isolation MOSFET is not connected, the mode resistor should be connected between MODE/FAULT pin and ground. If there is no resistor connected at MODE/FAULT pin, which is only allowed when the isolation MOSFET is not connected, default mode (Mode 1) will be selected. Please refer to APPLICATION INFORMATION section for more details. Table 2. Dimming Mode Setting SWITCH POINT BETWEEN ANALOG AND PWM DIMMING MODE MODE RESISTOR DIMMING MODE Mode 1 (Default mode) 1.3 MΩ (5%) Analog dimming + 22 kHz fixed frequency PWM dimming Mode 2 620 kΩ (5%) Analog dimming + Direct PWM dimming Mode 3 220 kΩ (5%) Analog dimming + 22 kHz fixed frequency PWM dimming 12.5% Mode 4 82 kΩ (5%) Analog dimming + Direct PWM dimming 12.5% 25% 25% DIMMING MODE ANALOG DIMMING MODE In analog dimming mode, the brightness dimming is realized by controlling the DC current of WLED diodes. Since the forward voltage of a WLED diode drops when its DC current reduces, the required output voltage can become lower when dimming duty cycle goes low, reducing the power budget for the backlight and allowing more system power saving. In analog dimming mode, the current of IFBx is regulated according to Equation 2: VISET _ full V IFBx = ISET ´ KISET = ´ KISET ´ Duty RISET RISET (2) Where: IFBx, current per string VISET, (ISET pin voltage during analog dimming) KISET = 1024 (Current multiple) VISET_full = 1.04V (ISET pin voltage with 100% dimming duty cycle) RISET = ISET pin resistor Duty = duty cycle of the PWM signal PWM DIMMING When the dimming duty cycle is below the switch point, PWM dimming mode is automatically implemented. In this mode, the current sink regulators are turned on and off according to the PWM duty cycle information, so the illumination of WLEDs is intermittent. At frequencies higher than human eyes' critical flicker frequency, the brightness is the same as the average brightness of the fluctuating light, thus controlling the duty cycle can realize the brightness dimming. While a current sink regulator is turned on during PWM dimming, its output current is equal to the DC current at the switch point. For example, if the switch point is set to 25%, the regulator's output current during the "ON" phase is equal to IFBx_full x 25%, and the "ON" phase's duty cycle Duty' is equal to Duty / 25%, where Duty is the input PWM signal's duty cycle information. Then the average current during PWM dimming can be still equal to IFBx_full x Duty. This design is in order to keep the brightness consistency between analog dimming and PWM dimming and avoid any abrupt brightness change around the switch point. If the switch point is set to 12.5%, the regulator's output current during the "ON" phase is equal to IFBx_full x 12.5%, and the "ON" phase's duty cycle Duty' is equal to Duty / 12.5%. Refer to Figure 15 for a graphical explanation. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 PWM Dimming Analog Dimming D=100% D=80% D=60% D=25% D=12.5% D=6.25% PWM Input TON TPER IFBx_Full 80% 60% IFBx 50% D’=25% D’=50% 25% 0A (a). Mixed Dimming Mode with switch point = 25% Analog Dimming D=100% D=80% D=60% PWM Dimming D=25% D=12.5% D=6.25% PWM Input TON TPER IFBx_Full 80% 60% IFBx 50% D’=50% 25% 12.5% 0A (b). Mixed Dimming Mode with switch point = 12.5% Figure 15. Mixed Dimming Mode Generally, the average current of an LED string in PWM dimming mode is equal to VISET_full IFBx_PWM = ´ KISET ´ Duty RISET (3) Where: IFBx_PWM, average current per string in PWM dimming mode VISET_full = 1.04V (ISET pin voltage with 100% dimming duty cycle) KISET = 1024 (Current multiple) RISET = ISET pin resistor Duty = duty cycle of the PWM signal The frequency of the current sink regulators' ON and OFF control depends on which PWM dimming mode is set. TPS61176 provides two different PWM dimming modes: direct PWM dimming mode and 22kHz fixed frequency PWM dimming mode. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 13 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com In direct PWM dimming mode, the current sinks are turned ON and OFF with the same frequency detected from the input PWM signal. The advantage of this mode is the dimming frequency can be adjusted freely. In addition, it is easy to achieve high dimming resolution in direct PWM dimming mode: with lower input PWM frequency, the higher dimming resolution can be detected and output. For example, when the input PWM frequency is 100Hz, 14-bit resolution can be achieved; when the input PWM frequency is 20kHz, 9-bit resolution achieved. So if high resolution is required, 100Hz or 200Hz dimming frequency is recommended. TPS61176 is designed to minimize the AC ripple on the output capacitor during PWM dimming. Careful passive component selection is also crucial to minimize AC ripple on the output capacitor. In order to further avoid the potential audible noise, input PWM frequency out of audible frequency range is recommended. See APPLICATION INFORMATION for more information. In 22kHz fixed frequency PWM dimming mode, current sinks are turned on and off according to the duty cycle information detected from the input PWM signal but with an internally fixed frequency – 22kHz. This mode facilitates the application where the input PWM signal frequency can’t be adjusted outside the audio frequency range. So in this mode the audible noise can be eliminated completely. Human eyes are much more sensitive to the brightness change at low brightness compared to at high brightness, so in order to improve the visual experience and avoid any potential flickering perception, high resolution dimming is implemented in PWM dimming mode. TPS61176 can achieve up to 14-bit dimming resolution during the PWM dimming. Generally, higher resolution can be achieved with lower input PWM frequency. Please refer to Table 3 for detailed dimming resolution information. Table 3. Dimming Resolution Information in PWM Dimming Mode DIMMING MODE INPUT PWM FREQUENCY DIMMING RESOLUTION IN PWM DIMMING MODE 100Hz ~ 4.5kHz 12-bit 4.5kHz ~ 9kHz 11-bit 9kHz ~ 18kHz 10-bit 18kHz ~ 20kHz 9-bit 100Hz ~ 1kHz 14-bit Mode 1 Mode 2 Mode 3 Mode 4 1kHz ~2kHz 13-bit 2kHz ~ 4kHz 12- bit 4kHz ~ 8kHz 11-bit 8kHz ~ 16kHz 10-bit 16kHz ~ 20kHz 9 -bit 100Hz ~ 5kHz 12-bit 5kHz ~ 10kHz 11-bit 10kHz ~ 20kHz 10-bit 100Hz ~ 1.2kHz 14-bit 1.2kHz ~2.4kHz 13-bit 2.4kHz ~ 4.8kHz 12- bit 4.8kHz ~ 9.6kHz 11-bit 9.6kHz ~ 20kHz 10-bit OVER VOLTAGE PROTECTION The output voltage of the boost converter is detected by OVP pin. The Over-Voltage-Protection threshold can be programmed by an external resistor divider (R3 and R4 in Typical Application Circuits), allowing the usage of low voltage rating Schottky diode in low output voltage application. The correct divider ratio is important for optimum operation of TPS61176. Use the following guidelines to choose the divider value. It can be noise sensitive if Rupper and Rdown have high impedance. Careful layout is required. Also, choose lower resistance values for Rupper and Rdown when power dissipation allows. Step1. Determine the maximum output voltage, VOUT, for the system according to the number of series WLEDs. Step2. Select Rupper resistor value (1 MΩ for a typical application; a lower value such as 100 kΩ for a noisy environment). Step3. Calculate Rdown by using Equation 4. 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 æ Rupper ö VOUT = çç + 1÷÷ ´ VOVP _ clamp è Rdown ø (4) Where: VOVP_clamp = 1.5 V When the over-voltage threshold VOVP_clamp is reached, TPS61176 detects if there is any LED string open first by sensing whether there is current on IFBx pin. If any string is open, the corresponding current sink is disabled and removed from regulation. Subsequently, the output voltage drops down and will be regulated to a voltage for the connected WLED strings. The IFBx current of the connected WLED strings keeps in regulation during the whole transition. If an open string is reconnected again, a POR toggling or PWM toggling is required to reactivate a previously deactivated string. TPS61176 shuts down and keeps off when it detects that all of the WLED strings are open. In this case, a POR toggling or PWM toggling is required to restart the IC. If there isn’t any string open, TPS61176 regulates the boost output at the over-voltage threshold. If the output voltage can’t be regulated at the value set by Equation 4 and keeps rising, once the OVP pin voltage exceeds VOVP_sd rising threshold (1.6V typical), the boost stops switching. When the OVP voltage falls below VOVP_sd falling threshold (1.55V typical), the boost recovers to switch. During the process, the IFBx current of the connected WLED strings keeps in regulation. CURRENT SINK OPEN PROTECTION If any IFBx pin voltage is detected to exceed the 1st level IFB over-voltage threshold (8.5V typical) when its current sink is turned on, TPS61176 turns off this current sink and removes it from output regulation loop. The current regulation of the remaining IFBx pins is not affected. This situation often occurs when there are several shorted WLED diodes in one string. WLED mismatch typically does not create such large voltage difference among WLED strings. TPS61176 shuts down when it detects that all of the IFBx pin voltages exceed the threshold. In this case, a POR toggling or PWM toggling is required to restart the IC. If any IFBx pin voltage is detected to exceed the 2nd level IFB over-voltage threshold (18V typical) no matter the current sink is turned on or off, TPS61176 shuts down immediately to avoid potential over stress damage at IFBx pin. A POR toggling or PWM toggling is required to restart the IC. OVER CURRENT AND SHORT CIRCUIT PROTECTION TPS61176 has a pulse-by-pulse over-current limit of 2.0A (min). The boost power MOSFET is turned off when the inductor current reaches this current limit threshold and it remains off until the beginning of the next switching cycle. This protects TPS61176 and external component under overload conditions. Under severe over-load or short circuit conditions, if the OVP pin voltage is detected below VOVP_SC ramp down threshold (70mV typical), TPS61176 shuts down and the MODE/FAULT pin is pulled to VIN by an internal switch immediately. As a result, the external isolation MOSFET can be turned off at once, cutting off the power path from input to output. The IC restarts after a POR toggling or PWM toggling. THERMAL PROTECTION An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15°C. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 15 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION Because the selection of the inductor affects power supply’s steady state operation, transient behavior, loop stability and the boost converter efficiency, the inductor is the most important component in switching power regulator design. There are three specifications most important to the performance of the inductor: inductance value, DC resistance and saturation current. TPS61176 is designed to work with inductor values between 4.7µH and 10µH. A 4.7µH inductor is typically available in a smaller or lower profile package, while a 10µH inductor produces lower inductor ripple. If the boost output current is limited by the over-current protection of the IC, using a 10µH inductor can maximize the controller’s output current capability. In a boost regulator, the inductor DC current can be calculated as Equation 5. IDC = Vout ´ Iout Vin ´ h (5) Where Vout = boost output voltage Iout = boost output current Vin = boost input voltage η = power conversion efficiency, use 85% for TPS61176 normal applications The inductor current peak to peak ripple can be calculated as Equation 6. IPP = 1 1 1 ö æ L´ç + ÷ ´ FS è Vout - Vin Vin ø (6) Where IPP = inductor peak-to-peak ripple L = inductor value FS = Switching frequency Vout = boost output voltage Vin = boost input voltage Therefore, the peak current seen by the inductor is calculated with Equation 7. IP = IDC + IPP 2 (7) Select the inductor with saturation current over the calculated peak current. To calculate the worse case inductor peak current, use minimum input voltage, maximum output voltage and maximum load current. Converter efficiency is dependent on the resistance of its high current path and switching losses associated with the internal switch and external power diode. Although TPS61176 has optimized the internal switch resistance, the overall efficiency is affected by the inductor’s DC resistance (DCR). Lower DCR improves efficiency. However, there is a trade off between DCR and inductor footprint. Furthermore, shielded inductors typically have higher DCR than unshielded ones. Note that inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines saturation. Table 4 lists the recommended inductors. Table 4. Recommended Inductor for TPS61176 16 Part Number L (µH) DCR (mΩ) Isat (A) Size (L x W x H mm) Vendor PCMB051H-4R7MS PCMB051H-6R8MS 4.7 78 4.0 5.4 x 5.2 x 1.8 Cyntec 6.8 107 3.4 5.4 x 5.2 x 1.8 Cyntec PCMB051H-100MS 10 140 3 5.4 x 5.2 x 1.8 Cyntec LPS4018-472ML 4.7 125 1.9 4.0 x 4.0 x 1.8 Coilcraft Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 Table 4. Recommended Inductor for TPS61176 (continued) Part Number L (µH) DCR (mΩ) Isat (A) Size (L x W x H mm) Vendor LPS4018-103ML 10 200 1.3 4.0 x 4.0 x 1.8 Coilcraft A915AY – 4R7M 4.7 38 1.87 5.2 x 5.2 x 3 TOKO A915AY – 100M 10 75 1.24 5.2 x 5.2 x 3 TOKO OUTPUT CAPACITOR SELECTION The output capacitor is mainly selected to meet the requirement for the loop stability and the output ripple. The loop is designed to be stable with an output capacitor within 2.2µF ~ 10µF range. This output ripple is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Due to its low ESR, the ripple caused by ESR could be neglected for ceramic capacitors. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated with Equation 8. Cout = (Vout - Vin) ´ Iout Vout ´ FS ´ Vripple (8) Where: Vripple = peak-to-peak output ripple. Note that capacitor degradation increases the ripple much. Select the capacitor which has less degradation at the output voltage. If the output ripple is too large, change a bigger capacitor could be helpful. Normally, X5R ±10% or better capacitors are recommended. SCHOTTKY DIODE SELECTION TPS61176 demands a low forward voltage, high-speed rectification and low capacitance schottky diode for optimum efficiency. Ensure that the diode average and peak current rating exceeds the average output current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the open LED protection voltage. Vishay SS2P5, MSS1P4 and NXP PMEG4010EPK are recommended for TPS61176. ISOLATION FET SELECTION TPS61176 provides a gate driver at MODE/FAULT pin to drive an external P-channel MOSFET which can act as an isolation MOSFET. When the IC is disabled or output short to ground issue happens, MODE/FAULT pin can turn off the isolation MOSFET to cut off the power path from the battery to the output. The source of the MOSFET should be connected to the battery input, and an external resistor must be connected between the source and gate of the MOSFET to keep the FET off when TPS61176 is disabled. This gate resistor also acts as a mode resistor to select the dimming mode. To turn on the isolation MOSFET, an internal current sink pulls MODE/FAULT pin low. When output short to ground fault happens, an internal switch pulls up the MODE/FAULT pin to VIN, turning off the isolation MOSFET immediately. When the isolation FET is turned on during startup, an inrush current will flow through the MOSFET from battery to charge the output capacitor. If the peak current is too large, a capacitor can be connected between the source and the gate of the isolation MOSFET to control the turning on speed (C5 in Figure 16), thus controlling the inrush current. Normally, 100pF ~ 1nF capacitor is recommended. During output short to ground protection process, the catch diode (D2 in Figure 16) may be forward biased to provide the continuous current of the inductor when the isolation FET is turned off. In this case, the drain of the isolation FET swings below ground. The voltage across the isolation FET can be momentarily greater than the input voltage. Therefore, select at least 10V maximum input MOSFET. Adding a capacitor parallel with D2 (refer to Figure 16) could also help reduce the voltage across MOSFET when this failure happens. The on resistance of the MOSFET has large impact on power conversion efficiency since the MOSFET carries the input current. Select a MOSFET with Rds(on) less than 100mΩ to limit the power losses. In order to detect larger than 1M RMode correctly, the gate leakage of isolation MOSFET should be less than 0.1µA. In multi-cell battery input applications, if the isolation MOSFET is connected, the voltage at MODE/FAULT pin may exceed its maximum rating voltage 7V when the IC is disabled or output short to ground issue happens. In order to prevent this over stress damange, isolation MOSFET can't be connected. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 17 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com AUDIBLE NOISE REDUCTION The controller’s output voltage also ripples due to the load transient that occurs during PWM dimming. If the PWM dimming frequency is in the audible frequency range, the ripple can produce audible noises on the output ceramic capacitor. There are two ways of reducing or eliminating the audible noise. The first way is to reduce the amount of the output ripple, and therefore minimize the audible noise. TPS61176 adopts a patented technology to limit this type of output ripple even with the minimum recommended output capacitance. The second way is to select PWM dimming frequency outside the audible frequency range to eliminate the audible noise completely. However, in some applications, the input PWM signal’s frequency range couldn’t be adjusted outside the audible frequency range. To solve this problem, TPS61176 provides the 22kHz fixed frequency PWM dimming mode. In this dimming mode, no matter what the input PWM frequency is, the PWM dimming is implemented at 22kHz, which is outside the audible frequency range, saving the effort to adjust the input PWM frequency. LAYOUT CONSIDERATION As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in the typical application circuit Figure 16, needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the input ripple seen by the IC. It should also be placed close to the inductor. C3 is the filter and noise decoupling capacitor for the internal linear regulator powering the internal digital circuits. It should be placed as close as possible between the VLDO and GND pins to prevent any noise insertion to the digital circuits. The SW pin carries high current with fast rising and falling edges. Therefore, the connection between the SW pin to the inductor and schottky diode should be kept as short and wide as possible. The trace between schottky diode and the output capacitor C2 should also be as short and wide as possible. It is also beneficial to have the ground of the output capacitor C2 close to the PGND pin since there is a large ground return current flowing between them. When laying out signal grounds, it is recommended to use short traces separated from power ground traces, and connect them together at a single point, for example on the thermal pad. The thermal pad needs to be soldered on to the PCB and connected to the GND pin of the IC. An additional thermal via can significantly improve power dissipation of the IC. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 TYPICAL APPLICATION CIRCUITS SINGLE-CELL BATTERY INPUT APPLICATION TPS61176's VIN pin voltage range is from 2.7V to 6.5V, so it can support single-cell battery input directly. If isolation MOSFET is connected, the mode resistor must be connected between VIN pin and MODE/FAULT pin as shown in Figure 16; if isolation MOSFET is not connected, the mode resistor can be connected between VIN pin and GND as shown in Figure 17. If there is no resistor connected at MODE/FAULT pin, which is only allowed when the isolation MOSFET is not connected, default mode (Mode 1) will be selected. 2.7V ~ 6.5V L1 4.7uH Q1 Up to 38V D1 VIN C1 2.2uF R2 1.3M C6 2.2uF C5 D2 100pF SW MODE / FAULT C2 4.7uF R3 1M PGND OVP R4 43k VIN TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF PWM IFB5 IFB6 PWM / EN ISET R1 51k COMP C4 0.47uF GND Figure 16. Typical Applications (single-cell battery input application) L1 4.7uH 2.7V ~ 6.5V Up to 38V D1 VIN C1 2.2uF SW R2 1.3M MODE / FAULT C2 4.7uF R3 1M PGND OVP R4 43k VIN TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF PWM IFB5 IFB6 PWM / EN ISET R1 51k COMP GND C4 0.47uF Figure 17. Typical Applications (single-cell battery input without isolation MOSFET application) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 19 TPS61176 SLVSBM5 – DECEMBER 2012 www.ti.com MULTI-CELL BATTERY INPUT APPLICATION In multi-cell battery input applications, because normally the input voltage is higher than VIN pin and MODE/FAULT pin’s maximum rating voltage 7V, the battery input can't be connected to VIN pin directly and the isolation MOSFET can't be connected either. A 3.3V or 5V bias is required to power VIN pin of the IC with up to 3mA current consumption, and the mode resistor should be connected between MODE/FAULT pin and ground. Please refer to Figure 18 as below. L1 4.7uH 2.7V ~ 24V Up to 38V D1 VBAT C1 2.2uF C2 4.7uF SW MODE / FAULT 2.7V ~ 6.5V R2 1.3M R3 1M PGND OVP R4 43k VIN C5 1uF TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF PWM IFB5 IFB6 PWM / EN ISET R1 51.2k COMP C4 0.47uF GND Figure 18. Typical Applications (Multi-cell battery input application) COMBINED STRING APPLICATION TPS61176 provides six current sinks with up to 35mA current capability each. If high brightness WLED diodes are used, the current sinks can be combined as two or three channels to support higher current capability requirement. Please refer to Figure 19 as below. L1 4.7uH 2.7V ~ 24V D1 Up to 38V VBAT C1 2.2uF SW MODE / FAULT 2.7V ~ 6.5V R2 1.3M C2 4.7uF R3 1M PGND OVP R4 43k VIN C5 1uF TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF PWM ISET R1 51.2k Up to 60mA per string IFB5 IFB6 PWM / EN COMP GND C4 0.47uF Figure 19. Typical Applications (combined string to support high brightness WLED diodes) 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 TPS61176 www.ti.com SLVSBM5 – DECEMBER 2012 SEPARATE PWM AND EN SIGNALS APPLICATION TPS61176 can be enabled or disabled automatically according to the PWM signal’s status. However, if the user wants to use separate EN and PWM signals to control the driver, the application circuit in Figure 20 or Figure 21 are recommended. L1 4.7uH 2.7V ~ 24V Up to 38V D1 VBAT C1 2.2uF C2 4.7uF SW MODE / FAULT R2 1.3M 2.7V ~ 6.5V R3 1M PGND OVP R4 43k VIN C5 1uF TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF Q2 PWM C6 100pF R5 10k EN R6 470k IFB5 IFB6 PWM / EN ISET R1 51.2k COMP C4 0.47uF GND Q2: BSS138 / FDV301N Figure 20. Typical Applications (to support separate 3.3V logic PWM and EN signals) L1 4.7uH 2.7V ~ 24V Up to 38V D1 VBAT C1 2.2uF SW MODE / FAULT R2 1.3M 2.7V ~ 6.5V C2 4.7uF PGND OVP R4 43k VIN C5 1uF TPS61176 IFB1 IFB2 IFB3 IFB4 VLDO C3 1uF R5 82k R3 1M R6 82k PWM IFB5 IFB6 PWM / EN Q2 ISET R1 51.2k COMP GND C4 0.47uF Q2: MMBT3904 EN Figure 21. Typical Applications (to support separate 1.8V logic PWM and EN signals) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS61176 21 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) TPS61176RTER ACTIVE Package Type Package Pins Package Qty Drawing WQFN RTE 16 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) CU NIPDAU MSL Peak Temp Samples (3) (Requires Login) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS61176RTER Package Package Pins Type Drawing WQFN RTE 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61176RTER WQFN RTE 16 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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