Evaluation board available. NX2114/2114A 300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER PRELIMINARY DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX2114 controller IC is a synchronous Buck controller IC designed for step down DC to DC converter applications. Synchronous control operation replaces the traditional catch diode with an Nch MOSFET resulting in improved converter efficiency. Although the NX2114 controller is optimized to convert single 5V bus voltages to supplies as low as 0.8V output voltage, however using a few external components it can also be used for other input supplies such as 12V input (See NX2113 data sheet for more optimized solution). The NX2114 operates at 300kHz while 2114A is set at 600kHz operation which together with less than 50 nS of dead band provides an efficient and cost effective solution. Other features of the device are: Internal digital soft start; Vcc undervoltage lock out; Output undervoltage protection with digital filter and shutdown capability via the enable pin. +5V APPLICATIONS n n n n n Graphic Card on board converters Memory Vddq Supply in mother board applications On board DC to DC such as 5V to 3.3V, 2.5V or 1.8V Hard Disk Drive Set Top Box TYPICAL APPLICATION C4 47uF,70mohm R5 10 5 1 Vcc BST Comp NX2114 7 OFF R6 10k C2 1.5nF 2N3904 C1 47pF D1 MBR0530T1 C6 1uF C8 47uF,70mohm R7 10k Synchronous Controller in 8 Pin Package Bus voltage operation from 2V to 25V Single 5V Supply Operation Short protection with feedback UVLO Internal 300kHz for 2114 and 600kHz for 2114A Internal Digital Soft Start Function Shut Down via pulling comp pin low Pb-free and RoHS compliant L2 1uH Vin ON n n n n n n n n R4 22.1k 6 Hdrv 2 C5 1uF Cin 220uF,12mohm M1 L1 1.5uH SW Ldrv Fb C7 0.1uF 8 4 Vout +1.6V,6A Co 2 x (220uF,15mohm) M2 Gnd 3 R1 10.2k R2 10.2k R3 1.5k C3 2.2nF Figure1 - Typical application of 2114 ORDERING INFORMATION Device NX2114CSTR NX2114ACSTR Rev. 4.0 06/20/06 Temperature 0 to 70oC 0 to 70o C Package SOIC-8L SOIC-8L Frequency 300kHz 600kHz Pb-Free Yes Yes 1 NX2114/2114A ABSOLUTE MAXIMUM RATINGS (NOTE1) Vcc to GND & BST to SW voltage ................... 6.5V BST to GND Voltage ...................................... 35V Storage Temperature Range ............................. -65oC to 150oC Operating Junction Temperature Range ............. -40oC to 125oC NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 8-PIN PLASTIC SOIC (S) θJA ≈ 130o C/W BST 1 HDrv 2 8 SW 7 Comp Gnd 3 6 Fb LDrv 4 5 Vcc ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) VCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) IBST (Static) Outputs not switching VBST Supply Current (Dynamic) IBST CLOAD=3300pF (Dynamic) Under Voltage Lockout VCC-Threshold VCC-Hysteresis VCC_UVLO VCC Rising VCC_Hyst VCC Falling Rev. 4.0 06/20/06 SYM VREF Test Condition Min 4.5V<Vcc<5.5V TYP MAX 0.8 0.1 FS=300kHz 4.5 5 2.1 5 Units V % 5.5 V mA mA 0.15 mA 5 mA 4.2 0.22 V V 2 NX2114/2114A PARAMETER SS Soft Start time Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Error Amplifiers Transconductance Input Bias Current Comp SD Threshold FB Under Voltage Protection FB Under voltage threshold High Side Driver(C L=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Output Sourcing Current Output Sinking Current Rise Time Fall Time Deadband Time Low Side Driver (C L=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Output Sourcing Current Output Sinking Current Rise Time Fall Time Deadband Time Rev. 4.0 06/20/06 SYM Tss FS Test Condition Min TYP MAX Units Fsw=300Khz, 2114 Fsw=600Khz, 2114A 3.4 1.7 mS 2114 2114A 300 600 1.7 94 kHz kHz V % % VRAMP 0 Ib 1900 10 0.3 umho nA V 0.4 V Rsource(Hdrv) I=200mA 1.1 ohm Rsink(Hdrv) I=200mA 0.8 ohm THdrv(Rise) THdrv(Fall) Tdead(L to H) VBST-VHDRV=5V VHDRV-VSW =5V 10% to 90% 90% to 10% Ldrv going Low to Hdrv going High, 10%-10% 2 2 50 50 30 A A ns ns ns Rsource(Ldrv) I=200mA 1.1 ohm Rsink(Ldrv) I=200mA 0.5 ohm 2 4 50 50 30 A A ns ns ns VPVCC-VLDRV=5V VLDRV-PGND=5V TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv L) going High, 10% to 10% 3 NX2114/2114A PIN DESCRIPTIONS PIN # 1 BST PIN DESCRIPTION This pin supplies voltage to the high side driver. A high frequency ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin. 2 HDRV High side MOSFET gate driver. 3 GND Ground pin. 4 LDRV Low side MOSFET gate driver. 5 Vcc Voltage supply for the internal circuit as well as the low side MOSFET gate driver. A 1uF high frequency ceramic capacitor must be connected from this pin to GND pin. 6 FB This pin is the error amplifier inverting input. This pin is also connected to the output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs are latched off. 7 COMP This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft start is reset. 8 SW This pin is connected to the source of the high side MOSFET and provides return path for the high side driver. Rev. 4.0 06/20/06 PIN SYMBOL 4 NX2114/2114A BLOCK DIAGRAM VCC 5 UVLO DRIVER 1 BST 2 Hdrv 8 SW 4 Ldrv 3 GND 7 COMP 6 FB OSC Q S Q R 0.3V LATCH DIGITAL SS TIMER 0.4V VREF Figure 1 - Simplified block diagram of the NX2114 Rev. 4.0 06/20/06 5 NX2114/2114A Demoboard design and waveforms sdfd L2 1uH Vin +5V C4 47uF,70mohm R5 10 C6 1uF 7 5 1 Vcc BST Comp C2 1.5nF R4 22.1k 6 NX2114 C8 47uF,70mohm C1 47pF D1 1N5819 Hdrv Cin 220uF,12mohm M1 2 L1 1.5uH SW Ldrv Fb C7 0.1uF C5 1uF 8 Co 2 x (220uF,15mohm) M2 4 Vout +1.6V,6A Gnd 3 R1 10.2k R2 10.2k R3 C3 1.5kohm 2.2nF Figure 2 - demoboard design on NX2114 Bill of Material Name Component de scription Vendor Vendor P/N 1% chip resistor Num b e r R1 10.2k 1 R2 10.2k R3 1.5k R4 22.1k 1% c hip resistor R5 10 C1 47pF ceramic 1 C2 1.5nF ceramic 1 C3 2.2nF C4,C8 47uF,16V,70mohm,SMD C5,C6 1uF ceramic 1 C7 CIN 0.1uF ceramic 220uF,6.3V,12mohm,SMD Sanyo 6TPD220M 1 1 CO 220uF,4V,15mohm,SMD Sanyo 4TPE220MF 2 D1 Diode D1N5819 1 M1,M2 MOSFET Fairchild FDS6294 1 L1 1.5uH,6.8A Coilcraft DO3316P-152 1 L2 1uH,6.4A Coilcraft DO3316P-102 1 1% c hip resistor 1 1% c hip resistor 1 sdfdsf 1 chip resistor 1 ceramic 1 Sanyo 16TQC47M 1 Note: To make sure short circuit protection of device functions correctly, C8 and R5 are necessary for filtering noise in single power supply design. Rev. 4.0 06/20/06 6 NX2114/2114A Vin=5V,Vout=1.6V Efficiency (%) f 95 90 85 80 75 70 0 1 2 3 Current (A) 4 Figure 3: Output efficiency Figure 5: Start up time Figure 7: Output voltage droop during transient(0A-6A) Rev. 4.0 06/20/06 5 6 Figure 4: Voltage ripple @1.6 V output voltage, 7A output current Figure 6: Output voltage transient response for load curent 0A-6A Figure 8: Startup operation waveform 7 NX2114/2114A APPLICATION INFORMATION Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current = VIN -VOUT VOUT 1 × × LOUT VIN FS 5V-1.6V 1.6v 1 × × = 2.4A 1.5uH 5v 300kHz ...(2) Output Capacitor Selection DVRIPPLE - Output voltage ripple FS ∆IRIPPLE = Output capacitor is basically decided by the - Working frequency amount of the output voltage ripple allowed during steady DIRIPPLE - Inductor current ripple state(DC) load condition as well as specification for the load transient. The optimum design may require a couple schematic is figure 2. of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load VIN = 5V condition is determined by equation(3). Design Example The following is typical application for NX2114, the VOUT=1.6V ∆VRIPPLE = ESR × ∆IRIPPLE + IOUT=6A DVRIPPLE <=20mV ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent DVDROOP<=60mV @ 6A step series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection such as Aluminum Electrolytic,POSCAP and OSCON The selection of inductor value is based on types are used, the amount of the output voltage ripple inductor ripple current, power rating, working frequency is dominated by the first term in equation(3) and the and efficiency. Larger inductor value normally means second term can be neglected. smaller ripple current. However if the inductance is For this example, POSCAP are chosen as output chosen too large, it brings slow response and lower capacitors, the ESR and inductor current typically de- efficiency. Usually the ripple current ranges from 20% termines the output voltage ripple. to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations: LOUT V -V V 1 = IN OUT × OUT × ∆IRIPPLE VIN FS IRIPPLE = k × IOUTPUT 5V-1.6V 1.6V 1 L OUT = × × 0.4 × 6A 5V 300kHz L OUT =1.51uH Choose inductor from COILCRAFT DO3316P-152 with L=1.5uH is a good choice. Rev. 4.0 06/20/06 ∆VRIPPLE 20mV = = 8.6mΩ ∆IRIPPLE 2.3A ...(4) If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP ...(1) where k is between 0.2 to 0.4. Select k=0.4, then Current Ripple is recalculated as ESR desire = 4TPE220MF with 15mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 15mΩ × 2.3A 20mV N =1.8 The number of capacitor has to be round up to a integer. Choose N =2. 8 NX2114/2114A If ceramic capacitors are chosen as output ca- voltage droop or overshoot is only dependent on the ESR pacitors, both terms in equation (3) need to be evaluated of output capacitor. For low frequency capacitor such to determine the overall ripple. Usually when this type of as electrolytic capacitor, the product of ESR and ca- capacitors are selected, the amount of capacitance per pacitance is high and L ≤ L crit is true. In that case, the single unit is not sufficient to meet the transient specifi- transient spec is dependent on the ESR of capacitor. cation, which results in parallel configuration of multiple capacitors. capacitors in parallel. The number of capacitors can be For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple is ∆VRIPPLE In most cases, the output capacitors are multiple calculated by the following N= 2.3A = 2mΩ × 2.3A + 8 × 300kHz × 100uF = 4.6mV + 9.6mV = 13.2mV ESR E × ∆Istep ∆Vtran is specified as: ∆VDROOP <∆VTRAN @ step load DISTEP transient is composed of two sections. One Section is 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT Lcrit = sient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. ...(6) where τ is the a function of capacitor, etc. The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is τ= = ...(7) where ESR × COUT × VOUT ESR E × C E × VOUT = ∆Istep ∆Istep where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. L × ∆I step VOUT − ESR E × C E 1.5µH × 6A − 15mΩ × 220µF = 2.3us 1.6V N= ...(8) ESR E × C E × VOUT = ∆Istep 15mΩ × 220µF × 1.6V = 0.88µH 6A when load from high load to light load with a DISTEP tran- L crit = ...(10) used, the critical inductance is given as input, output voltage. For example, for the overshoot, L ≥ L crit L ≥ L crit If the POSCAP 2R5TPE220MC (220uF, 12mΩ ) is a function of the inductor, output capacitance as well as if if For example, assume voltage droop during tran- dependent on the ESR of capacitor, the other section is 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT ...(9) sient is 100mV for 6A load step. During the transient, the voltage droop during the VOUT × τ2 2 × L × COUT VOUT × τ2 2 × L × C E × ∆Vtran where Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient ∆Vovershoot = ESR × ∆Istep + + ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × CE × ∆Vtran 15mΩ × 6A = + 60mV 1.6V × 2.3us 2 2 ×1.5µH × 220µF × 60mV = 1.7 The above equation shows that if the selected output inductor is smaller than the critical inductance, the The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. Rev. 4.0 06/20/06 9 NX2114/2114A It should be considered that the proposed equation is based on ideal case, in reality, the droop or over- FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) shoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of 1 FP2 = 2 × π × R4 × capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the ...(14) C1 × C2 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Their locations are shown in figure 10. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm is desirable. zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. A. Type III compensator design Zin R3 R2 For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero C3 sate the system with type III compensator. The following figures and equations show how to realize the type III C2 R4 Fb caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen- Zf C1 Vout gm Ve R1 Vref compensator by transconductance amplifier. Figure 9 - Type III compensator using transconductance amplifier Rev. 4.0 06/20/06 10 NX2114/2114A Gain(db) FO=30kHz. C3 = power stage FLC 40dB/decade 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 6.2kHz 48kHz =2.2nF = R4 = loop gain FESR VOSC 2 × π × FO × L × × Cout Vin C3 1.7V 2 × π × 30kHz × 1.5uH × × 440uF 5V 2.2nF =19.2k Ω = 20dB/decade Choose C3=2.2nF, R 4=22.1kΩ. compensator 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). FZ1 FZ2 FO FP1 FP2 C2 = 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 6.2kHz × 22.1kΩ = 1.55nF = Figure 10 - Bode plot of Type III compensator Design example for type III compensator are in order. The crossover frequency has to be selected as FLC<FO<FESR, and FO<=1/10~1/5Fs. 1. Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 × π × L OUT × COUT 1 2 × π × 1.5uH × 440uF = 6.2kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 7.5m Ω × 440uF = 48kHz = 2. Set R2 equal to10.2kΩ, then R1= 10.2kΩ. Choose C2=1.5nF. 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. C1 = 1 2 × π × R 4 × FP2 1 2 × π × 22.1kΩ × 150kHz = 48pF = Choose C1=47pF. 7. Calculate R 3 by equation (13). R3 = 1 2 × π × FP1 × C3 1 2 × π × 48kHz × 2.2nF = 1.5k Ω = Choose R3=1.5kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate R 4 and C3 with the crossover frequency at 1/10~ 1/5 of the switching frequency. Set Rev. 4.0 06/20/06 11 NX2114/2114A Vout B. Type II compensator design If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensa- R2 Fb tor can be used to compensate the system. Type II compensator can be realized by simple Ve gm R1 R3 Vref RC circuit without feedback as shown in figure 12. R3 C2 and C1 introduce a zero to cancel the double pole C1 effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain. Gain=gm × Fz = R1 × R3 R1+R2 ... (15) 1 2 × π × R3 × C1 Fp ≈ ... (16) 1 2 × π × R3 × C2 ... (17) Figure 12 - Type II compensator with transconductance amplifier For this type of compensator, FO has to satisfy FLC<FESR<<FO<=1/10~1/5Fs. The following uses typical design in figure 19 as an example for type II compensator design, two 680uF with 41mΩ electrolytic capacitors are used. 1.Calculate the location of LC double pole F LC and ESR zero FESR. Gain(db) power stage 40dB/decade FLC = 1 2 × π × L OUT × COUT 1 = loop gain 2 × π × 1.5uH × 1360uF = 3.5kHz 20dB/decade FESR = 1 2 × π × ESR × COUT 1 2 × π × 20.5m Ω × 1360uF = 5.7kHz = compensator Gain 2.Set R2 equal to10.2kΩ. Using equation 18, the FZ FLC FESR FO FP final selection of R1 is 3.24kΩ. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. Figure 11- Bode plot of Type II compensator Rev. 4.0 06/20/06 4.Calculate R3 value by the following equation. 12 NX2114/2114A 1.6V, the result of R1 is 10kΩ. R3 = VOSC 2 × π × FO × L 1 R1+R2 × × × Vin RESR gm R1 1.7V 2 × π × 30kHz × 1.5uH 1 × × 12 20.5Ω 1.9mA/V 10.2kΩ+3.24kΩ × 3.24kΩ =4.23kΩ Vout R2 Fb = R1 Vref Choose R 3 =4.53kΩ. Voltage divider 5. Calculate C1 by setting compensator zero FZ Figure 13 - Voltage divider In general, the minimum output load impedance at 75% of the LC double pole. C1 = 1 2 × π × R3 × Fz including the resistor divider should be less than 5kΩ to 1 2 × π × 4.51kΩ × 0.75 × 3.5kHz =13.3nF = prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A minimum load for 5kΩ less (<1/16w for most of application) is recommended to put at the output. For example, Choose C1=12nF. 6. Calculate C2 by setting compensator pole Fp at half the swithing frequency. in this application, Vout=1.6V The power loss is 1/16W less RLOAD = 1.6V × 1.6V /(1/16W) = 40Ω 1 C2 = p × R3 × Fs Select minimum load, 1kΩ should be good enough. 1 = p × 3.74kΩ × 300kHz =235pF Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic ca- Choose C2=220pF. pacitors bypass the high frequency noise, and bulk ca- Output Voltage Calculation Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V pacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise. The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as: when the output voltage is at the desired value. The IRMS = IOUT × D × 1- D following equation and picture show the relationship D= between VOUT , VREF and voltage divider.. R 1= R 2 × VR E F V O U T -V R E F ...(19) VIN = 5V, VOUT=1.6V, IOUT=6A, using equation ...(18) where R 2 is part of the compensator, and the value of R1 value can be set by voltage divider. Choose R2=10kΩ, to set the output voltage at Rev. 4.0 06/20/06 VOUT VIN (19), the result of input RMS current is 2.80A. For higher efficiency, low ESR capacitors are recommended. One Sanyo TPD series POSCAP 6TPD220M 6V 220uF with 12mΩ is chosen as input bulk capacitor. 13 NX2114/2114A Power MOSFETs Selection dependent. The NX2114 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. In this design example, two Fairchild FDS6294 are used. They have the following parameters: VDS=30V, ID =13A, RDSON =14.4mΩ,QGATE =10nC. There are three factors causing the MOSFET power loss: conduction loss, switching loss and gate driver loss. Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits. It is proportional to frequency and is defined as: Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS ...(20) Soft Start, Enable and shut Down The NX2114 has a digital start up. It is based on digital counter with 1024 cycles. For NX2114 with 300kHz operation, the start up time is about 3.5ms. For NX2114A with 600kHz operation, the start up time is about half of NX2114, 1.75mS. NX2114/NX2114A can be enabled or disabled by pulling COMP pin below 0.3V. The function is illustrated in the following diagram. During the normal operation, the lowest COMP voltage is clamped to be about 700mV , the COMP voltage is higher than 0.3V. If external switch with 10Ω Rdson or less to pull down COMP pin, when COMP is below 0.3V, the digital soft start will be reset to zero. All the drivers will be off. The synchronous buck is where QHGATE is the high side MOSFETs gate shut off. When external switch is released, and COMP charge, QLGATE is the low side MOSFETs gate charge, is above 0.3V, a soft start will initiates and system starts VHGS is the high side gate source voltage, and VLGS is from the beginning. the low side gate source voltage. According to equation (20), PGATE =0.03W. This power dissipation should not exceed maximum power dissipation of the driver device. Conduction loss is simply defined as: 2114 Shut down PH C O N = I O U T 2 × D × R D S ( O N ) × K FB PL C O N = I O U T 2 × (1 − D ) × R D S (O N ) × K P T O T A L = PH C O N + PL C O N Compensation Network ...(21) where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for o the worst case, in which K equals to 1.43 at 125 C comp OFF ON 0.3V 0.6 1.3V Clamp according to FDS6294 datasheet. Using equation (21), the result of PTOTAL is 0.75W. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. PSW 1 = × VIN × IOUT × TSW × FS 2 Figure 14 - Enable and Shut down NX2114 by pulling down COMP pin. Feedback Under Voltage Shut Down NX2114 relies on the Feedback Under Voltage Lock ...(22) where IOUT is output current, TSW is swithing time,and FS Out (FB UVLO ) to provide short circuit protection. Basically, NX2114 has a comparator compare the feedback voltage with the FB UVLO threshold 0.4V. is switching frequency. Swithing loss PSW is frequency Rev. 4.0 06/20/06 14 NX2114/2114A During the normal operation, if the output is short, age Lock Out comparator is disabled. After half of start the feedback voltage will be lower than 0.4V and com- up time, the Feedback UVLO comparator is enabled. parator will change the state. After certain internal delay, The FB UVLO threshold is set to be half of voltage at the both high side and low side driver will be turned off. The positive input of error amplifier. With this set up, if the output will be latched. The normal operation should be output is short before soft start, the Feedback UVLO achieved by removing the short and recycle the VCC. comparator can catch it and turn off the driver. The short circuit operation waveform during normal operation and during the soft start are shown as follows. During the normal operation, Feedback UVLO will take the role. But during the soft start, due to the input voltage dropping, UVLO Vcc will take the role, hiccup happens. The Feedback UVLO can provide short circuit protection under certain conditions. However, since feedback does not have accurate information of current, this protection only provides certain level of over current protection. MOSFET should design such that it can survive with high pulse current for a short period of time. Figure 15 - Operation waveforms during short condition. Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. CH3-bus voltage 5V/DIV There are two sets of components considered in the layout which are power components and small sigCH2-Vcc voltage 5V/DIV nal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, CH1-Fb voltage 0.5V/DIV inductor and output capacitors. A noisy environment is generated by the power components due to the switch- CH4-output current 10A/DIV ing power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input Figure 16 - Operation waveform with start up at short. During the start up, the output voltage is discharged to zero by the synchronous FET. FB voltage starts in- capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. crease from zero when digital start block operates. Be- 2. Low ESR capacitor which can handle input RMS fore half of the start up time, the Feedback Under Volt- ripple current and a high frequency decoupling ceramic Rev. 4.0 06/20/06 15 NX2114/2114A cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed. 7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. Rev. 4.0 06/20/06 16 NX2114/2114A TYPICAL APPLICATION Single Supply 5V Input L2 1uH Vin +5V R3 10 C4 33uF C3 C6 1uF 33uF D1 MBR0530T1 1 5 7 C2 8.2nF C1 150pF R4 7k 6 Hdrv NX2114 Comp Cin 2 x (470uF,60mohm) C7 0.1uF BST Vcc C5 1uF M1 2 L1 1.5uH SW Ldrv Fb Vout +2.5V,10A 8 M2 4 Co 4 x (330uF,80mohm) Gnd 3 R1 10 k 1% R2 4.7 k 1% Figure 17 - Application of NX2114 for 5V input and 2.5V output with electrolytic capacitors L2 1uH Vin 7 5 1 Vcc BST Comp C2 330pF R4 120 k 6 Cin 3 x 22uF X7R D1 MBR0530T1 C6 1uF C3 22uF C1 4.7pF C5 1uF R3 10 C4 22uF NX2114A +5V Fb Hdrv 2 C7 0.1uF M1 L1 3.3uH SW Ldrv 8 4 M2 Co 10 x 22uF X7R Vout +1.2V,4A Gnd 3 R2 20 k 1% R1 10 k 1% R3 787 C3 820pF Figure 18 - Application of NX2114 A for 5V input and 1.2V output with ceramic output capacitors Rev. 4.0 06/20/06 17 NX2114/2114A TYPICAL APPLICATIONS(CONT') Dual power supply (+5V BIAS,+12V BUS) L2 1uH Vin +12V C5 1uF C3 33uF Cin 2 x (47uF,60mohm) D1 MBR0530T1 Vin C6 1uF R8 1k R5 10 k 7 R7 5 k 5 1 Vcc BST Comp C2 15nF C1 270pF 2N3904 R4 3.74 k 6 2N3904 R6 680 C4 0.1uF Hdrv NX2114 +5V M1 2 L1 1.5uH Co 2 x (680uF,41mohm) M2 4 Ldrv Fb Vout +3.3V,10A 8 SW Gnd 3 R1 10.2 k 1% R2 3.24 k 1% Figure 19 -Application of NX2114 for 5V bias and 12V input bus Single power supply (+11V to +24V BUS) L2 1uH Vin +11~25V C4 33uF R5 3k C5 1uF Cin 2 x (47uF,60mohm) 2N3904 R6 10k D1 MBR0530T1 C6 2.2uF R7 10 k 7 5 1 Vcc BST Comp NX2114 TL431 C2 2.7nF C1 220pF R4 15k 6 Hdrv 2 M1 L1 5uH SW Ldrv Fb C7 0.1uF 8 4 M2 Vout +1.6V,5A Co 2 x (680uF,41mohm) Gnd 3 R2 10 k 1% R1 10 k 1% R3 787 C3 1nF Figure 20 -Application of NX2114 for high input bus application Rev. 4.0 06/20/06 18 NX2114/2114A SOIC8 PACKAGE OUTLINE DIMENSIONS Rev. 4.0 06/20/06 19 NX2114/2114A Rev. 4.0 06/20/06 20