LM2743 N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V General Description Features The LM2743 is a high-speed, N-Channel synchronous buck regulator controller with a 2%, 0.6V feedback reference voltage intended to make down conversion from 3.3V to as low as 0.6V easy. A fixed-frequency voltage-mode PWM control architecture is used, that is adjustable from 50kHz to 2MHz through an external resistor. This wide range of PWM frequencies gives the power supply designer the flexibility to make tradeoffs among component size, cost, noise and efficiency. The power MOSFETs can run on a separate 1V to 16V (Input Voltage, VIN) (Note 2) rail while the regulator is biased from a 3V to 6V (IC Input Voltage, VCC), 2mA rail. A power-good flag, precision shutdown threshold and soft start features make power supply tracking and sequencing easy. The LM2743 employs output under-voltage and over-voltage flag, and current limit. Current limit is achieved by monitoring the voltage drop across the on resistance of the low-side MOSFET. The adaptive non-overlapping MOSFET gate drivers help avoid potential shoot-through problems while maintaining high efficiency. Both high-side and low-side MOSFETs are the lower cost N-Channel type, and the IC can accept a bootstrap structure to saturate the high-side MOSFET for highest efficiency. MOSFET input voltage (VIN) from 1V to 16V (Note 2) IC input voltage (VCC) from 3V to 6V Output voltage adjustable down to 0.6V Power good flag and output enable Output over-voltage and under-voltage flag FB voltage: 2% over temperature Current limit without series sense resistor Adjustable soft start Tracking and sequencing with shutdown and soft start pins n Switching frequency from 50 kHz to 2 MHz n TSSOP-14 package n n n n n n n n n Applications n n n n 3.3V Buck Regulation Set-Top Boxes/ Home Gateways Core Logic Regulators High-Efficiency Buck Regulation Typical Application 20095201 © 2004 National Semiconductor Corporation DS200952 www.national.com LM2743 N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V April 2004 LM2743 Connection Diagram 20095202 14-Lead Plastic TSSOP θJA = 155˚C/W NS Package Number MTC14 SS (Pin 9) - Soft start and track pin. A 10 µA current is sourced from this pin. This pin is connected to the noninverting input of the error amplifier during soft start, or any time the voltage is below the reference. To track power supplies connect a resistor divider (smaller than 10kΩ for better precision) from the output of the master supply directly to the SS pin. To limit the inrush current of a single power supply, place a capacitor to ground (see Application Information/Start Up for appropriate capacitance value). This pin should not be forced before SD or VCC (above the UVLO). FB (Pin 10) - This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control loop. The FB current is negligible. FREQ (Pin 11) - The switching frequency (FOSC) is set by connecting a resistor (RFADJ) between this pin and ground. SD (Pin 12) - IC shutdown pin. To assure proper IC start-up the SD pin should not be left floating. When this pin is pulled low the chip turns both, high and low, sides off. While this pin is low, the IC will not start up. This pin features a precision threshold for power supply sequencing, as well as a lower threshold to ensure minimal quiescent current. HG (Pin 14) - Gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG (Pin 2) to avoid a shoot-through problem. Pin Description BOOT (Pin 1) - Supply rail for the N-channel MOSFET gate drive. The voltage should be at least one gate threshold (VGS(th)) above the regulator input voltage (VIN) to properly turn on the high-side FET. LG (Pin 2) - Gate drive for the low-side N-channel MOSFET. This signal is interlocked with HG (Pin 14) to avoid a shootthrough problem. PGND (Pins 3, 13) - Ground for low-side FET drive circuitry. Connect to system ground. SGND (Pin 4) - Ground for signal level circuitry. Connect to system ground. VCC (Pin 5) Supply rail for the controller. PWGD (Pin 6) - Power good pin. This is an open drain output. The pin is pulled low when the chip is in undervoltage flag (UVF), over-voltage flag (OVF), or UVLO mode. During normal operation, this pin is connected to VCC or other low voltage source through a pull-up resistor (RPULLUP). ISEN (Pin 7) - Current limit threshold setting. This sources a fixed 40µA current. A resistor of appropriate value should be connected between this pin and the drain of the low-side FET. EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop. www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Lead Temperature (soldering, 10sec) 260˚C Infrared or Convection (20sec) 235˚C ESD Rating (Note 3) 2 kV 7V VCC BOOT Voltage 21V All other pins Operating Ratings VCC + 0.3V Junction Temperature 150˚C Storage Temperature −65˚C to 150˚C IC Input Voltage (VCC) 3V to 6V Junction Temperature Range −40˚C to +125˚C Thermal Resistance (θJA) Soldering Information 155˚C/W Electrical Characteristics VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= +25˚C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter VFB FB Pin Voltage VON UVLO Thresholds Min Typ Max VCC = 3.3V Conditions 0.612 0.6 0.588 VCC = 5V 0.612 0.6 0.588 Rising Falling 2.76 2.42 1 1.5 2.1 VCC = 5V, SD = 3.3V Fsw = 600kHz 1 1.7 2.1 Shutdown VCC Current (Note 4) VCC = 3.3V, SD = 0V 0 110 185 tPWGD1 PWGD Pin Response Time FB Voltage Going Up 6 tPWGD2 PWGD Pin Response Time FB Voltage Going Down 6 ISS-ON SS Pin Source Current SS Voltage = 0V ISS-OC SS Pin Sink Current During Over SS Voltage = 0V Current Operating VCC Current ISEN-TH ISEN Pin Source Current Trip Point V V VCC = 3.3V, SD = 3.3V Fsw = 600kHz IQ_VCC Units mA 7 10 µs µs 14 90 25 40 µA µA µA 55 µA ERROR AMPLIFIER GBW G Error Amplifier Unity Gain Bandwidth 9 MHz Error Amplifier DC Gain 106 dB SR Error Amplifier Slew Rate 3.2 V/µs IEAO EAO Pin Current Sourcing and Sinking Capability VEAO = 1.5, FB = 0.55V VEAO = 1.5, FB = 0.65V 2.6 9.2 mA VEA Error Amplifier Maximum Swing Minimum Maximum 0 2 V 3 www.national.com LM2743 Absolute Maximum Ratings (Note 1) LM2743 Electrical Characteristics (Continued) VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= +25˚C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max Units 18 90 µA GATE DRIVE IQ-BOOT BOOT Pin Quiescent Current RDS1 Top FET Driver Pull-Up ON resistance RDS2 Top FET Driver Pull-Down ON resistance RDS3 Bottom FET Driver Pull-Up ON resistance RDS4 Bottom FET Driver Pull-Down ON resistance BOOTV = 12V, EN = 0 3 Ω 2 Ω 3 Ω 2 Ω BOOT-SW = 5V@350mA OSCILLATOR FOSC D PWM Frequency Max Duty Cycle RFADJ = 813.2kΩ 50 RFADJ = 117.6kΩ 300 RFADJ = 54.4kΩ 475 600 RFADJ = 18.8kΩ 1400 RFADJ = 10.8kΩ 2000 fPWM = 300kHz fPWM = 600kHz 90 85 725 kHz % LOGIC INPUTS AND OUTPUTS VSTBY-IH Standby High Trip Point FB = 0.575V, BOOTV = 3.3V, EN = 0V to 3.3V VSTBY-IL Standby Low Trip Point FB = 0.575V, BOOTV = 3.3V, EN = 3.3V to 0V VSD-IH SD Pin Logic High Trip Point FB = 0.575V, BOOTV = 3.3V, EN = 0V to 3.3V VSD-IL SD Pin Logic Low Trip Point FB = 0.575V, BOOTV = 3.3V, EN = 3.3V to 0V VPWGD-TH-LO PWGD Pin Trip Points VPWGD-TH-HI PWGD Pin Trip Points VPWGD-HYS PWGD Hysteresis FB Voltage Going Down FB Voltage Going Up 0.756 0.232 1.1 0.562 1 V V 1.3 V 0.8 1.1 FB Voltage Going Down 0.408 0.434 0.457 V FB Voltage Going Up 0.677 0.710 0.742 V 60 90 V mV Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device operates correctly. Opearting Ratings do not imply guaranteed performance limits. Note 2: The power MOSFETs can run on a separate 1V to 16V rail (Input voltage, VIN). Low range of VIN greatly depends on selection of the external MOSFET. Note 3: The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Note 4: Shutdown VCC current goes to zero amps after 20 seconds. www.national.com 4 LM2743 Typical Performance Characteristics Efficiency (VOUT = 2.5V) VCC = 3.3V, FSW = 300kHz Efficiency (VOUT = 1.2V) VCC = 3.3V, FSW = 300kHz 20095240 20095257 Efficiency (VOUT = 3.3V) VCC = 5V, FSW = 300kHz VCC Operating Current vs Temperature 20095241 20095261 BOOT Pin Current vs Temperature for BOOT Voltage = 3.3V FSW = 300kHz, FDS689A FET, No-Load VCC Operating Current plus BOOT Current vs Frequency FDS689A FET (TA = 25˚C) 20095242 20095245 5 www.national.com LM2743 Typical Performance Characteristics (Continued) BOOT Pin Current vs Temperature for BOOT Voltage = 12V FSW = 300kHz, FDS689A FET, No-Load BOOT Pin Current vs Temperature for BOOT Voltage = 5V FSW = 300kHz, FDS689A FET, No-Load 20095244 20095243 RFADJ vs Frequency 50kHz to 2MHz, TA = 25˚C Internal Reference Voltage vs Temperature 20095259 20095258 Frequency vs Temperature Output Voltage vs Output Current 20095260 20095256 www.national.com 6 (Continued) Switch Waveforms (HG Falling) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, FSW = 300kHz Switch Waveforms (HG Rising) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, FSW = 300kHz 20095247 20095246 Start-Up (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, FSW = 300kHz Start-Up (No-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, FSW = 300kHz 20095248 20095249 Load Transient Response (IOUT = 0A to 4A) VCC = 3.3V, VIN = 5V, VOUT = 1.2V CSS = 12nF, FSW = 300kHz Shutdown (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, FSW = 300kHz 20095250 20095251 7 www.national.com LM2743 Typical Performance Characteristics LM2743 Typical Performance Characteristics (Continued) Load Transient Response VCC = 3.3V, VIN = 5V, VOUT = 1.2V CSS = 12nF, FSW = 300kHz Load Transient Response (IOUT = 4A to 0A) VCC = 3.3V, VIN = 5V, VOUT = 1.2V CSS = 12nF, FSW = 300kHz 20095252 20095253 Line Transient Response (VIN = 6V to 3V) VCC = 3.3V, VOUT = 1.2V IOUT = 2A, FSW = 300kHz Line Transient Response (VIN = 3V to 6V) VCC = 3.3V, VOUT = 1.2V IOUT = 2A, FSW = 300kHz 20095254 www.national.com 20095255 8 LM2743 Block Diagram 20095203 Application Information THEORY OF OPERATION The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck converters. It has power good (PWGD) flag, output shutdown (SD), UVLO mode, and over-voltage flag (OVF) and under- voltage flag (UVF) features. The over-voltage and under-voltage signals are OR gated to drive the power good signal. If this signal is pulled low, the high side is off and low side if on, but only if the duty cycle is less then maximum. Current limit is achieved by sensing the voltage VDS across the low side FET. During current limit the high side gate is turned off and the low side gate is turned on. A 90µA source discharges the soft start capacitor (reducing max. duty cycle) until the current is under control. During soft start the power good flag is forced low and it is released when the voltage reaches a set value as shown in Figure 1. At this point the chip enters normal operation mode, the power good flag is released, and the OVF and UVF functions begin to monitor VOUT. START UP When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the internal fixed 10µA source begins charging the soft start capacitor. During this time the output of the error amplifier is allowed to rise with the voltage of the soft start capacitor. This capacitor, CSS, determines soft start time, and can be calculated approximately by: 9 www.national.com LM2743 Application Information (Continued) 20095206 FIGURE 2. SD Pin Logic The LM2743 is also adequate for tracking purposes through the SS/TRACK pin. The tracking circuit, in the design examples below, contains a Master Power Supply with VOUT1 = 5V and an LM2743 with VOUT2=1.8V. Three cases are described: 1. Both output voltages, VOUT1 and VOUT2, rise together, reaching their final values at the same time, 2. Both output voltages rise together at the same rate until VOUT2 = 1.8V, and finally 3. Output voltage VOUT2 starts rising 3.24ms after VOUT1 starts. The calculation of the feedback resistors Figure 3 for all cases is based on the Tracking Equation. Since VFB=0.6V, VOUT2=1.8V, and RFB2=10kΩ, then the RFB1 becomes 5kΩ. 20095204 FIGURE 1. Start-Up Behavior NORMAL OPERATION While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the high side and low side FETs. The equation governing output voltage is: Case 1: Rise together Both, VOUT1 and VOUT2, start rising, and reach their nominal values at the same time as shown in Figure 4. This means that VOUT2 rises at slower rate then VOUT1. The PWM frequency is adjustable between 50kHz and 2MHz and is set by an external resistor, RFADJ, between the FREQ pin and ground. The resistance needed for a desired frequency is approximately: where a2 = 0.206375, a1 = 3.691525, a0 = (-0.076875) are the coefficients, FOSC is the frequency in Hz, and RFADJ is the resistance in kΩ. SS/TRACK When the LM2743 is used for sequencing purposes, some care has to be taken. Once the shutdown voltage goes above VSTBY-IH, a 17µA pull-up current is activated as shown in Figure 2. This current is used to create an internal hysteresis (170mV); however, high external impedances will affect the SD pin level as well. The external impedance must be lower than 10kΩ to work properly without glitching the quiescent current of the chip. In that scenario the SS current will turn on and off during the glitching or most likely no switching will occur at all, due to the SS voltage being very low. 20095207 FIGURE 3. Block Diagram of Case 1 VSS = VOUT1 *(R3/(R3+R4)) www.national.com 10 Since VSS LM2743 Application Information (Continued) VFB = VOUT2 *(RFB2/(RFB1+RFB2)) = VFB=0.6V, then Tracking Equation The total value of the track resistor divider (Figure 3), R3 and R4, should be set below 10kΩ for better precision. Let R4=1K, for VOUT1= 5V and VOUT2=1.8V, R3=136Ω. 20095210 FIGURE 6. Timing Behavior of Case 2 Case 3: VOUT2 starts rising 3.0ms after VOUT1 Assuming VOUT1 slew rate SRVSD = 1V/ms and voltage divider ratio 1:3 (R3 = 500Ω and R4 = 1kΩ), the VSD slew rate equals SRVSD = 0.333V/ms. During the delay time VSD raises to 1.0V (VSD-IH) as shown in Figure 8. The delay time is calculated from : tDELAY = VSD-IH /SRVSD tDELAY= 1.0(V) / 0.333(V/ms) = 3.0ms 20095208 FIGURE 4. Timing Behavior of Case 1 Case 2: Rise together until VOUT2=1.8V 20095214 FIGURE 7. Block Diagram of Case 3 20095209 FIGURE 5. Block Diagram of Case 2 VSS = VFB= 0.6V, VOUT1 = VOUT2 = 1.8V For R4=1kΩ, R3=500Ω (from Tracking Equation). The soft start reaches 0.6V at VOUT1 equal 1.8V. For VOUT1 > 1.8V, VOUT2 stays in regulation at 1.8V. 11 www.national.com LM2743 Application Information (Continued) 20095212 FIGURE 9. Bootstrap Configuration 1 20095211 This means that if VCC is 3.0V, the gate drive for the FETs is approximately 2.5V. This voltage could be too low to fully turn the FET on. As a result I2R losses could be higher than expected. In the next bootstrap configuration (Figure 10) the voltage applied to the high side FET is VCC - 2VD and to the low side FET is VCC - 2VD + VIN. FIGURE 8. Timing Behavior of Case 3 If the tracking through SS/TRACK pin is not used, a capacitor to ground is needed to limit the inrush current. MOSFET GATE DRIVERS The LM2743 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power for the drivers is supplied through the BOOT pin. For the high side gate (HG), to fully turn the top FET on, the BOOT voltage must be at least one VGS(th) greater than VIN (VBOOT ≥ 2V + VIN). This voltage can be supplied from a separate voltage source or from a local charge pump structure, the bootstrap. A charge pump can be built using a diodes and small capacitors, as shown in the below figures. The capacitor serves to maintain enough voltage between the top FET gate and source to control the device even when the top FET is on and its source has risen up to the input voltage level. The LM2743 gate drives use a BiCMOS design. Unlike some other bipolar control ICs, the gate drivers have rail-to-rail swing, ensuring no spurious turn-on due to capacitive coupling. The LM2743 can operate its internal circuitry at the VCC range from 3.0V to 6.0V. However, the external FETs may operate more efficiently with higher gate drive voltage. Figure 9 shows a typical bootstrap method where the voltage applied to the FETs is VCC - VD. 20095213 FIGURE 10. Bootstrap Configuration 2 If VCC and VIN are both 3.0V, then 5V is developed at BOOT pin and the low side FET can be driven fully on. The high side FET however may have difficulty turning on since the applied gate drive is only 2V in this case. The Figure 11 shows next example of bootstrap configuration. In this case the low gate drive voltage on the top FET is resolved. Now the gate drive on both, the low and high, side FETs is VCC - 3VD + VIN. www.national.com 12 VDS and if the latter is higher, the current limit of the chip has been reached. The RCS can be found by using the following: (Continued) where resistance RDS(ON) is taken from MOSFET’s datasheet (RDS(ON LOW) =13mΩ) and current limit (ILIM) value is calculated from equation. where: L is the inductance and FOSC is the PWM frequency. Because current sensing is done across the low side FET, no minimum high side on-time is necessary. In the current limit mode the LM2743 will turn the high side off and the keep low side on for a time as long as necessary. The chip also discharges the soft start capacitor through a fixed 90µA source. This way, smooth ramping up of the output voltage as with a normal soft start is ensured. The output of the LM2743 internal error amplifier is limited by the voltage on the soft start capacitor. Hence, discharging the soft start capacitor reduces the maximum duty cycle (D) of the controller. During severe current limit, this reduction in duty cycle will reduce the output voltage if the current limit conditions last for an extended period of time. 20095219 FIGURE 11. Bootstrap Configuration 3 At an input voltage of 3V both, the high and low, side FETs are driven with about 4.5V. The decision on which configuration to use depends on the desired output current and operating frequency. At high currents and low frequencies, configuration 3 (Figure 11) is recommended. For low currents and high frequencies, configuration 1 (Figure 9) may work well. UVF/OVF The output under-voltage flag (UVF) and over-voltage flag (OVF) mechanisms engage at about 70% and 118% of the target output voltage, respectively. In the UVF case, the LM2743 will turn off the high side switch and turn on the low side switch and dischrage the soft start capacitor through the MOSFET switch. However, in the OVF the converter goes to maximum duty cycle and the high and low sides are still switching. The chip remains in this state until the shutdown pin has been pulled to a logic low and then released. The UVF function is masked only during the initial charge of the soft start capacitor, when voltage is first applied to the VCC pin. The power good flag goes low during this time, giving a logic-level warning signal. POWER GOOD SIGNAL The power good signal is the OR-gated flag representing over-voltage and under-voltage conditions. If the feedback pin (FB) voltage is about 18% over its nominal value (VPWGDTH-HI = 0.710V) or falls about 30% below its nominal value (VPWGD-TH-LO = 0.434V) the power good flag goes low. At about 118% of VFB the converter turns off the high side gate and turns on the low side gate. However, at about 70% of VFB the converter goes to maximum duty cycle and the high and low sides are still switching. The power good flag will return to logic high whenever the feedback pin voltage is between 70% and 118% of 0.6V. SHUT DOWN To assure proper IC start-up, shutdown pin (SD) should not be left floating. For Normal Operation this pin should be connected to VCC or other low voltage source (see Electrical Characteristics table). If the shutdown pin SD is pulled low, the LM2743 discharges the soft start capacitor through a MOSFET switch. The high and the low side switches are turned off. The LM2743 remains in this state until SD is released. UVLO The 2.76V turn-on threshold on VCC has a built in hysteresis of 400mV. Therefore, if VCC drops below 2.42V, the chip enters UVLO mode. UVLO consists of turning off the top and bottom FETs, and remaining in that condition until VCC rises above 2.76V. As with shutdown, the soft start capacitor is discharged through a FET, ensuring that the next start-up will be smooth. CURRENT LIMIT Current limit is realized by sensing the voltage across the low side FET while it is on. The RDS(ON) of the FET is a known value, and the voltage across the FET can be found from: VDS = IDS * RDS(ON) The current limit is determined by an external resistor, RCS, connected between the switch node and the ISEN pin. A constant current of 40µA is forced through RCS, causing a fixed voltage drop. This fixed voltage is compared against DESIGN CONSIDERATIONS The following is a design procedure for all the components needed to create the Typical Application Circuit. The designed 3.3V (VCC) to 1.2V (VOUT) converter is capable of delivering 4A with an efficiency of 89% at switching frequency of 300kHz. The same procedures can be followed to create many other designs with varies input and output voltages, and load current. 13 www.national.com LM2743 Application Information LM2743 Application Information CSS - the soft start capacitor depends on the user requirements and is calculated based on the equation from the Start Up section. For a 7ms delay, a 12nF capacitor will be suitable. (Continued) Input Capacitor The input capacitors in a Buck switching converter are subjected to high stress due to the input current square waveform. Hence input capacitors are selected for their ripple current capability and their ability to withstand the heat generated as that ripple current runs through their ESR. Input rms ripple current is approximately: Output Inductor The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the square wave created by the switching action and for controlling the output current ripple (∆IOUT). The inductance is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the more quickly the converter can respond to transients in the load current. However, as shown in the efficiency calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current ripple. An increase in frequency can mean increasing loss in the FETs due to the charging and discharging of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The equation for output inductor selection is: where D is the duty cycle. The power dissipated by each input capacitor is: where, n is the number of capacitors, and ESR is the equivalent series resistance of CIN1. The equation indicates that power loss in each capacitor decreases rapidly as the number of input capacitors increases. The worst-case ripple for a Buck converter occurs during full load and when the duty cycle (D) is 0.5. For design 3.3V (VCC) to 1.2V (VOUT) the duty cycle is 0.364. With a 4A maximum load the ripple current is around 2A. The Sanyo 20SP120M aluminum electrolytic capacitor works fine here. It has a ripple current rating of 3A and maximum ESR of 24mΩ at 100kHz. The power dissipated by the Sanyo’s capacitor is then 0.088W. Other options for input and output capacitors include MLCC, Tantalum, OSCON, SP, and POSCAPS. L = 16µH Plugging in the values for output current ripple, input voltage, output voltage, switching frequency, and assuming a 40% peak-to-peak output current ripple yields an inductance of 1.6µH. The output inductor must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + 0.5*∆IOUT) 4.8A for a 4A design. The Coilcraft DO3316P222P is 2.2µH, is rated to 7.4A rms, and has a direct current resistance (DCRIOUT) of 11mΩ. Support Components: Capacitors (CIN2, CCC, CBOOT, CSS), Resistors (RCC, RCS, RFADJ, RPULL-UP), and Schottky Diode (D1) CIN2 - the MOSFET’s input capacitor is high frequency bypass device designed to filter harmonics of the switching frequency and input noise. 0.1µF - 1µF ceramic capacitor with a sufficient voltage rating will work well in almost any case. RCC, CCC, and CBOOT - bypass resistor and bypass capacitors are standard filter components designed to ensure smooth DC voltage for the chip supply and for the bootstrap structure, if it is used. Recommended values: RCC= 10Ω, CCC= 0.1µF, and CBOOT = 0.1µF. RPULL-UP – this is a standard pull-up resistor for the opendrain power good signal (PWGD). The recommended value: 100Ω: connected to VCC. If this feature is not necessary, the resistor can be omitted. D1 - Schottky diode should be used for the bootstrap. It allows the minimum drop for both, high and low side drivers. The MBR0520 works well here. RCS - resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT+0.5*∆IOUT) of 4.8A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is 7.8 A.) Following the equation from the Current Limit section, use a 1.5kΩ resistor. RFADJ - this resistor is used to set the switching frequency (FOSC) of the chip. The resistor value is calculated from equation in Normal Operation section. To obtain the switching frequency of 300kHz, 110kΩ, 1% resistor is needed. www.national.com Output Capacitor The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control the output voltage ripple (∆VOUT) and to supply load current during fast load transients. In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the switching frequency. The large capacitance means that at switching frequency, the ESR is dominant, hence the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the maximum ESR based on the desired output voltage ripple, ∆VOUT and the designed output current ripple, ∆IOUT, is: 14 PSW = 0.5 x 3.3V x 4A x 300kHz x 31ns PSW = 61.38mW The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15ns and 16ns, respectively. The switching losses for this type of dual N-Channel MOSFETs are 0.061W. FET Conduction Loss (PCND) PCND = PCND1 + PCND2 PCND1 = I2OUT x RDS(ON) x k x D PCND2 = I2OUT x RDS(ON) x k x (1-D) RDS(ON) = 13mΩ and the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to heating. PCND1 = (4A)2 x 13mΩ x 1.3 x 0.364 PCND2 = (4A)2 x 13mΩ x 1.3 x (1 - 0.364) (Continued) In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor current ripple, the required maximum ESR is 15mΩ.The Sanyo 4SP560M aluminum electrolytic capacitor will give an equivalent ESR of 14mΩ. The capacitance of 560µF is enough to supply even severe load transients. MOSFETs MOSFETs are the critical parts of any switching controller. Both, the control high side FET and the synchronous low side FET, have a direct impact on the system efficiency. In this case the target efficiency for typical application circuit is about 89%. This variable will determine which MOSFET is acceptable to use for the design. Loss from the capacitors, inductors, and IC come to about 0.27W. This leaves about 0.33W for the FET switching, conduction, and gate charging losses to meet the target efficiency. All the losses are detailed in the Efficiency section. The switching loss is particularly difficult to estimate because it depends on many factors. When the load current is more than about 1 or 2 amps, conduction losses outweigh the switching and gate charging losses. This allows FET selection based on the RDS(ON) of the FET. After adding the FET switching and gate charging losses about 0.27W leaves for conduction losses. When plugged MOSFET, the FDS6898A with a typical RDS(ON) of 13mΩ, into the equation from Efficiency section for PCND the loss come to be about 0.27W. PCND = 98.42mW + 172mW = 270mW There are few additional losses that are taken into account: IC Operating Loss (PIC) PIC = IQ_VCC x VCC, where IQ-VCC is the typical operating VCC current PIC= 1.5mA *3.3V = 4.95mW FET Gate Charging Loss (PGATE) PGATE = n * VCC * QGS * FOSC PGATE = 2 x 3.3V x 3nC x 300kHz PGATE = 5.94mW The value n is the total number of FETs used and QGS is the typical gate-source charge value, which is 3nC. For the FDS6898A the gate charging loss is 5.94mW. Input Capacitor Loss (PCAP) Control Loop Components The Typical Application Circuit has been compensated to improve the DC gain and bandwidth. The result of this compensation is better line and load transient responses. For the LM2743, the top feedback divider resistor, RFB2, is also a part of the compensation. For the 3.3V to 1.2V at 4A design, the values are: CC1 = 27pF, CC2 = 1200nF, CC3 = 3300pF, RC1 = 40.2kΩ, RC2 = 2.55kΩ, RFB2 = 10kΩ. These values give a phase margin of 53˚ and a bandwidth of 80kHz. Where, n is the number of capacitors, and ESR is equivalent series resistance. EFFICIENCY CALCULATIONS A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the Output Power (POUT) loss and the Total Power (PTOTAL) loss: PCAP = 88.8mW Output Inductor Loss (PIND) PIND = I2OUT * DCRIOUT, where DCRIOUT is the direct current resistance PIND = (4A)2 x 11mΩ PIND = 176mW Total System Efficiency The Output Power (POUT) for theTypical Application Circuit design is (1.2V * 4A) = 4.8W. The Total Power (PTOTAL), with an efficiency calculation to complement the design, is shown below. The majority of the power losses are due to low and high side of MOSFET’s losses. The losses in any MOSFET are group of switching (PSW) and conduction losses(PCND). PFET = PSW + PCND = 61.38mW + 270mW PFET = 331.4mW FET Switching Loss (PSW) PSW = PSW(ON) + PSW(OFF) PSW = 0.5 * VCC * IOUT * (tr + tf)* FOSC 15 www.national.com LM2743 Application Information LM2743 Example Circuits 20095232 FIGURE 12. 3.3V to 1.8V @ 2A, FSW = 300kHz PART PART NUMBER TYPE PACKAGE U1 LM2743 Synchronous Controller TSSOP-14 Q1 FDS6898A Dual N-MOSFET SO-8 SOD-123 DESCRIPTION VENDOR NSC 20V, 10mΩ@ 4.5V, 16nC Fairchild D1 MBR0520LTI Schottky Diode L1 DO3316P-472 Inductor 4.7µH, 4.8Arms 18mΩ Coilcraft CIN1 16SP100M Aluminum Electrolytic 100µF, 16V, 2.89Arms Sanyo CO1 6SP220M Aluminum Electrolytic 220µF, 6.3V 3.1Arms Sanyo CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor 1206 0.1µF, 10% Vishay CC3 VJ805Y332KXXA Capacitor 805 3300pF, 10% Vishay CSS VJ0805Y123KXXA Capacitor 805 12nF, 10% Vishay CC2 VJ1805A821KXAA Capacitor 805 820pF 10% Vishay CC1 VJ0805A220KXAA Capacitor 805 22pF, 10% Vishay RFB2 CRCW08051002F Resistor 805 10.0kΩ 1% Vishay RFB1 CRCW08054991F Resistor 805 4.99kΩ1% Vishay RFADJ CRCW08051103F Resistor 805 110kΩ 1% Vishay RC2 CRCW08052101F Resistor 805 2.1kΩ 1% Vishay RCS CRCW08057500F Resistor 805 750Ω 1% Vishay RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay RC1 CRCW08055492F Resistor 805 54.9kΩ 1% Vishay RPULL-UP CRCW08051003J Resistor 805 100kΩ 5% Vishay www.national.com 16 LM2743 Example Circuits (Continued) 20095233 FIGURE 13. 5V to 2.5V @ 2A, FSW = 300kHz PART PART NUMBER TYPE PACKAGE U1 LM2743 Synchronous Controller TSSOP-14 Q1 FDS6898A Dual N-MOSFET SO-8 D1 MBR0520LTI Schottky Diode SOD-123 L1 DO3316P-682 CIN1 DESCRIPTION VENDOR NSC 20V, 10mΩ@ 4.5V, 16nC Fairchild Inductor 6.8µH, 4.4Arms, 27mΩ Coilcraft 16SP100M Aluminum Electrolytic 100µF, 16V, 2.89Arms Sanyo C O1 10SP56M Aluminum Electrolytic 56µF, 10V 1.7Arms Sanyo CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor 1206 0.1µF, 10% Vishay CC3 VJ0805A182KXAA Capacitor 805 1800pF, 10% Vishay CSS VJ0805Y123KXXA Capacitor 805 12nF, 10% Vishay CC2 VJ1805A821KXAA Capacitor 805 820pF 10% Vishay CC1 VJ0805A330KXAA Capacitor 805 33pF, 10% Vishay RFB2 CRCW08051002F Resistor 805 10.0kΩ 1% Vishay RFB1 CRCW08053161F Resistor 805 3.16kΩ 1% Vishay RFADJ CRCW08051103F Resistor 805 110kΩ 1% Vishay RC2 CRCW08051301F Resistor 805 1.3kΩ 1% Vishay RCS CRCW08057870F Resistor 805 787Ω 1% Vishay RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay RC1 CRCW08053322F Resistor 805 33.2kΩ 1% Vishay RPULL-UP CRCW08051003J Resistor 805 100kΩ 5% Vishay 17 www.national.com LM2743 Example Circuits (Continued) 20095234 FIGURE 14. 5V to 3.3V @ 4A, FSW = 300kHz PART PART NUMBER TYPE PACKAGE U1 LM2743 Synchronous Controller TSSOP-14 Q1 FDS6898A Dual N-MOSFET SO-8 D1 MBR0520LTI Schottky Diode SOD-123 L1 DO3316P-332 CIN1 16SP100M DESCRIPTION VENDOR NSC 20V, 10mΩ@ 4.5V, 16nC Fairchild Inductor 3.3µH, 5.4Arms 15mΩ Coilcraft Aluminum Electrolytic 100µF, 16V Sanyo 2.89Arms CO1 6SP220M Aluminum Electrolytic CCC, CBOOT, CIN2, CO2 VJ1206Y104KXXA Capacitor CC3 VJ805Y222KXXA CSS VJ0805Y123KXXA CC2 CC1 220µF, 6.3V 3.1Arms Sanyo 1206 0.1µF, 10% Vishay Capacitor 805 2200pF, 10% Vishay Capacitor 805 12nF, 10% Vishay VJ805Y332KXXA Capacitor 805 3300pF 10% Vishay VJ0805A820KXAA Capacitor 805 82pF, 10% Vishay RFB2 CRCW08051002F Resistor 805 10.0kΩ 1% Vishay RFB1 CRCW08052211F Resistor 805 2.21kΩ 1% Vishay RFADJ CRCW08051103F Resistor 805 110kΩ 1% Vishay RC2 CRCW08052611F Resistor 805 2.61kΩ 1% Vishay RCS CRCW08057870F Resistor 805 787Ω 1% Vishay RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay RC1 CRCW08051272F Resistor 805 12.7kΩ 1% Vishay RPULL-UP CRCW08051003J Resistor 805 100kΩ 5% Vishay www.national.com 18 LM2743 Evaluation Board Schematic 20095227 FIGURE 15. 3.3V to 1.2V @ 4A, FSW = 300kHz PART PART NUMBER TYPE PACKAGE U1 LM2743 Synchronous Controller TSSOP-14 Q1 FDS6898A Dual N-MOSFET SO-8 D1 MBR0520LTI Schottky Diode SOD-123 L1 DO3316P-222 J1 NOT USED C12 DESCRIPTION VENDOR NSC 20V, 10mΩ@ 4.5V, 16nC Fairchild Inductor 2.2µH, 6.1Arms 12mΩ Coilcraft 20SP120M Aluminum Electrolytic 120µF, 20V 3.1Arms Sanyo C16 4SP560M Aluminum Electrolytic 560µF, 4V 4Arms Sanyo C4,C5,C10, C13,C19 VJ1206Y104KXXA Capacitor 0.1µF, 10% Vishay C11 VJ805Y332KXXA Capacitor 805 3300pF 10% Vishay C7 VJ0805Y123KXXA Capacitor 805 12nF, 10% Vishay 1206 19 www.national.com LM2743 Evaluation Board Schematic (Continued) PART PART NUMBER TYPE PACKAGE DESCRIPTION C8 VJ1206Y122KXXA Capacitor 1206 1200pF 10% Vishay C9 VJ0805A270KXAA Capacitor 805 27pF, 10% Vishay C1, C2, C3, C6, C14, C15, C17, C18, C20 NOT USED R6 CRCW08051002F Resistor 805 10.0kΩ 1% Vishay R7 CRCW08051002F Resistor 805 10.0kΩ1% Vishay R2 CRCW08051103F Resistor 805 110kΩ 1% Vishay R5 CRCW08052551F Resistor 805 2.55kΩ 1% Vishay R4 CRCW08051501F Resistor 805 1.50kΩ 1% Vishay R1 CRCW080510R0F Resistor 805 10.0Ω 1% Vishay R3 CRCW08054022F Resistor 805 40.2kΩ 1% Vishay R11 CRCW08050R00F Resistor 805 0Ω 1% Vishay R8 CRCW08051003J Resistor 805 100kΩ 5% Vishay PCB Layout for the Evaluation Board 20095236 Top Silkscreen www.national.com 20 VENDOR LM2743 PCB Layout for the Evaluation Board (Continued) 20095237 Top Copper 20095238 Bottom Silkscreen 21 www.national.com LM2743 PCB Layout for the Evaluation Board (Continued) 20095239 Bottom Copper www.national.com 22 inches (millimeters) unless otherwise noted TSSOP-14 Pin Package NS Package Number MTC14 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. LM2743 N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V Physical Dimensions