LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION maximizing regulator response. A true differential input amplifier is used for remote voltage sensing at the processor core. A VID code generator provides an internal reference that will set the output voltage. This VID code can be changed during operation and the reference will slew the output voltage to its new setting at a preset rate. During VID changes on the fly the Power Good indication will stay valid. The current through the lower phase 1 MOSFET will be sampled using its RDS(ON) for current limit and shut down. For further protection, an over voltage circuit will trip at a specified setting and clamp the output by turning off the upper MOSFETs and turning on the lower MOSFETs. The upper MOSFET drivers use a bootstrap capacitor to provide the upper drive voltage over the input voltage range of 6 to 24 volts. IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com † Protected By US Patents: US6292378,US6285571 ‡ Protected By US Patents: US6825571, US6356063, US6605931 High Current Biphase Operation Outputs As Low As 0.800V † Biphase LoadSHARETM ‡ Transient Correction Loop™ Reduces Required Capacitance Differential Amplifier For Remote Voltage Sensing Integrated High Current MOSFET Drivers 200KHz to 1MHz Frequency Operation Programmable Slew Rate Control For Start-Up Sequence and VID change VID Changes On The Fly Power Good Indicator Short Circuit Protection Output Over Voltage and Under Voltage Protection No current-sense resistors WWW . Microsemi .C OM The LX1677 is a highly integrated VRM power supply controller IC featuring two PWM switching regulator stages. The two constant frequency voltage-mode PWM phases are configured as a single biphase high current output core supply. In biphase operation, the high current (>35A) output is generated by a LoadSHARETM† technique that balances the currents in the two phases. Power loss and noise, due to the ESR of the input capacitors, are minimized by operating the PWMs 180° out of phase. A synchronized Transient Correction Loop† provides exceptional control of the output droop and overshoot during very high di/dt load changes, the circuit can be configured for droop only, overshoot only or both. This architecture also minimizes capacitor requirements while APPLICATIONS AMD Athlon 64™ and AMD Opteron™ Processors Processor Core Voltage Supply Voltage Regulator Modules PRODUCT HIGHLIGHT T r a n s ie n t C o r e c tio n L o o p V in + 5 V V in 6 to 2 4 V 70nH LX1677 5 B it V ID V in 6 to 2 4 V Vout LX1677 PACKAGE ORDER INFO PW TJ (°C) 0 to 70 Plastic TSSOP 38-Pin LQ Plastic MLPQ 38-Pin RoHS Compliant / Pb-free Transition DC: 0518 RoHS Compliant / Pb-free Transition DC: 0512 LX1677CPW LX1677CLQ Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1677CLQ-TR) Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET FBDFOUT EO1 EA1DACOUT PWGD GND VIN ROSC ENA VID4 VID3 1 38 37 36 35 34 33 ILIM3 32 31 2 30 3 29 4 28 5 27 Connect Bottom to Power GND 6 7 26 25 8 24 9 23 10 22 11 12 21 13 14 15 16 17 18 19 20 VS3 I-MAX VC3 VC1 HO1 VS1 LO1 PGN LO2 VCCL I-MIN PGN3 WWW . Microsemi .C OM Supply Input Voltage (VCCL, VCC)................................................-0.3V to 6.0V Battery Input Voltage (VIN) ..............................................................-0.3V to 24V Current Limit Sense (ILIM1, ILIM3) ................................................-0.3V to 30V Topside Driver Supply Input Voltage (VC1, VC2, VC3)........ -0.3 to VSx + 6.0V Topside Driver Return Input Voltage (VS1, VS2)................................-5V to 24V Differential Sense Input Voltage (FB+, FB-)....................................-0.3V to 6.0V VID0 – VID4, Input Voltage ...............................................................-0.3V to 6V High Side Driver Peak (<500ns) Current (HO1/2, I-MAX) ............................+1A Low Side Driver Peak (<500ns) Sink Current (LO1/2, I-MIN)....................+1.5A Operating Junction Temperature.................................................................. 150°C Storage Temperature Range...........................................................-65°C to 150°C Lead Temperature (Soldering 10 seconds) .................................................. 300°C RoHS Peak Package Solder Reflow Temperature (40 second maximum exposure) ..................................................... 260°C (+0, -5) FB+ EO2 EA2LP2 LP1 ILIM1 PACKAGE PIN OUT VID2 VID1 VID0 VS2 HO2 VC2 VCC ABSOLUTE MAXIMUM RATINGS LQ PACKAGE Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. x denotes respective pin designator 1, 2, or 3 THERMAL DATA LQ Plastic MLPQ 38-Pin THERMAL RESISTANCE-JUNCTION TO CASE, θJC THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA PW 8°C/W 35°C/W Plastic TSSOP 38-Pin THERMAL RESISTANCE-JUNCTION TO CASE, θJC THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 12.2°C/W 38°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. (Top View) EA2EO2 FB+ FBDFOUT EO1 EA1DACOUT PWGD GND VIN ROSC ENA VID4 VID3 VID2 VID1 VID0 VS2 1 38 19 20 LP2 LP1 ILIM1 ILIM3 VS3 I-MAX VC3 VC1 HO1 VS1 LO1 PGN LO2 VCCL I-MIN PGN3 VCC VC2 HO2 PW PACKAGE (Top View) RoHS / Pb-free 100% Matte Tin Lead Finish RECOMMENDED OPERATING CONDITIONS Symbol Min LX1677 Typ Max Units PACKAGE DATA Parameter ` IC Input Supply Voltage Battery Input Voltage Biphase Topside Driver Return Voltage Transient Correction Phase Driver Return Voltage Copyright © 2000 Rev 1.1, 2003-03-03 VCC VIN VS1, VS2 VS3 4.5 5.7 0 0 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 5.5 24.0 24.0 5.5 V V V V Page 2 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION Description FB+ Differential Amplifier Positive Input – Feedback from output FB- Differential Amplifier Negative Input – Feedback from output DFOUT EA1- Differential Amplifier Output Phase 1 Error Amplifier Negative Input EO1 Phase 1 Error Amplifier Output GND Analog Ground ROSC ENA DACOUT A resister to ground sets PWM frequency Enable Input – Logic Low disables all converter phases DAC Output voltage – 50uA bi-directional current source VID4 Digital Input for VID code – Has an internal pull-up resister VID3 Digital Input for VID code – Has an internal pull-up resister VID2 Digital Input for VID code – Has an internal pull-up resister VID1 Digital Input for VID code – Has an internal pull-up resister VID0 Digital Input for VID code – Has an internal pull-up resister PWGD WWW . Microsemi .C OM Name Power Good Output Pin – Open drain output pin for power good indication. High = Power Good VCC IC Supply Voltage. Nominal +5V VC3 Supply for transient correction phase upper MOSFET driver, bootstrap voltage PGN3 Power ground pin for Transient Correction Loop driver I-MIN Output Driver for lower Transient Correction Loop MOSFET VS3 Low side of upper driver for Transient Correction Loop – MOSFET Driver power return I-MAX Output Driver for upper Transient Correction Loop MOSFET ILIM3 Transient Correction Loop current sense – A resister sets an upper limit for over current detection and shut down. LP1 Phase 2 differential amplifier positive input, filtered feedback from phase 1 output EA2- Negative Input of phase 2 integrating amplifier EO2 Output of phase 2 integrating amplifier LP2 Phase 2 differential amplifier negative input, filtered feedback from phase 2 output VIN Battery Voltage Input. LO2 Driver Output for phase 2 lower MOSFET VS2 Low side of upper gate driver for phase 2. Driver Output for phase 2 upper MOSFET VC2 Supply for phase 2 upper MOSFET driver, bootstrap voltage PGN Power ground pin for current sensing of lower MOSFET RDS(ON) for phase 1. LO1 Driver Output for phase 1 lower MOSFET ILIM1 Over-Current Limit Set – A resister sets an upper limit for over current detection and shut down. VS1 Low side of upper gate driver for phase #1. HO1 Driver Output for phase 1 upper MOSFET VC1 VCCL Copyright © 2000 Rev 1.1, 2003-03-03 PACKAGE DATA HO2 Supply for phase 1 upper MOSFET driver, bootstrap voltage Voltage bus for the lower MOSFET drivers. Nominal +5V Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS Parameter ` Symbol Low Side Driver Operating Current High Side Driver Operating Current Unity Gain Bandwidth Output Voltage Swing Unity Gain Bandwidth Slew Rate 9 1 mA µA ENA = VCC, FB+ = FBENA = GND IQ(VCCL) ENA = VCC, FB+ = FB- 0.5 1 mA IQ(VCx) ENA = VCC, FB+ = FB- 2 4 mA 6 100 mV nA dB V VOS IEA1 Common Mode Voltage (VCM) = 1.4V VICM CMRR > 50dB IEA1 = 2mA IEA1 = -20µA VOS ADA CMRRDA RIN VCM VDFOUT(MAX) VDFOUT (MIN) UGBW SR -6 -100 60 0.8 70 2.5 4.0 0.15 20 0.5 V MHz VCM=1.4V -6 0.99 0.8V < VCM < 2.5V Measured at FB+ Input 1 65 30 0 VDFOUT = 0V IDFOUT = 2mA IEA1 = -20µA 6 1.01 3 5 4.0 0.2 10 5 mV V/V dB KΩ V mA V MHz V/µs OSCILLATOR Maximum Clock Frequency Minimum Clock Frequency Frequency Stability fMAX fMIN RPWM=10kΩ RPWM=50kΩ 0.9 150 1 200 4 1.1 220 MHz KHz % PWM OUTPUT Maximum Duty Cycle DCMAX Minimum Pulse Width Dead Time tPWM(MIN) Ramp Amplitude VRAMP During Transient Correction Switching Transient Correction Not Switching 3000pF Load 3000pF Load at 50% of VCCL VIN = 6V VIN = 12 VIN = 24V 100 50 40 50 60 80 0.70 1.40 2.80 200 % nS nS V PHASE 2 INTEGRATING AMPLIFIER Input Offset Voltage DC Open Loop Gain Output Voltage Swing Unity Gain Bandwidth Copyright © 2000 Rev 1.1, 2003-03-03 VOS VEO2(MAX) VEO2(MIN) UGBW VCM=1.4V -6 IEA2 = 2mA IEA2 = -20µA Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 6 70 4.0 0.15 20 0.5 mV dB V MHz Page 4 ELECTRICALS ` 5 Units DIFFERENTIAL AMPLIFIER Input Offset Voltage Gain Common Mode Rejection Ratio Input Resistance Input Common Mode Range Source / Sink Current ` 1 Max IQ(VCC) VEO1(MAX) VEO1(MIN) UGBW Output Voltage Swing ` LX1677 Typ ERROR AMPLIFIER: PHASE 1 Input Offset Voltage Input Bias Current DC Open Loop Gain Input Common Mode Range ` Min REGULATOR IC Supply Current ` Test Conditions WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONT) Parameter ` VOS ADA CMRRDA RB UGBW IHOx Lower MOSFET Driver Current ILOx LP1=LP2 -6 0.98 Common Mode Voltage = 0 to 2 V Units 1 60 180 4 6 1.02 mV V/V dB KΩ MHz 50 nS 50 nS VDFOUT Rising 3000pF Load 40 mV VDFOUT Falling 3000pF Load 40 mV CL = 3000pF, VCx - VSx = 5V 50 50 nS VHOx = 20mA, VCx - VSx = 5.0 V VHOx = -20mA, VCx - VSx = 5.0 V 4.8 VLOx = 20mA, VCCL - VPGN = 5.0 V VLOx = -20mA, VCCL - VPGN = 5.0 V VCx - VSx = 5.0 V, Load = 3300pf at <500nSec VCCL - PGN = 5.0 V, Load = 3300pf at <500nSec 4.8 IILIM1 tCSD(ILIM1) 4.9 0.1 4.9 0.1 V 0.2 V 0.2 1 A 1.5 A 44 200 50 400 60 500 µA nS 40 200 50 400 60 500 µA nS TRANSIENT CORRECTION LOOP OVER CURRENT PROTECTION IILIM3 tCSD(ILIM3) 1.5 0.3 100 V V KΩ 0.5 V ELECTRICALS ENABLE INPUT / VOLTAGE IDENTIFICATION (VID) Logic Low Threshold Hysteresis Pullup Resistance ` Max PHASE 1 OVER CURRENT PROTECTION Current Sense Bias Current Current Sense Delay ` tRISE tFALL High Side Driver Current Current Sense Bias Current Current Sense Delay ` LX1677 Typ OUTPUT DRIVERS Driver Rise Time Fall Time High Side Driver Voltage: [VHOx - VVSx] Drive High Drive Low Low Side Driver Voltage: [VLOx – VPGN] Drive High Drive Low ` Min TRANSIENT CONTROL LOOP Voltage Droop Sense Propagation Delay : FB+ and FB- to I-MAX Voltage Overshoot Sense Propagation Delay : FB+ and FB- to I-MIN Voltage Droop Sense Threshold Voltage Overshoot Sense Threshold ` Test Conditions PHASE 2 DIFFERENTIAL AMPLIFIER Input Offset Voltage Gain Common Mode Rejection Ratio Input Resistance Unity Gain Bandwidth ` Symbol WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. POWER GOOD Low Output Voltage Copyright © 2000 Rev 1.1, 2003-03-03 VPWGD IPWGD = -3mA Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONT) Parameter ` Test Conditions Min LX1677 Typ Max Units UVLO VCC VIN ` Symbol Threshold Hysteresis VCC Rising Threshold Hysteresis VIN Rising 4.2 0.3 V 5.5 0.3 OVER VOLTAGE PROTECTION Over Voltage Threshold ` UNDER VOLTAGE PROTECTION Under Voltage Threshold ` DAC DAC Output Voltage Positioning Offset - At No Load 1 ≤ VDACOUT ≤1.4 0.925 ≤ VDACOUT < 1 Initial DACOUT Accuracy High Side Driver Current IHOx Lower MOSFET Driver Current ILOx 1.85 V 0.725 V -20 mV 1 2 1.4 < VDACOUT ≤ 2 VCx - VSx = 5.0 V, Load = 3300pf at <500nSec VCCL - PGN = 5.0 V, Load = 3300pf at <500nSec VID Logic High Threshold VID Hysteresis 0.5 % 1 A 1.5 A 1.3 0.3 2 WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 70°C except where otherwise noted and the following test conditions: VCC = 5V, VCCL = 5V, VIN = 12V, Switching Frequency = 500KHz. V V VOLTAGE IDENTIFICATION (VID) CODE Copyright © 2000 Rev 1.1, 2003-03-03 VOUT (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VOUT (V) 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 ELECTRICALS VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Page 6 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM VCCL EO1 EA1 - WWW . Microsemi .C OM DFOUT I-MAX VC1 - 0° - HO1 R - VS1 + + FB - + Phase 1 Error Amp Diff Amp Q S I-MIN FB + LO1 I-MIN DACOUT PGOOD 50µA PGN Q R + 180° VC2 S DAC VID0 POR DACOUT - 30mV VID1 VID2 ILIM VS2 _ DACOUT UV S R S + 0.85 VID3 VID4 HO2 I-MAX _ OV + 2.35 LO2 Fault S gm Bandgap S VCC S UVLO VIN + PWGD - EO2 Phase 2 Integrating Amp EA2 - PGOOD 100K 90K DACOUT 90K LP1 IMAX + _ ROSC VCC VIN AMP FRQ OSC 0° 180° 35mV offset 35mV offset Phase 2 Differential Amp + _ - LP2 90K VCCL _IMIN 90K + PGN + VIN Bandgap VS3 GND ILIM ILIM3 ILIM1 Copyright © 2000 Rev 1.1, 2003-03-03 ELECTRICALS ENA ILIM PGN3 I-Min VS3 I-Max VC3 ENA Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET APPLICATION CIRCUITS 4700pF +5VP CR3 +5VP R3 61.9K C3 R8 R7 4.02K Q7 6 7 C10 10uF 25V 8 R9 45.3K VBAT R10 1.00K 9 10 11 R11 100K 12 32 ILIM3 34 35 33 ILIM LP1 LP2 EA2- 37 36 38 FB+ VC3 EA1- VC1 DACOUT HO1 LX1677 LQ PWRGD GND LO1 VIN PGN ROSC VCCL VID4 I-MIN VID3 CR4 19 18 17 16 15 14 13 R15 100K C13 4.7uF 6.3V C28 25 10uF 24 23 22 PGN3 C5 0.22 4.7uF 6.3V 21 C25 20 4.7uF 6.3V R6 25V VBAT C24 Q3 IRLR8203 Q10 N/U +5VP C8 4.7uF 6.3V C16 10uF 25V C22 10uF 25V Q11 IRLR8203 Q4 IRLR8203 L1 2.2uH VCORE + C18 270uF 2V + C19 270uF 2V RTN C29 +5VP CR5 +5VP C14 1N5817 6.3V VBAT 10uF Q5 IRLR8203 C6 Q12 N/U Q6 IRLR8203 VBAT C17 10uF 25V C23 10uF 25V L2 0.22 Q13 IRLR8203 Enable VID 0 VID 0 VID 0 VID 0 VID 0 PWRGD C30 10uF 25V 25V 4.7uF R22 1.00K R23 1.00K +5VP 1N5817 26 10.0 C7 4.7uF 6.3V R14 100K C36 10uF 25V 28 27 R12 100K R13 100K C15 10uF 25V BATT RTN 29 LO2 ENA VBAT +BATT IN CR2 SK32 30 VS1 VCC 5 NDS7002A EO1 VC2 4 70nH 31 VS3 L3 0.22 Q2 SI4842DY I-MAX HO2 3 4700pF DFOUT VS2 C9 FB- VID0 2 VID1 0.22uF VID2 C26 Q8 EO2 U1 1 NDS7002A C4 C12 47uF 6.3V +5 RTN C11 47uF 6.3V CR1 SK32 6.04K R4 4.02K R5 +5VP 10K R19 Q1 SI4842DY 4700pF 2.00K R1 100K +5 VIN 1N5817 C1 4700pF WWW . Microsemi .C OM R2 61.9K C2 2.2uH + C20 270uF 2V + C21 270uF 2V VBAT C31 10uF 25V C32 10uF 25V C33 10uF 25V C34 10uF 25V C35 10uF 25V Figure 2 – Typical VRM Application APPLICATIONS Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1677 TM ® AMD64 Processor VRM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION POWER UP AND INITIALIZATION At power up, the LX1677 monitors the supply voltage to VCC and Vin, Before both supplies reach their undervoltage lock-out (UVLO) thresholds, a power on reset condition will prevent soft-start from beginning, the oscillator is disabled and all MOSFETs are kept off. SOFT-START Once the supplies are above the UVLO threshold and the Enable pin is brought high, the soft-start capacitor begins to be charged up by the reference DAC through the DACOUT pin. The capacitor voltage at the DACOUT pin rises as a linear ramp. The DACOUT pin is connected to the error amplifier’s non-inverting input which controls the output voltage. The output voltage will follow the DACOUT pin voltage. Phase 3 (hysteretic phase) is disabled during soft-start. Copyright © 2000 Rev 1.1, 2003-03-03 OVER-CURRENT PROTECTION (PHASE 1) The phase 1 current limit uses the RDS(ON) of the lower MOSFET, together with a resistor (RSET) to set the actual current limit point. The current limit comparator senses the current 400 nS after the lower MOSFET is switched on. A current source supplies a current (ISET), of 50µA which flows into RSET and determines the current limit trip point. The value of RSET is selected to set the current limit for the application. Phase 1 RSET is calculated by: R SET = ILimit • RDS(ON) 50 µA The current limit comparator will trip when the drop across RSET equals the drop across the lower MOSFET RDS(ON)., at this time the comparator outputs a signal to set the I limit latch and removes the enable command. The Over-Current sensing is done on phase 1 only because phase 2 current is always being forced to equal the phase 1 current, therefore the current trip point is set at half of the desired current limit. For an output current limit setting of 30 amps, the current trip point for phase 1 is set at 15 amps. When the phase 1 over current latch is set all three phases are disabled, all MOSFETs are turned off. Vin 50 uA Q1 RSET + _ + _ Vout _ Iout RDS(ON) + Current Limit Comparator Q2 Q2 Current Flow 400nSec Delay Figure 3 – Phase 1 Current Limit The delay before current limit is activated will result in current pulses exceeding the calculated values during the delay period if a short circuit is applied during that time. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 APPLICATIONS OVER-CURRENT PROTECTION There are two separate current limit circuits in the LX1677. One looks at the phase 1 lower MOSFET drain current and the second looks at the phase 3 upper MOSFET drain current. Both circuits have a 400 nS delay before a current limit command is issued to the current limit latch, once set the current limit latch will hold all three phases off until it is reset. The Over-Current Protection is disabled during positive VID changes. To reset the current limit latch either the enable command (ENA) must be cycled low then back high or the input power must cycle off and then back on. WWW . Microsemi .C OM GENERAL DESCRIPTION The LX1677 is a voltage-mode pulse-width modulation controller integrated circuit. The PWM frequency is programmable from 200kHz to 1MHz. The device has external compensation, for more flexibility of the loop response. The LX1677 also makes use of a true differential input amplifier for remote voltage sensing at the actual processor core. This is a very important feature now that the core voltages are in the 1 to 2 volt range. The reference for the biphase PWM output is a 5 bit VID code DAC. The VID code DAC can generate a reference voltage of 0.925 to 2.000 volts. The output of the DAC is a bi-directional current source and is connected to the DACOUT pin. Connecting a capacitor from this pin to ground will generate a linear ramp, which will determine the rate of change of the output voltage. The rate of change can be set so that the current required to charge the total output capacitance is below the maximum current limit trip point. This will allow VID changes on the fly without tripping the over current sensor. LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) 50 uA ILIM3 +_ RSET + Current Limit Comparator + RDS(ON) Q1 _ Vout VS3 400nS Delay Q2 Figure 4 – Phase 3 Current Limit Enable (ENA) pin being pulled low Over-current condition on either phase 1 or phase 3 Over Voltage output > 1.85V Under Voltage output < 0.725V PWM FREQUENCY An external resistor sets the PWM frequency from the ROSC pin to ground. Phase 3 RSET is calculated by: Rset = In all cases except Over Voltage all MOSFET drivers will be latched off. For an Over Voltage fault the lower MOSFETs for phase 1 and 2 will be held on to discharge the bulk capacitance on the output till a lower limit of 0.725 volts is reached then all MOSFETS will be turned off. To reset a fault it necessary to cycle the ENA pin low then back high or remove and reapply the input voltage VIN. The Under Voltage monitor is not enabled until the output voltage has ramped up to the level commanded by the DACOUT pin and the PWGD output in high. Vin _ FAULT LOGIC There are a number of possible states that will cause a fault condition that will disable the output MOSFET drivers. A fault condition will be caused by the following: WWW . Microsemi .C OM OVER-CURRENT PROTECTION (PHASE 3) The hysteretic phase has its own current limit protection because with it’s very fast response time with a 100 nH inductor the upper MOSFET cannot be allowed to stay on during an output short circuit condition. The phase 3 overcurrent sensing uses the RDS(ON) of the upper MOSFET with a resistor RSET to determine the over current limit point. A current source draws 50uA through RSET which determines the required drop across the MOSFET RDS(ON) to initiate a current limit condition. The equation for ROSC is: ILimit • RDSon 50uA ROSC = OVER VOLTAGE PROTECTION An over voltage protection circuit monitors the output voltage and will latch all three phases off if an over voltage condition (greater than 2.35 V) is detected. Both MOSFETs for phase 3 will be held off and the lower MOSFETs for phase 1 and 2 will be held on to discharge the output capacitor till the output voltage drops below .85 volt, at .85 volts all MOSFETs will be turned off. ( 1 K • f ) + 100e − 9 where ROSC is in Ω, f is in Hz, K=105e-12 APPLICATIONS Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 10 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) Phase 1 Low Pass Filter Phase 1 Diff Amp + - - Differential Amp EA - LP2 _ gm 180° Phase 2 Integrating Amp Ramp .75 V to 3 V Both PWMs + Phase 2 Comparator HO1 LO1 PWM + DC Bias Phase 1 Comparator + DC Bias + + _ PWM DACOUT DC Bias 0° - Differential Feedbach From Vout LP1 Phase 1 Error Amp HO2 Vout LO2 EO2 APPLICATIONS Phase 2 Low Pass Filter Figure 5 – LoadSHARE Control Loop Copyright © 2000 Rev 1.1, 2003-03-03 WWW . Microsemi .C OM The second feedback loop will use the output of the phase 1 LPF as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 LPF. This error signal will be amplified and used to control the PWM circuit of phase 2. Therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. This will force the current in the phase 2 inductor to follow and equal the phase 1 inductor current. With the LoadSHARETM topology it is possible to imbalance the phases so that one phase will supply more current than the other under unique situations. The LX1677 will normally be used with the same supply voltages on phase 1 and 2 PWM inputs and will have equal currents in both phases. THEORY OF OPERATION FOR A BI-PHASE, LOADSHARETM CONFIGURATION The basic principle used in LoadSHARETM in a multiple phase buck converter topology is that if multiple, identical, inductors have the same identical voltage impressed across their leads, they must then have the same identical current passing through them. The current that we would like to balance between inductors is mainly the DC component along with as much as possible the transient current. All inductors in a multiphase buck converter topology have their output side tied together at the output filter capacitors. Therefore this side of all the inductors has the same identical voltage. If the input side of the inductors can be forced to have the same equivalent DC potential on this lead, then they will have the same DC current flowing. To achieve this requirement, phase 1 will be the control phase that sets the output operating voltage, under normal PWM operation. To force the current of phase 2 to be equal to the current of phase 1; a second feedback loop is used. Phase 2 has a low pass filter connected from the input side of each inductor. This side of the inductors has a square wave signal that is proportional to its duty cycle. The output of each LPF is a DC (+ some AC) signal that is proportional to the magnitude and duty cycle of its respective inductor signal. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION (CONTINUED) DACOUT +5V VC3 + 35mV FB - I-Max I-Max Comparator Vout VCCL VS3 70nH + - FB + + Phase 3 is a Transient Correction Loop that can sum a large amount of current into the output node when required by an out of range condition. The differential feedback summing amplifier is connected directly to the output terminals and has sufficient bandwidth to follow any fast changes in output voltage. The feedback error voltage is compared to the commanded reference voltage (DACOUT) by two high speed comparators, I-Max and I-Min. The other inputs of these comparators are offset from the DACOUT as shown in Fig 6. If the error in output voltage exceeds the offset in either direction the appropriate MOSFET will be turned on to force current into or out of the output node to correct the voltage error. The very low value inductor (100nH) allows large amounts of current to be forced into or out of the output node very quickly. When the Transient Correction Loop is switching it forces the appropriate upper or lower MOSFETs in phases 1 and 2 to stay on (100% or 0% duty cycle) until the error is corrected. - TRANSIENT CORRECTION LOOP - The PWM ramp shown in Figure 5 is automatically adjusted to keep its amplitude a fixed percentage of Vin over the range of 6 to 24 V input. This maintains a constant loop gain that is set by the feedback networks around the error amplifiers independent of PWM input voltage. The two drivers for the Transient Correction Loop have outputs (I-Max) and (I-Min) that may be used to drive a half bridge to correct for both low and high output voltage conditions. This permits pulling the output low if an overshoot occurs due to a rapid reduction in load current. With a conventional Buck regulator rapid changes in the negative direction are not possible due to the low voltage available as a forcing function. The two outputs (I-MAX and I-MIN) are completely independent. A single MOSFET and diode can be used to correct for voltage droop only or voltage overshoot only when driven by the appropriate output. If the I-MAX driver is not used the VC3 and VS3 pins must be connected to +5 volts. Under normal operation the Transient Correction phase is only active for a very brief time during high di/dt loads on the output. WWW . Microsemi .C OM LOOP GAIN AUTOMATIC COMPENSATION 35mV I-Min I-Min Comparator PGN3 Figure 6 – Phase 3 Transient Correction Loop APPLICATIONS Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET APPLICATION NOTE The allowed ESR can be found by: VRIPPLE = ESR × I RIPPLE ( VIN − VOUT L × D fs ∆I is the inductor ripple current, L is the output inductor value and ESR is the Effective Series Resistance of the output capacitor. ∆I should typically be in the range of 20% to 40% of the maximum output current. Higher inductance results in lower output voltage ripple, allowing slightly higher ESR to satisfy the transient specification. Higher inductance also slows the inductor current slew rate in response to the loadcurrent step change, ∆I, resulting in more output-capacitor voltage droop. When using electrolytic capacitors, the capacitor voltage droop is usually negligible, due to the large capacitance The inductor-current rise and fall times are: TRISE = L× ∆I (V IN − VOUT ) and TFALL = L× ∆I ∆I × D fs I RMS = I L d(0.5 − d) for d < 0.5 OUTPUT CAPACITOR The output capacitor is sized to meet ripple and transient performance specifications. Effective Series Resistance (ESR) is a critical parameter. When a step load current occurs, the output voltage will have a step that equals the product of the ESR and the current step, ∆I. In an advanced Copyright © 2000 Rev 1.1, 2003-03-03 Where IL is the inductor current and d is the duty cycle. The maximum RMS value of 0.25IL will occur when d = 25% or 75%. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 APPLICATIONS VIN − VOUT Where IRIPPLE is the inductor ripple current, ∆I is the maximum load current step change, and VEX is the allowed output voltage excursion in the transient. Electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. As they age, their ESR degrades, reducing the system performance and increasing the risk of failure. It is recommended that multiple parallel capacitors be used, so that, as ESR increase with age, overall performance will still meet the processor’s requirements. There is frequently strong pressure to use the least expensive components possible, however, this could lead to degraded long-term reliability, especially in the case of filter capacitors. Microsemi’s demonstration boards use the CDE Polymer AL-EL (ESRE) filter capacitors, which are aluminum electrolytic, and have demonstrated reliability. The OS-CON series from Sanyo generally provides the very best performance in terms of long term ESR stability and general reliability, but at a substantial cost penalty. The CDE Polymer AL-EL (ESRE) filter series provides excellent ESR performance at a reasonable cost. Beware of off-brand, very low-cost filter capacitors, which have been shown to degrade in both ESR and general electrolytic characteristics over time. INPUT CAPACITOR The input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5V rail. In addition, the input capacitor provides local de-coupling the buck converter. The capacitor should be rated to handle the RMS current requirements. The RMS current is: VOUT . The inductance value can be calculated by: L= ) ESR × I RIPPLE + ∆I < VEX where ∆I = microprocessor power supply, the output capacitor is usually selected from ESR instead of capacitance or RMS current capability. A capacitor that satisfies the ESR requirements usually has a larger capacitance and current capability than strictly needed WWW . Microsemi .C OM OUTPUT INDUCTOR The output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. The peak-to-peak output voltage ripple is: LX1677 TM ® AMD64 Processor VRM Controller P RODUCTION D ATA S HEET APPLICATION NOTE (CONTINUED) PROGRAMMING THE OUTPUT VOLTAGE Output voltage is determined by the internal 5 bit DAC. The DAC inputs are the Voltage Identification (VID) 0-4 lines, the VID table lists the available output voltages for the corresponding VID codes. There are no external resistor dividers to program output voltage and only the steps listed are available. WWW . Microsemi .C OM SOFT-START CAPACITOR An external soft-start capacitor is connected to the DACOUT pin and will be charged, or discharged, at a linear rate by the internal 50uA bi-directional current source after the UVLO circuit has been satisfied. Whenever the VID code is changed during normal operation the soft-start capacitor will determine the rate of change at the output. APPLICATIONS Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 LX1677 ® TM AMD64 Processor VRM Controller P RODUCTION D ATA S HEET PACKAGE DIMENSIONS WWW . Microsemi .C OM LQ 38-Pin Micro Leadframe Package (MLPQ) D L Dim A A1 A3 b D D2 E E2 e L D2 E E2 3 2 1 e MILLIMETERS MIN MAX 0.80 1.00 0 0.05 0.20 REF 0.18 0.30 5.00 BSC 3.00 3.25 7.00 BSC 5.00 5.25 0.50 BSC 0.30 0.50 INCHES MIN MAX 0.031 0.039 0 0.002 0.008 REF 0.007 0.011 0.196 BSC 0.118 0.127 0.275 BSC 0.196 0.206 0.019 BSC 0.012 0.020 MILLIMETERS MIN MAX 1.2 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 9.60 9.80 6.25 6.50 4.30 4.50 0.50 BSC 0.45 0.75 0° 8° 0.10 INCHES MIN MAX 0.047 0.002 0.006 0.031 0.041 0.007 0.011 0.004 0.008 0.378 0.386 0.246 0.256 0.169 0.177 0.02 BSC 0.018 0.030 0° 8° 0.004 A b A1 PW A3 38-Pin Thin Small Shrink Outline (TSSOP) 1 19 E 20 38 e E1 D M A2 A b L c MECHANICALS A1 Dim A A1 A2 b c D E E1 e L M *LC Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 15 LX1677 TM ® AMD64 Processor VRM Controller P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2000 Rev 1.1, 2003-03-03 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 16