TI SMJ626162

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
D
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HKD PACKAGE
(TOP VIEW)
Organization
512K × 16 Bits × 2 Banks
3.3-V Power Supply (±5% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
High Bandwidth – Up to 83-MHz Data Rates
Read Latency Programmable to
2 or 3 Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or
Interleave
Burst Length Programmable to 1, 2, 4, 8, or
256 (Full Page)
Chip Select and Clock Enable for Enhanced
System Interfacing
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control
Autorefresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
Pipeline Architecture
Temperature Ranges:
Operating, – 55°C to 125°C
Storage, – 65°C to 150°C
Performance Ranges:
’626162-12
’626162-15
’626162-20
† Read latency = 3
SYNCHRONOUS
ACCESS TIME
CLOCK CYCLE
CLOCK TO
TIME
TIME
OUTPUT
INTERVAL
tCK
(MIN){
tAC
(MIN){
tREF
(MAX)
12 ns
15 ns
20 ns
8 ns
9 ns
10 ns
32 ms
32 ms
32 ms
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VCCQ
NC
DQMU
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
REFRESH
description
The SMJ626162 series of devices are
16 777 216-bit synchronous dynamic randomaccess memory (SDRAM) devices organized as
two banks of 524 288 words with 16 bits per word.
All inputs and outputs of the SMJ626162 series
are compatible with the LVTTL interface.
PIN NOMENCLATURE
A[0:10]
A11
CAS
CKE
CLK
CS
DQ[0:15]
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
Address Inputs
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Data Output
Data-Input/Data-Output Mask Enable
No Connect
Row-Address Strobe
Power Supply (3.3-V Typical)
Power Supply for Output Drivers
(3.3-V Typical)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
• HOUSTON, TEXAS 77251–1443
1
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power requirements.
All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with
high-speed microprocessors and caches.
The SMJ626162 SDRAM is available in a 50-lead, 650-mil-wide ceramic dual flatpack (HKD suffix).
functional block diagram
CLK
CKE
AND
CS
DQMx
RAS
CAS
W
A0–A11
Array Bank T
DQ
Buffer
Control
16
DQ0–DQ15
Array Bank B
12
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ15, are also referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently; however, a bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
D
D
D
D
D
Bank-activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank-deactivate
Autorefresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1, Table 2, and Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2
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SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
Table 1. Basic Command Truth Table†
COMMAND
Mode register set
Bank deactivate (precharge)
Deactivate all banks
STATE OF
BANK(S)
CS
RAS
CAS
W
A11
A10
A9 – A0
MNEMONIC
T = deac
B = deac
L
L
L
L
X
X
A9 = V
A8 – A7 = 0
A6 – A0 = V
MRS
X
L
L
H
L
BS
L
X
DEAC
X
L
L
H
L
X
H
X
DCAB
Bank activate/row-address entry
SB = deac
L
L
H
H
BS
V
V
ACTV
Column-address entry / write operation
SB = actv
L
H
L
L
BS
L
V
WRT
Column-address entry / write operation
with auto-deactivate
SB = actv
L
H
L
L
BS
H
V
WRT-P
Column-address entry/read operation
SB = actv
L
H
L
H
BS
L
V
READ
Column-address entry/read operation
with auto-deactivate
SB = actv
L
H
L
H
BS
H
V
READ-P
X
L
H
H
H
X
X
X
NOOP
X
H
X
X
X
X
X
X
DESL
T = deac
B = deac
L
L
L
H
X
X
X
REFR
No operation
Control-input inhibit / no operation
Autorefresh‡
† For execution of these commands on cycle n, one of the following must be true:
– CKE (n–1) must be high
– tCESP must be satisfied for power-down exit
– tCES and nCLE must be satisfied for clock-suspend exit. DQMx (n) is irrelevant.
‡ Autorefresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
V
= Valid
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
BS
= Logic high to select bank T; logic low to select bank B
SB
= Bank selected by A11 at cycle n
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3
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
Table 2. Clock-Enable (CKE) Command Truth Table†
STATE OF BANK(S)
CKE
(n – 1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
MNEMONIC
T = no access operation§
B = no access operation§
H
L
X
X
X
X
PDE
T = power down
B = power down
L
H
X
X
X
X
—
CLK suspend on cycle (n + 1)
T = access operation§
B = access operation§
H
L
X
X
X
X
HOLD
CLK suspend exit on cycle (n + 1)
T = access operation§
B = access operation§
L
H
X
X
X
X
—
COMMAND
Power-down entry on cycle (n + 1)‡
Power-down exit¶
† For execution of these commands, A0 – A11 (n) and DQMx (n) are don’t care entries.
‡ On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.
§ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
¶ If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise,
either a DESL or a NOOP command must be applied before any other command.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
T
= Bank T
B
= Bank B
4
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• HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
Table 3. Data Mask (DQM) Command Truth Table†
COMMAND
STATE OF
BANK(S)
DQML
DQMU‡
(n)
DATA IN
(n)
DATA OUT
(n + 2)
MNEMONIC
—
T = deac
and
B = deac
X
N/A
Hi-Z
—
—
T = actv
and
B = actv
( no access operation )§
X
N/A
Hi-Z
—
Data-in enable
T = write
or
B = write
L
V
N/A
ENBL
Data-in mask
T = write
or
B = write
H
M
N/A
MASK
Data-out enable
T = read
or
B = read
L
N/A
V
ENBL
Data-out mask
T = read
or
B = read
H
N/A
Hi-Z
MASK
† For execution of these commands on cycle n, one of the following must be true:
– CKE (n) must be high
– tCESP must be satisfied for power-down exit
– tCES and nCLE must be satisfied for clock-suspend exit.
CS(n), RAS(n), CAS(n), W(n), and A0 – A11 are irrelevant.
‡ DQML controls DQ0 – DQ7.
DQMU controls DQ8 – DQ15.
§ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
V
= Valid
M
= Masked input data
N/A = Not applicable
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
write = Activated and accepting data in on cycle n
read = Activated and delivering data out on cycle (n + 2)
Hi-Z = High-impedance state
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5
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
burst sequence
All data for the ’626162 is written or read in a burst fashion—that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first access can be at preceding, as well as succeeding, column
addresses, depending on the starting address entered. This sequence can be programmed to follow either a
serial burst or an interleave burst (see Table 4, Table 5, and Table 6). The length of the burst can be programmed
to be either 1, 2, 4, 8, or full-page (256) accesses (see the section on setting the mode register). After a read
burst is completed (as determined by the programmed burst length), the outputs are in the high-impedance state
until the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL
Serial
Interleave
6
BINARY
START
2ND
3RD
4TH
START
2ND
3RD
0
1
2
3
00
01
10
11
1
2
3
0
01
10
11
00
2
3
0
1
10
11
00
01
3
0
1
2
11
00
01
10
0
1
2
3
00
01
10
11
1
0
3
2
01
00
11
10
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
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4TH
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
BINARY
START
2ND
3RD
4TH
5TH
6TH
7TH
8TH
START
2ND
3RD
4TH
5TH
6TH
7TH
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
2
3
4
5
6
7
0
1
010
011
100
101
110
111
000
001
3
4
5
6
7
0
1
2
011
100
101
110
111
000
001
010
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
6
7
0
1
2
3
4
101
110
111
000
001
010
011
100
6
7
0
1
2
3
4
5
110
111
000
001
010
011
100
101
7
0
1
2
3
4
5
6
111
000
001
010
011
100
101
110
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
0
3
2
5
4
7
6
001
000
011
010
101
100
111
110
2
3
0
1
6
7
4
5
010
011
000
001
110
111
100
101
3
2
1
0
7
6
5
4
011
010
001
000
111
110
101
100
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
4
7
6
1
0
3
2
101
100
111
110
001
000
011
010
6
7
4
5
2
3
0
1
110
111
100
101
010
011
000
001
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
Serial
Interleave
8TH
latency
The beginning data-out cycle of a read burst can be programmed to occur 2 or 3 CLK cycles after the read
command (see the section on setting the mode register). This feature allows the adjustment of the ’626162 to
operate in accordance with the system’s capability to latch the data output from the ’626162. The delay between
the READ command and the beginning of the output burst is known as read latency (also known as CAS
latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening
gaps. Use of minimum read latencies is restricted, based on the particular maximum frequency rating of the
’626162.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the contents of the mode register.
two-bank operation
The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Then, each bank must be
deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry
command (ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK.
A bank can be deactivated either automatically during a READ-P or a WRT-P command or by use of the
deactivate-bank command (DEAC). Both banks can be deactivated at once by use of the DCAB command (see
Table 1 and the section on bank deactivation).
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7
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM. This is accomplished by activating one bank with a row address and, while the data
stream is being accessed to/from that bank, activating the second bank with another row address. When the
data stream to/from the first bank is complete, the data stream to/from the second bank can begin without
interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row
address for the next round of accesses. In this manner, operation can continue in an interleaved fashion.
Figure 25 is an example of two-bank, row-interleaving, read bursts with automatic deactivate for a read latency
of 3 and a burst length of 8.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
read or write commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 26 is an example of two-bank, column-interleaving, read bursts
for a read latency of 3 and a burst length of 2.
bank deactivation (precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 is used to select the bank to be precharged as shown in Table 1.
A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is held high
during the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically
upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank
remains active following the burst. The read and write commands with automatic deactivation are denoted as
READ-P and WRT-P.
chip select (CS)
CS can be used to select or deselect the ’626162 for command entry, which might be required for
multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again. Device select is accomplished by holding
CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising
CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1
and Table 2). The use of CS does not affect an access burst that is in progress; the DESL command can restrict
only RAS, CAS, and W input to the ’626162.
data mask
The mask command, or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any individual data cycle within a read burst or a write burst. DQML controls
DQ0–DQ7, and DQMU controls DQ8–DQ15. The application of DQMx to a write burst has no latency
(nDID = 0 cycle), but the application of DQMx to a read burst has a latency of nDOD = 2 cycles. During a write
burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst,
if DQMx is held high on the rising edge of CLK, then nDOD cycles after the rising edge of CLK, the data-output
will be in the high-impedance state. Figure 16, Figure 29, Figure 30, Figure 31, and Figure 32 show examples
of data-mask operations.
8
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SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
setting the mode register
The ’626162 contains a mode register that must be programmed with the read latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on address lines A0–A9. A logic 0 must be entered on A7 and A8. A10 and A11 are don’t care entries
for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined
by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word
valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.
A11
A10
A9
Reserved
A8
A7
0
0
A6
A5
A4
A3
A2
A1
A0
0 = Serial
1 = Interleave
(burst type)
REGISTER
BIT A9
WRITEBURST
LENGTH
0
A2–A0
1
1
REGISTER
BITS†
A6
0
0
A5
A4
1
1
0
1
READ
LATENCY‡
2
3
REGISTER
BITS†
BURST LENGTH
A2
A1
A0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
4
8
256
† All other combinations are reserved.
‡ See the timing requirements for minimum valid read latencies based on maximum frequency rating.
Figure 1. Mode-Register Programming
refresh
The ’626162 must be refreshed at intervals not exceeding tREF (see timing requirements) or data cannot be
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, or by
performing 4096 autorefresh (REFR) commands. Regardless of the method used, refresh must be
accomplished before tREF has expired.
autorefresh (REFR)
Before performing a REFR operation, both banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, both banks of the ’626162 have
been refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command
automatically deactivates both banks upon completion of the internal autorefresh cycle. This allows consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before tREF expires.
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9
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
CLK-suspend/power-down mode
For normal device operation, CKE must be held high to enable CLK. If CKE goes low during the execution of
a read or write operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current
state. No further inputs are accepted until CKE returns high; this is known as a CLK-suspend operation, and
its execution is denoted as a HOLD command. The device resumes operation from the point at which it was
placed in suspension, beginning with the second rising edge of CLK after CKE returns high.
If CKE is brought low when no read or write command is in progress, the device enters the power-down mode.
If both banks are deactivated when the power-down mode is entered, power consumption is reduced to the
minimum. Power-down mode can be used during row-active or autorefresh periods to reduce input-buffer
power. After power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that
data in the device remains valid, the power-down mode must be exited periodically to meet the requirements
described earlier for device refresh. When exiting power-down mode, new commands can be entered on the
first CLK edge after CKE returns high, provided that the setup time (tCESP) is satisfied. Table 2 shows the
command configuration for a CLK-suspend/power-down operation; Figure 17, Figure 18, and Figure 35 show
examples of the procedure.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of a READ-P or a
WRT-P operation is not supported.
Table 7. Read-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
READ, READ-P
Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met
and new output cycles begin (see Figure 2).
WRT, WRT-P
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQMx must
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD–1), nCCD, and
(nCCD+1), assuming that there is any output on these cycles (see Figure 3).
DEAC, DCAB
The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes, whichever
occurs first (see Figure 4).
nCCD = 1 Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
C0
DQ
C1
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
10
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C1 + 2
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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interrupted bursts (continued)
nCCD = 5 Cycles
CLK
Interrupting
WRT Command
READ Command
DQ
Q
D
D
See Note B
DQMx
NOTES: A. For this example, assume read latency = 3 and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (nCCD – 1), nCCD, and (nCDD + 1).
Figure 3. Read Burst Interrupted by Write Command
nCCD = 2 Cycles
nHZP
CLK
READ Command
Interrupting
DEAC/DCAB
Command
Q
DQ
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).
WRT, WRT-P
The new WRT (WRT-P) command and data inputs immediately supersede the write burst in progress
(see Figure 6).
DEAC, DCAB
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
mask the DQ bus such that the write recovery specification (tRWL) is not violated by the
interrupt (see Figure 7).
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interrupted bursts (continued)
nCCD = 1 Cycle
CLK
WRT
Command
READ
Command
D
DQ
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 5. Write Burst Interrupted by Read Command
nCCD = 2 Cycles
CLK
WRT Command
at Column
Address C0
DQ
C0
Interrupting
WRT Command
at Column Address C1
C0 + 1
C1
C1 + 1
C1 + 2
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
nCCD = 3 Cycles
CLK
WRT Command
DQ
D
Interrupting
DEAC or DCAB
Command
D
Ignored
Ignored
tRWL
DQMx
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
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Q
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power up
Device initialization should be performed after a power up to the full VCC level; however, after power is
established, a 200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the
device must be deactivated. Eight REFR commands must be performed and the mode register must be set to
complete the device initialization.
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absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any input pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
VCCQ
Supply voltage
3.135
3.3
3.465
V
Supply voltage for output drivers‡
3.135
3.3
3.465
V
VSS
VSSQ
Supply voltage
VIH
VIL
High-level input voltage
2
Low-level input voltage
0
Supply voltage for output drivers
0
TA
Ambient temperature
‡ VCCQ
VCC + 0.3 V
v
14
V
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V
V
– 0.3
VCC + 0.3
0.8
–55
125
°C
V
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electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
’626162-12
’626162-15
’626162-20
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
VOH
High-level output
voltage
IOH = –2 mA
VOL
Low-level output
voltage
IOL = 2 mA
0.4
0.4
0.4
V
II
Input current
(leakage)
0 V ≤ VI ≤ VCC,
All other pins = 0 V to VCC
±10
±10
±10
µA
IO
Output current
(leakage)
0 V ≤ VO ≤ VCCQ, Output disabled
±10
±10
±10
µA
Read latency = 2
85
75
70
Average
g read or
write current
Burst length = 1,
tRC ≥ tRC MIN,
IOH/IOL = 0 mA,
mA
One bank activated
(see Note 3)
Read latency = 3
100
95
85
2
2
2
2
2
2
40
35
30
2
2
2
CKE ≤ VIL MAX,
tCK = MIN
One bank activated (see Note 4)
10
10
10
CKE and CLK ≤ VILMAX,
tCK = ∞
One bank activated (see Note 5)
10
10
10
CKE ≥ VIH MIN,
tCK = MIN
One bank activated (see Note 4)
55
45
40
CKE ≥ VIH MIN,
CLK ≤ VIL MAX,
tCK = ∞, One bank activated (see Note 5)
15
15
15
165
130
110
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
Precharge
g standby
y
current in
power-down mode
Precharge standby
current in
nonpower-down
mode
Active standby
current in
power-down mode
Active standby
current in
nonpower-down
mode
Burst current
Autorefresh
NOTES: 2.
3.
4.
5.
6.
2.4
2.4
tCK = MIN (see Note 4)
CKE and CLK
VIL MAX,
tCK = ∞ (see Note 5)
v
tCK = MIN (see Note 4)
tRC ≥ tRC MIN
Read latency = 2
mA
mA
CKE ≥ VIH MIN,
CLK ≤ VIL MAX,
tCK = ∞ (see Note 5)
Continuous burst,
IOH/IOL = 0 mA,
activated
All banks activated,
nCCD = one cycle
(see Note 6)
V
mA
CKE ≤ VIL MAX,
CKE ≥ VIH MIN,
2.4
mA
mA
mA
Read latency = 3
210
175
150
Read latency = 2
120
100
80
Read latency = 3
120
100
80
mA
All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
Control and address inputs change state twice during tRC.
Control and address inputs change state once every 2 × tCK.
Control and address inputs do not change state (stable).
Control and address inputs change state once every cycle.
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capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 7)
PARAMETER
MIN
MAX
UNIT
Ci(S)
Input capacitance, CLK input
8
pF
Ci(AC)
Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W
8
pF
Ci(E)
Input capacitance, CKE input
8
pF
Co
Output capacitance
10
pF
NOTE 7: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
ac timing requirements†‡
’626162-12
MIN
tCK
time CLK (system clock)
Cycle time,
tCKH
tCKL
Pulse duration, CLK (system clock) high
’626162-20
MAX
MIN
15
20
30
Read latency = 3
12
15
20
4
4
4
Pulse duration, CLK (system clock) low
4
Access time,, CLK ↑ to data out
(see Note 8)
tLZ
Delay time, CLK to DQ in the low-impedance state (see Note 9)
Delayy time,, CLK to DQ in the
high-impedance state (see Note 10)
MIN
Read latency = 2
tAC
tHZ
’626162-15
MAX
4
MAX
ns
ns
4
ns
Read latency = 2
9
15
20
Read latency = 3
8
9
10
0
0
UNIT
0
ns
ns
Read latency = 2
8
14
15
Read latency = 3
8
11
12
ns
tDS
tAS
Setup time, data input
3
4
4
ns
Setup time, address
3
4
4
ns
tCS
tCES
Setup time, control input (CS, RAS, CAS, W, DQMx)
3
4
4
ns
Setup time, CKE (suspend entry/exit, power-down entry)
3
4
4
ns
tCESP
tOH
Setup time, CKE (power-down/self-refresh exit) (see Note 11)
10
10
10
ns
Hold time, CLK ↑ to data out
1.5
2
2
ns
tDH
tAH
Hold time, data input
2
2
2
ns
Hold time, address
2
2
2
ns
tCH
tCEH
Hold time, control input (CS, RAS, CAS, W, DQMx)
2
2
2
ns
Hold time, CKE
tRC
tRAS
tRCD
2
2
2
ns
REFR command to ACTV, MRS, or REFR command;
ACTV command to ACTV, MRS, or REFR command
96
120
160
ns
ACTV command to DEAC or DCAB command
60
ACTV command to READ or WRT command (see Note 12)
24
100 000
75
30
100 000
100
40
100 000
ns
ns
tRP
DEAC or DCAB command to ACTV, MRS, or REFR command
36
45
60
ns
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK unless otherwise noted.
NOTES: 8. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced
from the rising transition of CLK that is one cycle before read latency for the READ command. Access time is measured at output
reference level 1.4 V.
9. tLZ is measured from the rising transition of CLK that is one cycle before read latency for the READ command.
10. tHZ (MAX) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
11. See Figure 18.
12. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
16
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ac timing requirements†‡ (continued)
tAPR
’626162-12
’626162-15
’626162-20
MIN
MIN
MIN
MAX
Final data out of READ-P operation to ACTV, MRS, or REFR
command
MAX
tRP + (nEP × tCK)
tAPW
tRWL
Final data in of WRT-P operation to ACTV, MRS, or REFR command
Final data in to DEAC or DCAB command
24
tRRD
tT
ACTV command for one bank to ACTV command for the other bank
24
Transition time, all inputs (see Note 13)
MAX
tRP + tCK
30
5
ns
ns
40
30
1
ns
40
1
UNIT
5
ns
1
5
ns
tREF
Refresh interval
32
32
32
ms
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK unless otherwise noted.
NOTE 13: Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between VIH MIN and VIL MAX. This is
ensured by design but not tested.
clock timing requirements‡§
’626162-12
’626162-15
’626162-20
MIN
MIN
MIN
MAX
MAX
MAX
UNIT§
nEP
Final data out to DEAC or
DCAB command
Read latency = 2
–1
–1
–1
Read latency = 3
–2
–2
–2
DEAC or DCAB interrupt of
data out burst to DQ in the
data-out
high-impedance state
Read latency = 2
2
2
2
nHZP
Read latency = 3
3
3
3
nCCD
READ or WRT command to interrupting READ, WRT, DEAC, or DCAB
command
1
1
1
nCWL
nWCD
Final data in to READ or WRT command in either bank
1
WRT command to first data in
0
0
0
0
0
0
cycles
nDID
nDOD
ENBL or MASK command to data in
0
0
0
0
0
0
cycles
ENBL or MASK command to data out
2
2
2
2
2
2
cycles
HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command
1
1
1
1
1
1
cycles
nCLE
cycles
cycles
1
cycles
1
cycles
nRSA
MRS command to ACTV, REFR, or MRS command
2
2
2
cycles
nCDD DESL command to control input inhibit
0
0
0
0
0
0 cycles
‡ All references are made to the rising transition of CLK unless otherwise noted.
§ A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE
(those CLK cycles occurring during the time when CKE is asserted low).
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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PARAMETER MEASUREMENT INFORMATION
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level is changed
to VIH MIN and VIL MAX instead of the midpoint level. All specifications referring to READ commands are also
valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also
valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are
specified as consecutive commands for the same bank unless otherwise noted.
IOL
Tester Pin
Electronics
(see Note A)
50 Ω
1.4 V
Output
Under
Test
CL = 50 pF
IOH
NOTE A: Series termination resistors may be used on test
hardware for output impedance matching purposes.
Figure 8. LVTTL-Load Circuit
tCK
tCKH
CLK
tT
tCKL
tDS, tAS, tCS, tCES
tT
tDH, tAH, tCH, tCEH
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
tT
tDH, tAH, tCH, tCEH
tDS, tAS, tCS, tCES, tCESP
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
tT
Figure 9. Input-Attribute Parameters
18
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PARAMETER MEASUREMENT INFORMATION
Read Latency
CLK
ACTV
Command
tAC
READ
Command
tHZ
tLZ
tOH
DQ
Figure 10. Output Parameters
READ, WRT
nCCD
READ, READ-P, WRT, WRT-P, DEAC, DCAB
DESL
nCDD
Command Disable
ACTV
tRAS
DEAC, DCAB
ACTV, REFR
ACTV
DEAC, DCAB
tRC
tRCD
tRP
ACTV, MRS, REFR
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR
ACTV
tRRD
ACTV (different bank)
MRS
nRSA
ACTV, MRS
Figure 11. Command-to-Command Parameters
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PARAMETER MEASUREMENT INFORMATION
nHZP
nEP
CLK
DEAC or
DCAB
Command
READ
Command
DQ
Q
tHZ
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 12. Read Followed by Deactivate
tAPR
CLK
READ-P
Command
ACTV, MRS, or
REFR Command
Final Data Out
DQ
Q
NOTE A: For this example, assume read latency = 3 and burst length = 1.
Figure 13. Read With Auto-Deactivate
nCWL
tRWL
CLK
WRT
Command
DQ
WRT
Command
D
DEAC or DCAB
Command
D
NOTE A: For this example, assume burst length = 1.
Figure 14. Write Followed By Deactivate
20
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PARAMETER MEASUREMENT INFORMATION
nCWL
tAPW
CLK
WRT
Command
DQ
ACTV, MRS, or
REFR Command
WRT-P
Command
D
D
Figure 15. Write With Auto-Deactivate
nDOD
tRWL
nDOD
CLK
DEAC or
DCAB
Command
WRT
Command
READ
Command
DQ
Q
ENBL
Command
MASK
Command
MASK
Command
MASK
Command
D
Ignored
Ignored
ENBL
Command
MASK
Command
MASK
Command
Ignored
DQMx
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 16. DQ Masking
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PARAMETER MEASUREMENT INFORMATION
nCLE
nCLE
CLK
DQ
DQ
DQ
DQ
DQ
tCES
tCES
tCEH
tCEH
CKE
Figure 17. CLK-Suspend Operation
22
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PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
power-down
mode
Exit
power-down
mode if tCESP is
satisfied (new
command)
CLK is don’t
care, but
must be
stable
before CKE
high
CKE
tCESP
tCEH
tCES
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
power-down
mode
CLK is don’t
care, but
must be
stable
before CKE
high
DESL or
NOOP
command
only if tCESP
is not
satisfied
Exit power-down
mode (new
command)
CKE
tCEH
tCESP
tCES
Figure 18. Power-Down Operation
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23
DEAC T
CLK
DQ
a
b
c
d
DQMx
PARAMETER MEASUREMENT INFORMATION
RAS
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CAS
W
R0
A10
A11
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum tRCD and nEP for the ’626162-15 at 66 MHz.
Figure 19. Read Burst (read latency = 3, burst length = 4)
SMJ626162
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READ T
SGMS737C – JULY 1997 – REVISED MARCH 1999
24
ACTV T
ACTV T
WRT T
DEAC T
CLK
a
DQ
b
c
d
e
f
g
h
DQMx
RAS
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W
R0
A10
A11
R0
A0 – A9
C0
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum tRCD and tRWL for the ’626162-15 at 66 MHz.
Figure 20. Write Burst (burst length = 8)
25
SGMS737C – JULY 1997 – REVISED MARCH 1999
BURST
TYPE
SMJ626162
524288 BY 16-BIT BY 2-BANK
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PARAMETER MEASUREMENT INFORMATION
CAS
WRT B
READ B
DEAC B
CLK
DQ
a
c
b
d
DQMx
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
A11
A0 – A9
R0
C1
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
D
Q
B
B
R0
R0
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1 + 1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum tRCD and nEP for the ’626162-15 at 66 MHz.
Figure 21. Write-Read Burst (read latency = 3, burst length = 2)
PARAMETER MEASUREMENT INFORMATION
CAS
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV B
SGMS737C – JULY 1997 – REVISED MARCH 1999
26
3
ACTV T
READ T
WRT-P T
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
DQMx
RAS
CAS
W
A11
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
i
j
k
C1
C1 + 1 C1 + 2
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
l
m
n
o
p
C1 + 3
C1 + 4
C1 + 5
C1 + 6
C1 + 7
Figure 22. Read-Write Burst With Automatic Deactivate (read latency = 3, burst length = 8)
SGMS737C – JULY 1997 – REVISED MARCH 1999
27
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
R0
A0 – A9
PARAMETER MEASUREMENT INFORMATION
R0
A10
WRT-P T
CLK
DQ
a
b
c
d
e
f
g
h
i
DQMx
RAS
CAS
W
R0
A11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
R0
C1
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
i
C1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 23. Read Burst – Single Write With Automatic Deactivate (read latency = 3, burst length = 8)
PARAMETER MEASUREMENT INFORMATION
A10
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ T
SGMS737C – JULY 1997 – REVISED MARCH 1999
28
ACTV T
ACTV B
READ- P B
CLK
DQ0
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+253 n+254 n+255
DQMx
RAS
CAS
W
R0
A11
R0
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
BURST CYCLE†
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
Q
B
R0
C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
† Column-address sequence depends on programmed burst type and starting column address C0.
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 24. Read Burst – Full Page (read latency = 3, burst length = 256)
p
q
r
s
.
255
.
SGMS737C – JULY 1997 – REVISED MARCH 1999
29
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
PARAMETER MEASUREMENT INFORMATION
A10
ACTV T
ACTV B
READ- P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
R1
R2
R3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A11
C0
R0
A0 – A9
R1
C1
R2
C2
R3
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
Q
Q
Q
B
T
B
R0
R1
R2
C0
BURST CYCLE†
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
C2 + 1 C2 + 2 .
.
C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
C1
C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7
C2
† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 25. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8)
PARAMETER MEASUREMENT INFORMATION
R0
A10
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ- P T
READ- P B
SGMS737C – JULY 1997 – REVISED MARCH 1999
30
ACTV T
ACTV B
ACTV T
ACTV B
READ T
READ T
READ B
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQMx
RAS
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
C2
C3
C4
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
Q
Q
Q
.
B
T
B
...
R0
R1
R0
...
C0
C0 + 1
BURST CYCLE †
c
d
C1
C1 + 1
e
f
C2
C2 + 1
...
...
...
...
† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).
Figure 26. Two-Bank Column-Interleaving Read Bursts (read latency = 3, burst length = 2)
31
SGMS737C – JULY 1997 – REVISED MARCH 1999
BURST
TYPE
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
DEAC B
READ B
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R1
R0
A11
A0 – A9
C0
R0
R1
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
B
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5.)
NOTE A: This example illustrates minimum tRCD, nEP, and tRWL for the ’626162-15 at 66 MHz.
Figure 27. Read-Burst Bank B, Write-Burst Bank T (read latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV B
DEAC T
SGMS737C – JULY 1997 – REVISED MARCH 1999
32
WRT T
ACTV T
ACTV T
WRT- P T
ACTV B
READ- P B
CLK
DQ
a
b
c
d
e
f
g
DQMx
RAS
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
D
Q
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE †
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum nCWL for the ’626162-15 at 66 MHz.
Figure 28. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency = 3, burst length = 4)
33
SGMS737C – JULY 1997 – REVISED MARCH 1999
BURST
TYPE
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
WRT T
DCAB
CLK
e
b
a
DQ
c
d
g
f
h
DQMx
RAS
W
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
R0
A10
A11
C0
R0
A0 – A9
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 29. Data Mask (read latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ T
SGMS737C – JULY 1997 – REVISED MARCH 1999
34
ACTV T
ACTV B
ACTV T
READ B
READ T
READ T
READ B
READ B
CLK
DQ0 – DQ7
a
b
c
d
e
f
DQML
Hi-Z
DQ8 – DQ15
DQMU
W
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
C2
C3
CS
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
Q
Q
Q
Q
T
B
T
B
R0
R1
R0
R1
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1+1
e
f
C2
C1+1
g
h
C3
C3+ 1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
Figure 30. Data Mask With Byte Control (read latency = 3, burst length = 2)
35
SGMS737C – JULY 1997 – REVISED MARCH 1999
CKE
C4
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
PARAMETER MEASUREMENT INFORMATION
RAS
WRT T
DEAC T
CLK
DQ0 – DQ7
e
f
g
h
DQML
a
DQ8 – DQ15
b
c
d
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
W
A10
R1
R0
A11
A0 – A9
R0
C0
R1
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD and nEP read burst, and a minimum tRWL write burst for the ’626162-15 at 66 MHz.
Figure 31. Data Mask With Byte Control (read latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
DQMU
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
DEAC B
READ B
SGMS737C – JULY 1997 – REVISED MARCH 1999
36
ACTV T
ACTV B
ACTV T
READ T
ACTV B
WRT B
DCAB
CLK
DQ0 – DQ7
a
b
c
d
a
b
c
d
f
h
DQML
DQ8 – DQ15
e
f
g
h
RAS
W
R0
A10
R1
A11
R0
A0 – A9
R1
C0
C1
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD and tRWL for the ’626162-15 at 66 MHz.
Figure 32. Data Mask With Cycle-by-Cycle Byte Control (read latency = 3, burst length = 4)
37
SGMS737C – JULY 1997 – REVISED MARCH 1999
BURST
TYPE
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
PARAMETER MEASUREMENT INFORMATION
DQMU
READ T
DEAC T
REFR
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
R0
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A10
A11
A0 – A9
R0
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim tRC, tRCD, and nEP for the ’626162-15 at 66 MHz.
Figure 33. Refresh Cycles (read latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
W
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV T
SGMS737C – JULY 1997 – REVISED MARCH 1999
38
REFR
MRS
DCAB
ACTV B
WRT-P B
CLK
DQ
a
b
c
d
DQMx
RAS
R0
A10
See Note B
A11
See Note B
A0 – A9
R0
C0
See Note B
CS
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
BURST CYCLE†
a
b
c
d
D
B
R0
C0
C0 + 1
C0 + 2
C0 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum tRP, nRSA, and tRCD for the ’626162-15 at 66 MHz.
B. See Figure 1.
Figure 34. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(read latency = 3, burst length = 4)
39
SGMS737C – JULY 1997 – REVISED MARCH 1999
CKE
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
WRT-P T
HOLD
HOLD
PDE
CLK
DQ
a
b
e
d
c
f
g
h
DQMx
RAS
CAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
R0
A10
A11
R0
A0 – A9
C1
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 35. CLK Suspend (HOLD) During Read Burst and Write Burst (read latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
W
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ T
SGMS737C – JULY 1997 – REVISED MARCH 1999
40
ACTV T
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
MECHANICAL DATA
HKD (R-CDFP-F50)
CERAMIC DUAL FLATPACK
0.665 (16,90)
0.634 (16,10)
1
50
0.031 (0,80)
0.843 (21,40)
0.811 (20,60)
0.766 (19,45)
0.746 (18,95)
0.020 (0,50)
0.012 (0,30)
25
26
0.370 (9,40)
0.250 (6,35)
0.015 (0,38) MIN
(4 Places)
Lid
0.140 (3,55)
0.110 (2,80)
0.009 (0,23)
0.004 (0,10)
0.030 (0,76) MIN
0.587 (14,90)
0.555 (14,10)
0.026 (0,66) MIN
4081537/B 10/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The leads will be gold plated.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
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