TI TMS626162

TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Organization . . . 512K × 16 × 2 Banks
3.3-V Power Supply (± 10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
High Bandwidth – Up to 83-MHz Data Rates
CAS Latency (CL) Programmable to 2 or 3
Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or
Interleave
Burst Length Programmable to 1, 2, 4, 8, or
Full Page
Chip Select and Clock Enable for
Enhanced-System Interfacing
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper and Lower Byte Control
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
Compatible With JEDEC Standards
Pipeline Architecture
Temperature Ranges:
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
SYNCHRONOUS
CLOCK CYLE
TIME
†
ACCESS TIME
CLOCK TO
OUTPUT
tAC2
(CL = 2)
DGE PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
REFRESH
INTERVAL
tREF
tCK3
(CL‡ = 3)
tCK2
(CL = 2)
tAC3
(CL = 3)
’626162-12A†
12 ns
15 ns
9 ns
9 ns
64 ms
’626162-12
12 ns
18 ns
9 ns
10 ns
64 ms
–12A speed device is supported only at –5/+10% VCC
‡ CL = CAS latency
description
The TMS626162 device is a high-speed
16 777 216-bit synchronous dynamic randomaccess memory (SDRAM) organized as two
banks of 524 288 words with 16 bits per word.
All inputs and outputs of the TMS626162 series
are compatible with the LVTTL interface.
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VCCQ
NC
DQMU
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0–A10
A11
CAS
CKE
CLK
CS
DQ0–DQ15
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
Address Inputs
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Output
Data/Output Mask Enables
No Connect
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626162 SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
CS
DQMx
RAS
CAS
W
A0 – A11
Array Bank T
AND
DQ
Buffer
Control
16
DQ0 – DQ15
Array Bank B
12
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0– DQ15, also are referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
D
D
D
D
D
D
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
Auto-refresh
Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
Table 1. Basic Command Truth Table†
COMMAND‡
Mode register set
Bank deactivate (precharge)
Deactivate all banks
STATE OF
BANK(S)
CS
RAS
CAS
W
A11
A10
A9 – A0
MNEMONIC
T = deac
B = deac
L
L
L
L
X
X
A9 = V
A8 – A7 = 0
A6 – A0 = V
MRS
X
L
L
H
L
BS
L
X
DEAC
X
L
L
H
L
X
H
X
DCAB
Bank activate/row-address entry
SB = deac
L
L
H
H
BS
V
V
ACTV
Column-address entry / write operation
SB = actv
L
H
L
L
BS
L
V
WRT
Column-address entry / write operation
with auto-deactivate
SB = actv
L
H
L
L
BS
H
V
WRT-P
Column-address entry/read operation
SB = actv
L
H
L
H
BS
L
V
READ
Column-address entry/read operation
with auto-deactivate
SB = actv
L
H
L
H
BS
H
V
READ-P
Burst stop
SB = actv
L
H
H
L
X
X
X
STOP
No operation
X
L
H
H
H
X
X
X
NOOP
Control-input inhibit / no operation
X
H
X
X
X
X
X
X
DESL
T = deac
B = deac
L
L
L
H
X
X
X
REFR
Auto refresh§
† For execution of these commands on cycle n:
– CKE (n–1) must be high, or
– tCESP must be satisfied for power-down exit, or
– tCESP and tRC must be satisfied for self-refresh exit, or
– tCES and nCLE must be satisfied for clock-suspend exit.
DQMx(n) is a don’t care.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ Auto-refresh or self-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
V
= Valid
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
BS
= Logic high to select bank T; logic low to select bank B
SB
= Bank selected by A11 at cycle n
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3
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
Table 2. Clock Enable (CKE) Command Truth Table†
COMMAND‡
Self-refresh entry
Power-down entry on cycle (n + 1)§
STATE OF BANK(S)
CKE
(n – 1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
MNEMONIC
T = deac
B = deac
H
L
L
L
L
H
SLFR
T = no access operation¶
B = no access operation¶
H
L
X
X
X
X
PDE
L
H
L
H
H
H
—
Self refresh exit
Self-refresh
T = self refresh
B = self refresh
L
H
H
X
X
X
—
Power-down exit#
T = power down
B = power down
L
H
X
X
X
X
—
CLK suspend on cycle (n + 1)
T = access operation¶
B = access operation¶
H
L
X
X
X
X
HOLD
CLK suspend exit on cycle (n + 1)
T = access operation¶
B = access operation¶
L
H
X
X
X
X
—
† For execution of these commands, A0 – A11 (n) and DQMx (n) are don’t cares.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.
¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
# If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise,
either DESL or NOOP command must be applied before any other command.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
T
= Bank T
B
= Bank B
deac = Deactivated
4
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
Table 3. Data-Mask (DQM) Command Truth Table†
COMMAND‡
STATE OF
BANK(S)
DQML
DQMU§
(n)
DATA IN
(n)
DATA OUT
(n + 2)
MNEMONIC
—
T = deac
and
B = deac
X
N/A
Hi-Z
—
—
T = actv
and
B = actv
( no access operation )¶
X
N/A
Hi-Z
—
Data-in enable
T = write
or
B = write
L
V
N/A
ENBL
Data-in mask
T = write
or
B = write
H
M
N/A
MASK
Data-out enable
T = read
or
B = read
L
N/A
V
ENBL
Data-out mask
T = read
or
B = read
H
N/A
Hi-Z
MASK
† For execution of these commands on cycle n:
– CKE (n) must be high, or
– tCESP must be satisfied for power-down exit, or
– tCESP and tRC must be satisfied for self-refresh exit, or
– tCES and nCLE must be satisfied for clock suspend exit.
CS(n), RAS(n), CAS(n), W(n), and A0 – A11 are don’t cares.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ DQML controls D 0 – D 7 and Q 0 – Q 7.
DQMU controls D 8 – D 15 and Q 8 – Q15.
¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
= CLK cycle number
L
= Logic low
H
= Logic high
X
= Don’t care, either logic low or logic high
V
= Valid
M
= Masked input data
N/A = Not applicable
T
= Bank T
B
= Bank B
actv = Activated
deac = Deactivated
write = Activated and accepting data inputs on cycle n
read = Activated and delivering data outputs on cycle (n + 2)
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5
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
burst sequence
All data for the ’626162 is written or read in a burst fashion, that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. After
the first access some of the subsequent accesses can be at preceding as well as succeeding column addresses,
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst (see Table 4 through Table 6). The length of the burst can be programmed to be 1, 2, 4,
8, or full-page ( 256 ) accesses (see the section on setting the mode register, page 9). After a read burst is
complete (as determined by the programmed-burst length), the outputs are in the high-impedance state until
the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1 – A0
DECIMAL
Serial
Interleave
6
BINARY
START
2ND
3RD
4TH
START
2ND
3RD
0
1
2
3
00
01
10
11
1
2
3
0
01
10
11
00
2
3
0
1
10
11
00
01
3
0
1
2
11
00
01
10
0
1
2
3
00
01
10
11
1
0
3
2
01
00
11
10
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
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4TH
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2 – A0
DECIMAL
BINARY
START
2ND
3RD
4TH
5TH
6TH
7TH
8TH
START
2ND
3RD
4TH
5TH
6TH
7TH
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
2
3
4
5
6
7
0
1
010
011
100
101
110
111
000
001
3
4
5
6
7
0
1
2
011
100
101
110
111
000
001
010
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
6
7
0
1
2
3
4
101
110
111
000
001
010
011
100
6
7
0
1
2
3
4
5
110
111
000
001
010
011
100
101
7
0
1
2
3
4
5
6
111
000
001
010
011
100
101
110
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
0
3
2
5
4
7
6
001
000
011
010
101
100
111
110
2
3
0
1
6
7
4
5
010
011
000
001
110
111
100
101
3
2
1
0
7
6
5
4
011
010
001
000
111
110
101
100
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
4
7
6
1
0
3
2
101
100
111
110
001
000
011
010
6
7
4
5
2
3
0
1
110
111
100
101
010
011
000
001
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
Serial
Interleave
8TH
latency
The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read
command (see the section on setting the mode register, page 9). This feature allows adjustment of the device
so that it operates using the capability to latch the data output. The delay between the READ command and
the beginning of the output burst is known as CAS latency. After the initial output cycle begins, the data burst
occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is restricted, based
on the maximum frequency rating of the ’626162.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the mode-register contents.
two-bank operation
The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Each bank then must be deactivated
before it can be activated again with a new row address. The bank-activate/row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can
be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank
(DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the
section on bank deactivation, page 8).
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7
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM, by activating one bank with a row address and, while the data stream is being accessed
to/from that bank, activating the second bank with another row address. When the data stream to or from the
first bank is complete, the data stream to or from the second bank can begin without interruption. After the
second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next
round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 28 is an example
of two-bank row-interleaving read bursts with automatic deactivate for a CAS latency of three and burst length
of eight.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 29 is an example of two-bank column-interleaving read bursts
for a CAS latency of three and burst length of two.
bank deactivation (precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 used to select the bank to be precharged as shown in Table 1.
A bank can be deactivated automatically by using A10 during a read or write command. If A10 is held high during
the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically upon
completion of the access burst. If A10 is held low during the entry of a read or write command, that bank remains
active following the burst. The read and write commands with automatic deactivation are signified as READ-P
and WRT-P.
chip select (CS)
CS can be used to select or deselect the ’626162 for command entry, which might be required for
multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge
of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select
operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use
of CS does not affect an access burst that is in progress; the DESL command can only restrict RAS, CAS, and
W input to the ’626162.
data mask
The mask command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. DQML controls DQ0 – DQ7, and
DQMU controls DQ8 – DQ15. The application of DQMx to a write burst has no latency (nDID = 0 cycle), but the
application of DQMx to a read burst has a latency of nDOD = 2 cycles. During a write burst, if DQMx is held high
on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst, if DQMx is held high on
the rising edge of CLK and nDOD cycles after that rising edge of CLK, the data-output is in the high-impedance
state. Figure 18 and Figure 32 through Figure 35 show examples of data-mask operation.
8
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the DQ bus occurring at the immediate next rising edge of
CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known as
a CLK-suspend operation, and its execution indicates a HOLD command. The device resumes operation from
the point when it was placed in suspension, beginning with the second rising edge of CLK after CKE returns
high.
If CKE is brought low when no read or write command is in progress, the device enters power-down mode. If
both banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum.
Power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. After
power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that data in the
device remains valid during the power-down mode, the self-refresh command ( SLFR) must be executed
concurrently with the power-down entry ( PDE) command. When exiting power-down mode, new commands
can be entered on the first CLK edge after CKE returns high, provided that the setup time (tCESP) is satisfied.
Table 2 shows the command configuration for a CLK-suspend/power-down operation. Figure 19, Figure 20,
and Figure 38 show examples of the procedure.
setting the mode register
The ’626162 contains a mode register that must be programmed with the CAS latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on the address lines A0 – A9. A logic 0 must be entered on A7 and A8, but A10 and A11 are don’t-care
entries for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length
is defined by A0 – A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid
addresses allow the mode register to be changed. If the addresses are not valid, the previous contents of the
mode register remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the
input mode word valid on A0 – A9 on the rising edge of CLK (see Table 1). The MRS command can be executed
only when both banks are deactivated.
A11
A10
A9
Reserved
A8
A7
0
0
A6
A5
A4
A3
A2
A1
A0
0 = Serial
1 = Interleave
(burst type)
REGISTER
BIT A9
Write Burst
L
Length
th
0
A2 – A0
1
1
REGISTER
BITS†
A6
A5
A4
0
0
1
1
0
1
CAS
‡
l t
latency
2
3
REGISTER
BITS†
BURST LENGTH
A2
A1
A0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
4
8
256
† All other combinations are reserved.
‡ See timing requirements for minimum valid read latencies based on maximum frequency rating.
Figure 1. Mode-Register Programming
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9
TMS626162
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
refresh
The ’626162 must be refreshed at intervals not exceeding tREF (see timing requirements) or data cannot be
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, 4 096
auto-refresh (REFR) commands, or by placing the device in self-refresh mode. Regardless of the method used,
refresh must be accomplished before tREF has expired.
auto refresh (REFR)
Before performing a REFR, both banks must be deactivated (placed in precharge). To enter a REFR command,
RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The refresh address
is generated internally such that, after 4 096 REFR commands, both banks of the ’626162 have been refreshed.
The external address and bank select (A11) are ignored. The execution of a REFR command automatically
deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only
commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not
necessarily have to be consecutive, but all 4 096 must be completed before tREF expires.
self refresh (SLFR)
To enter self refresh, both banks of the ’626162 must be deactivated and then a self-refresh (SLFR) command
must be executed (see Table 2). The SLFR command is identical to the REFR command, except that CKE is
low. For proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK that RAS and
CAS are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, all
refreshing signals are generated internally for both banks with all external signals (except CKE) being ignored.
Data is retained by the device automatically for an indefinite period when power is maintained, and power
consumption is reduced to a minimum. To exit self-refresh mode, CKE must be brought high. New commands
are issued after tRC has expired. If CLK is made inactive during self refresh, it must be returned to an active and
stable condition before CKE is brought high to exit self refresh (see Figure 21).
Upon exiting self refresh, the device must begin the normal-refresh scheme immediately. If the burst-refresh
scheme is used, then 4 096 REFR commands must be executed before continuing with normal device
operations. If a distributed-refresh scheme utilizing auto refresh is used (for example, two rows every 32 µs),
the first set of refreshes must be performed before continuing with normal device operation. This ensures that
the SDRAM is fully refreshed.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of READ-P or WRT-P
operations is not supported.
10
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
Table 7. Read-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding-READ (READ-P) command is met
and new output cycles begin (see Figure 2).
READ, READ-P
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQMx must
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD-1), nCCD, and
(nCCD+1), assuming that there is any output on these cycles (see Figure 3).
The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes, whichever
occurs first (see Figure 4).
WRT, WRT-P
DEAC, DCAB
The DQ bus is in the high-impedance state when nBSD cycles are satisfied or when the read burst completes, whichever
occurs first. The bank remains active. A new read or write command cannot be entered for at least two cycles after the
STOP command (see Figure 5).
STOP
nCCD = One Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
C0
C1
C1 + 1
C1 + 2
a) INTERRUPTED ON ODD CYCLES
nCCD = Two Cycles
CLK
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
Output Burst for the
Interrupting READ
Command Begins Here
C0
C0 + 1
C1
C1 + 1
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples, assume CAS latency = 3, and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
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TMS626162
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
nCCD = Five Cycles
CLK
Interrupting
WRT Command
READ Command
DQ
Q
D
See Note B
DQMx
NOTES: A. For the purposes of this example, assume CAS latency = 3, and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (nCCD – 1), nCCD, and (nCDD + 1).
Figure 3. Read Burst Interrupted by Write Command
nCCD = Two Cycles
nHZP
CLK
Interrupting
DEAC/DCAB
Command
READ Command
Q
DQ
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
nCCD = Two Cycles
nBSD
CLK
READ Command
Interrupting
STOP Command
NEW Command
DQ
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 5. Read Burst Interrupt by STOP Command
12
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D
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data in on previous cycle is written. No further data in is accepted (see Figure 6).
WRT, WRT-P
The new WRT (WRT-P) command and data in immediately supersede the write burst in progress
(see Figure 7).
DEAC, DCAB
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
mask the DQ bus so that an interrupt does not violate the write-recovery specification (tWR ) (see Figure 8).
STOP
The data on the input pins at the time of the burst-STOP command is not written; no further data is accepted.
The bank remains active. A new read or write command cannot be entered for at least nBSD cycles after the
STOP command (see Figure 9).
nCCD = One Cycle
CLK
WRT
Command
DQ
READ
Command
D
Q
Q
Q
Q
Q
a) INTERRUPTED ON ODD CYCLES
nCCD = Two Cycles
CLK
WRT Command
DQ
D
READ Command
D
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples, assume CAS latency = 3, burst length = 4.
Figure 6. Write Burst Interrupted by Read Command
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13
TMS626162
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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interrupted bursts (continued)
nCCD = Two Cycles
CLK
WRT Command
at
Column
Address C0
DQ
C0
Interrupting
WRT Command
at Column Address C1
C0 + 1
C1
C1 + 1
C1 + 2
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by Write Command
nCCD = Three Cycles
CLK
WRT Command
DQ
D
Interrupting
DEAC or DCAB
Command
D
Ignored
Ignored
tWR
DQMx
NOTE A: For this example, assume burst length = 4.
Figure 8. Write Burst Interrupted by DEAC/DCAB Command
nCCD = Two Cycles
nBSD
CLK
Interrupting
STOP Command
WRT Command
DQ
D
D
Ignored
New Command
Ignored
NOTE A: For this example, assume burst length = 4.
Figure 9. Write Burst Interrupted by STOP Command
14
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C1 + 3
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
power up
Device initialization should be performed after a power up to the full VCC level. After power is established, a
200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the
device initialization.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
VCCQ
Supply voltage
3
3.3
3.6
V
Supply voltage for output drivers
3
3.3
3.6
V
VSS
VSSQ
Supply voltage
0
Supply voltage for output drivers
0
VIH
VIL
High-level input voltage
2
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
NOTE 2: VIL MIN = 1.5 V ac (pulsewidth
– 0.3
0
v 5 ns)
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V
V
VCC + 0.3
0.8
V
70
°C
V
15
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 2 mA
IOL = 2 mA
II
IO
Input current (leakage)
0 V ≤ VI ≤ VCC + 0.3 V,
All other pins = 0 V to VCC
Output current (leakage)
0 V ≤ VO ≤ VCC + 0.3 V,
Output disabled
w
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Operating current
ICC2P
ICC2PS
Precharge
g standby
y current in power-down
mode
CKE
Precharge
g standby
y current in
non-power-down mode
CKE
ICC3P
ICC3PS
Precharge
g standbyy current in power-down
mode
CKE
ICC3N
ICC3NS
Precharge
g standby
y current in
non-power-down mode
ICC4
Burst current
ICC5
Auto refresh current
Auto-refresh
v
MIN
MAX
2.4
Burst length
g = 1,, tRC
tRC MIN
IOH/IOL = 0 mA, one bank activated (see Note 4)
ICC1
ICC2N
ICC2NS
’626162-12A†
TEST CONDITIONS
’626162-12
MIN
MAX
2.4
UNIT
V
0.4
0.4
V
±10
±10
µA
±10
±10
µA
CAS latency = 2
85
80
mA
CAS latency = 3
105
105
mA
2
2
mA
2
2
mA
30
30
mA
2
2
mA
8
8
mA
VIL MAX, tCK = 15 ns (see Note 5)
CKE & CLK
VIL MAX, tCK = ∞ (see Note 6)
v
w VIH MIN, tCK = 15 ns (see Note 5)
v VIL MAX, tCK = 15 ns (see Note 5)
CKE & CLK v VIL MAX, tCK = ∞ (see Note 6)
CKE w VIH MIN, tCK = 15 ns (see Note 5)
CKE w VIH MIN, CLK v VIL MAX tCK = ∞ (see Note 6)
8
8
mA
35
35
mA
10
10
mA
Page
g burst,, IOH/IOL = 0 mA
All banks activated, nCCD = one cycle (see Note 7)
CAS latency = 2
140
130
mA
CAS latency = 3
170
170
mA
w tRC MIN
CKE v VIL MAX
CAS latency = 2
75
70
mA
CAS latency = 3
85
85
mA
2
2
µA
tRC
ICC6
Self-refresh current
† –12A-speed device is supported only at –5/+10% VCC.
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Control, DQ, and address inputs change state only twice during tRC.
5. Control, DQ, and address inputs change state only once every 30 ns.
6. Control, DQ, and address inputs do not change (stable).
7. Control, DQ, and address inputs change state only once every cycle.
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
PARAMETER
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
16
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted)
(see Note 3)
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 8)
MIN
MAX
UNIT
Ci(S)
Input capacitance, CLK input
5
pF
Ci(AC)
Input capacitance, address and control inputs: A0 – A11, CS, DQMx, RAS, CAS, W
5
pF
Ci(E)
Input capacitance, CKE input
5
pF
Co
Output capacitance
8
pF
NOTE 8: VCC = 3.3 ± 0.3 V and bias on pins under test is 0 V.
ac timing requirements over recommended ranges of supply voltage and operating free-air
temperature†‡
’626162-12A§
PARAMETER
MIN
MAX
’626162-12
MIN
MAX
UNIT
tCK2
tCK3
Cycle time, CLK
CAS latency = 2
15
18
ns
Cycle time, CLK
CAS latency = 3
12
12
ns
tCH
tCL
Pulse duration, CLK high
4
4
ns
tAC2
tAC3
Access time, CLK high to data out (see Note 9)
CAS latency = 2
9
10
ns
Access time, CLK high to data out (see Note 9)
CAS latency = 3
9
9
ns
tOH
tLZ
Hold time, CLK high to data out
3
3
ns
Delay time, CLK high to DQ in low-impedance state (see Note 10)
3
3
ns
tHZ
tIS
Delay time, CLK high to DQ in high-impedance state (see Note 11)
Setup time, address, control, and data input
3
3
ns
tIH
tCESP
Hold time, address, control, and data input
1
1.5
ns
Power down/self-refresh exit time (see Note 12)
10
tRAS
Delay time, ACTV command to DEAC or DCAB command
60
tRC
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR
command
90
108
ns
tRCD
Delay time ACTV command to READ, READ-P, WRT, or WRT-P command
(see Note 13)
30
30
ns
tRP
tRRD
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
30
36
ns
Delay time, ACTV command in one banki to ACTV command in the other bank
24
24
ns
tRSA
tAPR
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
24
24
ns
tAPW
tWR
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command
60
Delay time, final data in of WRT operation to DEAC or DCAB command
15
Pulse duration, CLK low
4
4
10
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command
ns
10
10
100000
72
tRP – (CL –1) * tCK
60
20
ns
ns
100000
ns
ns
ns
ns
tT
Transition time
1
5
1
5
ns
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK, unless otherwise noted.
§ –12A-speed device is supported only at – 5 / + 10% VCC .
NOTES: 9. tAC is referenced from the rising transition of CLK that is previous to the data-out cycle. For example, the first data out tAC is
referenced from the rising transition of CLK that is CAS latency – one cycle after the READ command. An access time is measured
at output reference level 1.4 V.
10. tLZ is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command.
11. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
12. See Figure 20 and Figure 21.
13. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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17
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
ac timing requirements over recommended ranges of supply voltage and operating free-air
temperature†‡ (continued)
’626162-12A§
PARAMETER
MIN
MAX
’626162-12
MIN
64
MAX
tREF
nCCD
Refresh interval
Delay time, READ or WRT command to an interrupting command
1
nCDD
nCLE
Delay time, CS low or high to input enabled or inhibited
0
0
0
0
cycle
Delay time, CKE high or low to CLK enabled or disabled
1
1
1
1
cycle
nCWL
nDID
Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P
1
Delay time, ENBL or MASK command to enabled or masked data in
0
0
0
0
cycle
nDOD
Delay time, ENBL or MASK command to enabled or masked data out
2
2
2
2
cycle
nHZP2
Delay time, DEAC or DCAB, command to DQ in high-impedance
state
CAS latency = 2
2
2
cycle
nHZP3
Delay time, DEAC or DCAB, command to DQ in high-impedance
state
CAS latency = 3
3
3
cycle
0
cycle
1
cycle
nWCD Delay time, WRT command to first data in
nBSD
Delay time, STOP command to READ or WRT command
† See Parameter Measurement Information for load circuits.
‡ All references are made to the rising transition of CLK, unless otherwise noted.
§ –12A-speed device is supported only at – 5 / + 10% VCC .
18
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0
64
UNIT
1
1
0
1
0
ms
cycle
cycle
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level should
be changed to VIH MIN and VIL MAX instead of the midpoint level. All specifications referring to READ
commands are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT
commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to
consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
1.4 V
RL = 50 Ω
ZO = 50 Ω
Output
Under Test
CL = 50 pF
Figure 10. LVTTL-Load Circuit
tCK
tCH
CLK
tT
tCL
tiS
tT
tiH
DQ, A0 – A11, CS, RAS,
CAS, W, DQMx, CKE
tT
tiH
tiS, tCESP
DQ, A0 – A11, CS, RAS,
CAS, W, DQMx, CKE
tT
Figure 11. Input-Attribute Parameters
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19
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CAS latency
CLK
ACTV
Command
tAC
READ
Command
tHZ
tLZ
tOH
DQ
Figure 12. Output Parameters
READ, WRT
nCCD
READ, READ-P, WRT, WRT-P, DEAC, DCAB
DESL
nCDD
Command Disable
ACTV
tRAS
DEAC, DCAB
ACTV, REFR, SELF-REFRESH EXIT
ACTV
DEAC, DCAB
ACTV, MRS, REFR, SLFR
tRC
READ, READ-P, WRT, WRT-P
tRCD
ACTV, MRS, REFR, SLFR
tRP
ACTV
tRRD
ACTV (different bank)
MRS
tRSA
ACTV, MRS
Figure 13. Command-to-Command Parameters
nHZP
CLK
READ
Command
DEAC or
DCAB
Command
DQ
Q
tHZ
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 14. Read Followed by Deactivate
20
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Q
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
tAPR
CLK
READ-P
Command
ACTV, MRS,
REFR, or SLFR
Command
Final Data Out
DQ
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 15. Read With Auto-Deactivate
nCWL
tWR
CLK
WRT
Command
DQ
DEAC or DCAB
Command
WRT
Command
D
D
NOTE A: For this example, assume burst length = 1.
Figure 16. Write Followed By Deactivate
nCWL
tAPW
CLK
WRT
Command
DQ
WRT-P
Command
D
ACTV, MRS,
REFR, or SLFR
Command
D
Figure 17. Write With Auto-Deactivate
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21
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
nDOD
tRWL
nDOD
CLK
DEAC or
DCAB
Command
WRT
Command
READ
Command
DQ
D
Ignored
Ignored
ENBL
Command
MASK
Command
MASK
Command
Q
ENBL
Command
MASK
Command
MASK
Command
MASK
Command
Ignored
DQMx
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 18. DQ Masking
nCLE
nCLE
CLK
DQ
DQ
DQ
DQ
DQ
tiS
tiS
tiH
tiH
CKE
Figure 19. CLK-Suspend Operation
22
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
Exit
Power-Down
Mode If tCESP Is
Satisfied (New
Command)
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
CKE
tCESP
tiH
tiS
CLK
Last Data-In
WRT
(WRT-P)
Operation
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
DESL or
NOOP
Command
Only If tCESP
Is Not
Satisfied
Exit Power-Down
Mode (New
Command)
CKE
tiH
tCESP
tiS
Figure 20. Power-Down Operation
POST OFFICE BOX 1443
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23
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
SLFR Command
Both Banks
Deactivated
Exit SLFR
if tCESP Is
Satisfied
CLK Is Don’t
Care, But
Must
Be Stable
Before
CKE high
ACTV, MRS,
or REFR
Command
DESL or NOOP
Command
Only Until
tRC Is Satisfied
CKE
tRC
tCESP
tiH
tiS
CLK
SLFR Command
Both Banks
Deactivated
tCESP NotYet
Satisfied
CLK is Don’t
Care, But
Must
Be Stable
Before
CKE High
ACTV, MRS,
or REFR
Command
DESL or
NOOP
Only Until
tRC Is
Satisfied
CKE
tRC
tCESP
tiH
tiS
Figure 21. Self-Refresh Operation
24
Exit
SLFR
POST OFFICE BOX 1443
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ACTV T
READ T
DEAC T
CLK
DQ
a
b
c
d
DQMx
W
R0
A10
A11
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
Figure 22. Read Burst (CAS latency = 3, burst length = 4)
25
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
PARAMETER MEASUREMENT INFORMATION
RAS
DEAC T
CLK
a
DQ
b
c
d
e
f
g
h
DQMx
RAS
PARAMETER MEASUREMENT INFORMATION
CAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
R0
A10
A11
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum tRCD and tWR for the ’626162-12 at 83 MHz.
Figure 23. Write Burst (burst length = 8)
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
WRT T
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
26
ACTV T
ACTV B
WRT B
READ B
DEAC B
CLK
DQ
a
c
b
d
DQMx
RAS
A10
R0
A11
A0 – A9
R0
C0
C1
CS
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
D
Q
B
B
R0
R0
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1 + 1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
Figure 24. Write-Read Burst (CAS latency = 3, burst length = 2)
27
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
CKE
TMS626162
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
WRT-P T
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
DQMx
RAS
CAS
W
R0
A11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
R0
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
i
j
k
C1
C1 + 1 C1 + 2
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
l
m
n
o
p
C1 + 3
C1 + 4
C1 + 5
C1 + 6
C1 + 7
Figure 25. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
PARAMETER MEASUREMENT INFORMATION
A10
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ T
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
28
ACTV T
ACTV T
READ T
WRT-P T
CLK
DQ
a
b
c
d
e
f
g
h
i
DQMx
RAS
CAS
W
R0
A11
R0
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
BURST CYCLE†
i
C1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
Figure 26. Read Burst – Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
29
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
PARAMETER MEASUREMENT INFORMATION
A10
DQ0 – DQ15
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+253 n+254 n+255
DQMx
RAS
CAS
W
A10
R0
A0 – A9
C0
R0
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
BURST CYCLE
a
b
c
d
e
f
g
h
†
C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
i
j
k
l
m
n
o
Q
B
R0
† Column-address sequence depends on programmed burst type and starting column address C0.
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
Figure 27. Read Burst – Full Page (CAS latency = 3, burst length = 256)
p
q
r
s
.
255
.
PARAMETER MEASUREMENT INFORMATION
A11
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ- P B
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
30
ACTV B
CLK
ACTV T
ACTV B
READ- P T
ACTV T
ACTV B
READ- P B
READ- P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
A10
R1
R0
R2
R3
C0
R0
R1
C1
R2
C2
R3
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
Q
Q
Q
B
T
B
R0
R1
R2
C0
BURST CYCLE†
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
C2 + 1 C2 + 2 .
.
C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
C1
C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7
C2
† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
31
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
Figure 28. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (CAS latency = 3, burst length = 8)
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A0 – A9
PARAMETER MEASUREMENT INFORMATION
A11
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQMx
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
R1
R0
R1
A11
A0 – A9
C1
C0
C2
C3
C4
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
Q
Q
Q
.
B
T
B
...
R0
R1
R0
...
C0
C0 + 1
BURST CYCLE †
c
d
C1
C1 + 1
e
f
C2
C2 + 1
...
...
...
...
† Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).
Figure 29. Two-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
PARAMETER MEASUREMENT INFORMATION
CAS
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
READ T
READ B
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
32
READ T
ACTV T
ACTV B
WRT T
ACTV T
ACTV B
DEAC T
DEAC B
READ B
CLK
a
DQ
b
c
d
e
f
g
h
DQMx
RAS
A10
R0
R1
A11
C0
R0
A0 – A9
R1
C1
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
B
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1. (Refer to Table 5.)
NOTE A: This example illustrates minimum tRCD and tWR for the ’626162-12 at 83 MHz.
Figure 30. Read-Burst Bank B, Write-Burst Bank T (CAS latency = 3, burst length = 4)
33
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
BURST
TYPE
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
READ- P B
CLK
DQ
a
b
c
e
d
f
g
DQMx
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
A10
R0
R1
R0
R1
A11
A0 – A9
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
D
Q
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE †
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum nCWL for the ’626162-12 at 83 MHz.
Figure 31. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (CAS latency = 3, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
WRT- P T
ACTV B
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
34
ACTV T
ACTV T
WRT T
READ T
DCAB
CLK
a
b
c
e
d
f
g
h
DQ
DQMx
RAS
R0
A10
A11
R0
A0 – A9
C1
C0
CS
CKE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD for the ’626162-12 at 83 MHz.
Figure 32. Data Mask (CAS latency = 3, burst length = 4)
35
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
BURST
TYPE
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
PARAMETER MEASUREMENT INFORMATION
CAS
READ B
READ T
READ T
READ B
READ B
CLK
DQ0 – DQ7
a
b
c
d
e
f
DQML
High Impedance
DQ8 – DQ15
DQMU
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
W
A10
R0
R1
R0
R1
A11
A0 – A9
C1
C0
C2
C3
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
Q
Q
Q
Q
T
B
T
B
R0
R1
R0
R1
C0
C0 + 1
BURST CYCLE†
c
d
C1
C1+1
e
f
C2
C1+1
g
h
C3
C3+ 1
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
Figure 33. Data Mask With Byte Control (CAS latency = 3, burst length = 2)
C4
PARAMETER MEASUREMENT INFORMATION
RAS
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
ACTV T
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
36
ACTV B
ACTV T
READ B
ACTV B
DEAC B
WRT T
DEAC T
CLK
e
DQ0 – DQ7
f
g
h
DQML
a
DQ8 – DQ15
b
c
d
RAS
W
A10
R1
R0
A11
R0
A0 – A9
R1
C0
C1
CS
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD read burst, and a minimum tWR write burst for the ’626162-12 at 83 MHz
Figure 34. Data Mask With Byte Control (CAS latency = 3, burst length = 4)
37
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
CKE
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
PARAMETER MEASUREMENT INFORMATION
DQMU
ACTV B
WRT B
DCAB
CLK
DQ0 – DQ7
a
b
c
d
a
b
c
d
f
h
DQML
DQ8 – DQ15
e
f
g
h
DQMU
PARAMETER MEASUREMENT INFORMATION
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CAS
W
R1
R0
A10
A11
R0
A0 – A9
R1
C0
C1
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
D
T
B
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum tRCD and tWR for the ’626162-12 at 83 MHz.
Figure 35. Data Mask With Cycle-by-Cycle Byte Control (CAS latency = 3, burst length = 4)
TMS626162
524288 BY 16-BIT BY 2-BANK
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READ T
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
38
ACTV T
REFR
ACTV T
READ T
DEAC T
REFR
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
R0
A10
R0
A0 – A9
C0
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
Figure 36. Refresh Cycles (CAS latency = 3, burst length = 4)
39
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim tRC and tRCD for the ’626162-12 at 83 MHz.
TMS626162
524288 BY 16-BIT BY 2-BANK
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
A11
PARAMETER MEASUREMENT INFORMATION
W
WRT-P B
CLK
DQ
a
b
c
d
DQMx
RAS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
W
R0
A10
See Note B
A11
See Note B
A0 – A9
R0
C0
See Note B
CS
CKE
BURST
TYPE
BANK
ROW
(D/Q)
(B/ T )
ADDR
a
b
c
d
D
B
R0
C0
C0 + 1
C0 + 2
C0 + 3
BURST CYCLE†
† Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum tRP, tRSA, and tRCD for the ’626162-12 at 83 MHz.
B. Refer to Figure 1.
Figure 37. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(CAS latency = 2, burst length = 4)
PARAMETER MEASUREMENT INFORMATION
CAS
TMS626162
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ACTV B
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
40
MRS
DCAB
ACTV T
READ T
WRT-P T
HOLD
HOLD
PDE
CLK
DQ0
a
b
d
c
e
f
g
h
DQMx
RAS
CAS
A11
R0
A0 – A9
C1
C0
CS
CKE
BURSTBANK
TYPE
ROW
BURST CYCLE†
(B/ T )
ADDR
a
b
c
d
Q
D
T
T
R0
R1
C0
C0 + 1
C0 + 2
C0 + 3
e
f
g
h
C1
C1 + 1
C1 + 2
C1 + 3
† Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 38. CLK Suspend (HOLD) During Read Burst and Write Burst (CAS latency = 3, burst length = 4)
41
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
(D/Q)
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
R0
A10
PARAMETER MEASUREMENT INFORMATION
W
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
device symbolization
TI
-SS
Speed Code (-12A, -12)
TMS626162 DGE
Package Code
W
B
Y
M
LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
42
POST OFFICE BOX 1443
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TMS626162
524288-WORD BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
MECHANICAL DATA
DGE (R-PDSO-G50)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.012 (0,30)
0.031 (0,80)
50
0.006 (0,16) M
26
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
25
0.006 (0,15) NOM
0.829 (21,05)
0.821 (20,85)
Gage Plane
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.000 (0,00) MIN
0.004 (0,10)
4040070-5 / C 12/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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