NJRC NJW4800

NJW4800
30V/4A Half Bridge Driver
GENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW4800 is a general purpose, half bridge power driver
capable of supplying 4A current. The internal gate driver drives
high-side/low-side power MOSFET; therefore, it has fast switching.
Additionally, it has protection features such as over current
protection and thermal shutdown.
And in the case of failure, it can output a fault flag.
It is suitable for power switching applications of DSP/micro
controller.
NJW4800GM1
FEATURES
● Output Switch Current
±4A
● Operating Voltage
7.5V to 30V
● Up to 1.2MHz Switching Frequency
● Thermal Shut Down
● Over Current Protection
● Under Voltage Lockouts
● Fault Indicator Output
● Stand-by Current
IQOFF =3µA typ.
● High Heat Radiation Package
● Package Outline
HSOP8
PIN CONFIGURATION
1
8
2
7
3
6
4
5
Exposed PAD on
backside connect to GND
Ver.2010-09-29
PIN FUNCTION
1. PWM
2. VDD
3. OUT
4. GND
5. BS
6. STBY
7. REG
8. FLT
-1-
NJW4800
BLOCK DIAGRAM
RFLT
FLT
CREG
VDD
REG
Over current
Protection
BS
Regulator (5V)
Thermal
Shut Down
High Side
Gate Driver
Level Shift
CBS
Under Voltage
Lock Out
OUT
PWM
Low Side
Gate Driver
Input Control
STBY
100kΩ
750kΩ
GND
-2-
Ver.2010-09-29
NJW4800
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply Voltage
V+
VSTBY
Input Voltage
VPWM
FLT pin Voltage
VFLT
BS pin Voltage
VBS
BS-OUT pin Voltage
VBS–OUT
Power Dissipation
PD
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
Tj
Topr
Tstg
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
Operating Voltage
Vopr
7.5
Output Switch Current
IOM
0
VSTBY,
Input Voltage
0
VPWM
FLT pin Voltage
VFLT
0
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
Junction-toθja
Ambient Temperature
ψjt
Junction-to-Case
MAXIMUM RATINGS
35
UNIT
V
-0.3 ∼ 6
V
-0.3 ∼ 6
40
-0.3 ∼ 6
900 (*1)
3100 (*2)
-40 ~ +150
-40 ~ +85
-50 ~ +150
V
V
V
(Ta=25°C)
REMARKS
VDD-GND pin
STBY,
PWM-GND pin
FLT-GND pin
BS-GND pin
BS-OUT pin
W
–
°C
°C
°C
–
–
–
TYP.
–
–
MAX.
30
4
UNIT
V
A
–
5.5
V
–
VREG1
V
THERMAL RESISTANCE
139 (*1)
40 (*2)
19 (*1)
3.7 (*2)
(Ta=25°C)
REMARKS
VDD-GND pin
OUT pin
STBY,
PWM-GND pin
FLT-GND pin
(Ta=25°C)
UNIT
°C/W
°C/W
(*1): Mounted on glass epoxy board based on EIA/JEDEC. (76.2 × 114.3 × 1.6mm: 2-Layers)
(*2): Mounted on glass epoxy board based on EIA/JEDEC.
(76.2 × 114.3 × 1.6mm: 4-Layers Internal foil area: 74.2 × 74.2mm)
Power Dissipation vs. Ambient Temperature
D
Power Dissipation P (W)
4
3.5
At on 4 layer PC Board
3
2.5
2
1.5
1
At on 2 layer PC Board
0.5
0
-50
Ver.2010-09-29
(Topr=-40~+85oC, Tj= ~150oC)
-25
0
25
50
75
100
o
Ambient Temperature Ta ( C)
-3-
NJW4800
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1µF, CREG=1µF, Ta=25°C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
General Characteristics
Quiescent Current 1 (Operating)
Quiescent Current 2 (Switching)
Quiescent Current 3 (Standby)
IQ1
IQ2
IQOFF
VPWM=0V
VPWM=0V to 3V, fPWM=1.2MHz
VSTBY=5.5V, VPWM=0V
–
–
–
1
9
3
2
14
10
mA
mA
µA
RDSH
RDSL
ILIMIT
tr
tf
Dt
td_ON
td_OFF
IOSOURCE=1A, VBS–OUT=5V
IOSINK=1A
High-side and Low-side
VPWM=0V to 3V
VPWM=3V to 0V
VPWM=0V to 3V
VPWM=0V to 3V
VPWM=3V to 0V
–
–
4
–
–
–
–
–
0.25
0.25
5.5
3
3
20
60
60
0.45
0.45
7
–
–
–
–
–
Ω
Ω
A
ns
ns
ns
ns
ns
VPDOV
V+=5.7V, IORH=1A
–
0.85
1.1
V
VPDGO
V+=5.7V, IORL=1A
–
0.85
1.1
V
V =5.7V, VSTBY=5.5V
V+=30V, VSTBY=5.5V,
VOUT=0V
50
100
200
kΩ
–
–
1
µA
V+=5.7V, VOUT=0V
–
30
60
µA
VIHSTBY
2.4
–
5.5
V
VILSTBY
0
–
0.8
V
VPWM=5.5V
VPWM=5.5V
–
500
2.2
0
–
140
0.01
750
–
–
0.01
300
1
1000
5.5
0.9
1
–
µA
kΩ
V
V
µA
µs
V+ = L → H
V+ = H → L
VUVLO2-VUVLO1
5.9
5.65
–
6.6
6.35
0.25
7.3
7.05
–
V
V
V
Output Block
High-side SW ON Resistance
Low-side SW ON Resistance
Over Current Limit
Output Rise Time
Output Fall Time
Dead Time
PWM Rise Delay Time
PWM Fall Delay Time
OUT pin – VDD pin
Potential Difference
GND pin – OUT pin
Potential Difference
Output Pull-down Resistance
Output Leak Current
(High Side SW OFF)
OUT pin Output Current
(FLT Signal Output )
Input Circuit Block
STBY pin High Voltage
(Standby Mode)
STBY pin Low Voltage
(Operating Mode)
STBY pin Input Current
STBY Pull-down Resistance
PWM pin High Voltage
PWM pin Low Voltage
PWM pin Input Current
Continuous Output High Time
RPD
IOLEAKOUT
IO-FLT
IISTBY
IISTBY
VIHPWM
VILPWM
IIPWM
tHPWM
Under Voltage Lockout (UVLO) Block
UVLO Release Voltage
VUVLO2
UVLO Operation Voltage
VUVLO1
UVLO Hysteresis Voltage
∆VUVLO
-4-
+
VSTBY=5.5V
Ver.2010-09-29
NJW4800
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=12V, VSTBY=0V, CBS=0.1µF, CREG=1µF, Ta=25°C)
PARAMETER
Internal Power Supply Circuit
Output Voltage 1
Line Regulation
Load Regulation
REG pin Output Current
Fault Function (FLT pin)
Low Level Output Voltage
OFF Leak Current
SYMBOL
TEST CONDITION
VREG1
IREG=0mA
∆VREG–VDD V+=8 ∼ 30V, IREG=0mA
∆VREG–IO IREG=0 ∼ 20mA
VREG1×0.95,
IOREG
Input signal=500kHz
VLFLT
IOLEAKFLT
IFLT=500µA
VFLT=5.5V
MIN.
TYP.
MAX.
UNIT
4.75
–
–
5
2
20
5.25
20
50
V
mV
mV
30
–
–
mA
–
–
0.25
–
0.5
1
V
µA
PIN OPERATION TABLE
INPUT
OUTPUT
Mode
High-side
Low-side
PWM
STBY
VDD
FLT
SW
SW
ON
OFF
ON
Normal
L
L
V+ ≥ VRUVLO
ON
ON (*3)
OFF
Normal
H
L
V+ ≥ VRUVLO
L
H
–
OFF
OFF
OFF
Stand-by
H
H
–
OFF
OFF
OFF
Stand-by
+
L
L
V < VDUVLO
OFF
OFF
OFF
UVLO
H
L
V+ < VDUVLO
OFF
OFF
OFF
UVLO
(*3) If PWM=H continues by tHPWM or more and is input, it becomes low-side SW=ON during tHPWM/128.
INPUT
Tj
IOUT
FLT
Tj >150°C
–
–
IOUT ≥ IOM
OFF
OFF
Ver.2010-09-29
OUTPUT
High-side
SW
OFF
OFF
Low-side
SW
OFF
OFF
Mode
TSD
OCP
-5-
NJW4800
TIMING CHART
Fig1. Output Rise/Fall Time, PWM Rise/Fall Delay Time
50%
50%
PWM
tr
tf
90%
90%
50%
OUT
50%
10%
10%
td_ON
td_OFF
Fig2. Maximum Continuous Output Time (High-level)
PWM
tHPWM/128
OUT
tHPWM
Fig3. Switching and Dead Time
ON
High Side
SW
OFF
ON
Low Side
SW
OFF
Dead Time 50ns typ.
-6-
Ver.2010-09-29
NJW4800
TYPICAL APPLICATIONS
V
RFLT
=47kΩ
CREG
=1µF
+
CP=1µF
VDD
REG
CIN=100µF
BS
CBS=0.1µF
FLT
NJW4800
FAULT
PWM
Controller
(NJU7600)
PWM Signal
PWM
VOUT
OUT
STBY
GND
Stand-by
Synchronous PWM step down switching regulator
+
V
CREG
=1µF
RFLT
=47kΩ
REG
CP=1µF
VDD
CIN=100µF
BS
CBS=0.1µF
FAULT
FLT
PWM
Signal
PWM
Stand-by
STBY
NJW4800
OUT
GND
Class-D single ended audio amplifier
V
V+
CP=1µF
VDD
REG
FAULT
PWM Signal
PWM
Signal
OUT
STBY
GND
CIN=100µF
BS
PWM Signal
NJW4800
PWM
OUT
GND
Stand-by
4
V
V+
REG
FLT
FAULT
CP=1µF
VDD
+
CP=1µF
CIN=100µF
REG
BS
FLT
NJW4800
PWM
STBY
FAULT
OUT
GND
Stand-by
Class-D full bridge audio amplifier
Ver.2010-09-29
FAULT
STBY
Stand-by
PWM Signal
VDD
REG
NJW4800
PWM
CP=1µF
BS
FLT
FLT
Digital
Audio
Signal
+
CIN=100µF
PWM Signal
VDD
M
BS
NJW4800
PWM
STBY
CIN=100µF
OUT
GND
Stand-by
Full bridge motor driver
-7-
NJW4800
CHARACTERISTICS
Over Current Limit vs. Temperature
(A)
CBS=0.47µF
LIMIT
CREG=1µF
Over Current Limit I
6
5.5
5
4.5
6.5
CBS=0.47 µF
CREG=1 µF
6
5.5
5
4.5
4
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
High-side SW ON Resistance vs. Temperature
(I OSOURCE=1A, VBS-OUT=5V)
0.5
Low-side SW ON Resistance vs. Temperature
DSL
(Ω)
4
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
0.4
0.3
0.2
0.1
0
-50 -25
0
25
50
75 100 125 150
o
Ambient Temperature Ta ( C)
-8-
(Low-side, V+=12V)
7
Low-side SW ON Resistance R
High-side SW ON Resistance R
DSH
(Ω)
Over Current Limit I
LIMIT
(A)
7
6.5
Over Current Limit vs. Temperature
(High-side, V+=12V)
0.5
(V+=12V, IOSINK=1A)
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
Ver.2010-09-29
NJW4800
Continuous Output High Time vs. Temperature
400
CREG=1 µF
REG1
380
CREG=1 µF
(V)
CBS=0.47 µF
360
340
320
300
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
5
4.9
4.8
4.7
7
V
RUVLO
6.6
6.4
V
DUVLO
6
5.8
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
VILPWM
1.2
1
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
Quiescent Current I
1.4
VILSTBY
1.2
Frequency vs. Operating Voltage
Q
IHPWM
IHSTBY
1
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
(mA)
V
V
1.4
(VPWM=0V to 3V, Ta=25oC)
20
1.6
Ver.2010-09-29
(V+=12V)
1.6
(V+=12V)
(V)
PWM
PWM pin Voltage V
1.8
100
1.8
PWM pin Voltage vs. Temperature
2
20
40
60
80
Output Current I REG (mA)
2
STBY pin Voltage VSTBY (V)
UVLO Voltage V
UVLO
(V)
7.2
6.2
0
STBY pin Voltage vs. Temperature
Under Voltage Lockout Block vs. Temperature
6.8
(V+=12V, Ta=25oC)
5.1
Output Voltage 1 V
Continuous Output High Time t
Internal Power Supply Circuit Load Regulation
(V+=12V, VPWM=3V)
HWM
(µs)
CHARACTERISTICS
CBS=0.47 µF
CREG=1 µF
15
V+=30V
V+=12V
10
5
V+=7.5V
0
0
200
400 600 800 1000 1200
Frequency fPWM (kHz)
-9-
NJW4800
CHARACTERISTICS
Quiescent Current 1 vs. Temperature
2
(mA)
(VPWM=0V, Ta=25oC)
CBS=0.47 µF
Q1
CREG=1 µF
1.5
Quiescent Current 1 I
Quiescent Current 1 I Q1 (mA)
Quiescent Current 1 vs. Operating Voltage
1
0.5
0
0
5
10
15
20
25
30
35
+
1.5
1
0.5
15
10
5
0
(mA)
20
Q2
CREG=1µF
0
5
10 15 20 25 30
+
Operating Voltage V (V)
35
(µA)
QOFF
CBS=0.47µF
CREG=1µF
8
6
4
2
0
0
5
10
15 20 25 30
+
Operating Voltage V (V)
35
PWM
=0V to 3V, f
PWM
=1.2MHz)
15
CREG=1µF
10
5
0
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
Quiescent Current 3 vs. Temperature
Quiescent Current 3 I
Quiescent Current 3 I QOFF (µA)
- 10 -
10
(V+=12V, V
CBS=0.47µF
Quiescent Current 3 vs. Operating Voltage
(VSTBY=2V, fPWM=0V, Ta=25oC)
CREG=1µF
Quiescent Current 2 vs. Temperature
Quiescent Current 2 I
Quiescent Current 2 IQ2 (mA)
CBS=0.47µF
=0V)
CBS=0.47µF
Quiescent Current 2 vs. Operating Voltage
20
PWM
0
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
Operating Voltage V (V)
(VPWM=0V to 3V, f PWM=1.2MHz, Ta=25oC)
(V+=12V, V
2
10
(V+=12V, V
STBY
=2V, V
PWM
=0V)
CBS=0.47µF
8
CREG=1µF
6
4
2
0
-50 -25 0 25 50 75 100 125 150
o
Ambient Temperature Ta ( C)
Ver.2010-09-29
NJW4800
PIN DESCRIPTION
PIN
PIN NAME
NUMBER
1
PWM
2
VDD
3
OUT
4
GND
5
BS
6
STBY
7
REG
8
FLT
–
Exposed
PAD
Ver.2010-09-29
FUNCTION
PWM Signal Input Terminal
As for Control Logic, Refer to PIN OPERATION TABLE (page.5)
Power Supply Terminal
You should connect capacitor (AL and MLCC) for reducing Input Impedance.
Output Terminal
The High-side/Low-side Switch are Limited to 5.5A(typ.) by Over Current
Protection Circuit.
Ground Terminal
Boot Strap Output Terminal
Boot Strap Output drives the High-side Switch. You should connect capacitor
larger than 0.1µF between BS Terminal (5-pin) and Out Terminal (3-pin).
Standby Terminal
NJW4800 becomes standby status by High Level
NJW4800 operates by Low Level
Built-in Regulator (5V) Output Terminal
You should connect capacitor larger than 1µF for stable output.
Fault Signal Output Terminal
It is Open Drain Output Type. You should connect through Pull-up Resister to
REG Terminal (7-pin) or External Power Supply.
It outputs Low Level under normal operating condition and outputs High Level
under Abnormal Conditions.
Connected to 4pin (Ground Terminal)
- 11 -
NJW4800
FUNCTIONAL EXPLANATION
High-side, Low-side Switch
The SW output drives the load. It is controlled by the logic input signal from PWM terminal at PWM. When the signal at
PWM is high (above 2.2V), the high-side switch is turned on. When the signal at PWM is low (less than 0.9V), the
low-side switch is turned on.
The NJW4800 uses built-in Nch MOSFETs (RON=0.25Ω typ.) for both the high-side and low-side switches. The
high-side SW gate is driven with V++5V that generated by bootstrap. The high-side SW turn on time is limited to
300µsec(typ.). (ex. Fig2)
ON
There is a dead time region (20nsec (typ.): design value) to
High Side
prevent short circuit (high-side and low-side) where both the
SW
high-side and low-side switches are off. (ex. Fig3)
OFF
The NJW4800 is suitable for high-frequency switching
ON
regulator. The NJW4800 operates at frequencies up to
Low Side
1.2MHz.
SW
OFF
The OUT terminal is pulled down inside with 100kΩ,
compensates the leak current of the High-side SW.
Dead Time 20ns typ.
Fig3. SW Function and Dead Time Relation
Over Current Protection Function
The internal over-current protection circuit monitors the flow currents of both the high-side and low-side switches. The
over-current protection circuit operates at 5.5A (typ.) and stops the SW operation. The FLT signal is output from FLT
terminal at the same time. The over-current protection operation is released at the PWM input signal falling edge. (ex.
Fig4)
If OUT terminal is shorted directly to GND, a large surge current is flowing for fast current change and may exceed
current limit. Because that time big electric power consumption occurs instantaneously in NJW4800, you should design
sufficient heat dissipation.
When a load condition is inductive property, a reverse direction current flows to the high-side and low-side SW body
diode by inductive kickback.
The built-in over-current protection circuit has not aimed at protection against the inductive kickback.
Therefore, an external diode should be considered usage against reverse-current regeneration according to the kind of
the application.
The Overcurrent Protection is
released with the falling edge
PWM Input
High
Low
ON
High Side SW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OFF
ON
Low Side SW
OFF
ON
Current Limit
OFF
Fault Output
(FLT pin Pull-Up)
High
Low
Fig4. Timing Chart of High-side/Low-side Switch at Over Current Protection Operating
- 12 -
Ver.2010-09-29
NJW4800
Boot Strap
In order to drive the gate of the high side SW, the voltage that is higher than power supply voltage is necessary.
The bootstrap condenser generates the power supply voltage of V++5V to BS terminal and it supplies the power to the
gate of the high side SW. As Shown as Fig5 in detail.
V
Power Line
+
V
Regulator Voltage
VDD
Power Line
+
Regulator Voltage
VDD
V+=5V is generated to
the BS terminal.
BS
Regulator
5V
Regulator
5V
OFF
CBS
High Side
Gate Driver
CBS is
charged to 5V
ON
OUT becomes V+
voltage
OUT
OUT
ON
Low Side
Gate Driver
High-side SW: OFF
Low-side SW: ON
CBS
High Side
Gate Driver
OFF
Low Side
Gate Driver
High-side SW: ON
Low-side SW: OFF
Fig5. High-side SW driven by Boot Strap
You should connect bootstrap condenser larger than CBS=0.1µF between BS Terminal and OUT Terminal.
The internal counter decides the bootstrap condenser Charge and Discharge time.
A capacitor discharge time (tHPWM) for High-side SW Maximum ON Time is 300ms (typ).
A capacitor charge time (tHPWM / 128) for Low-side SW Minimum ON Time is 2.34µs (typ).
Built-in Regulator
The REG Terminal outputs Reference Voltage (5V).
It can be used as generating of the voltage for the bootstrap or a power supply voltage for other device(s). You should
connect capacitor (CREG) larger than 1µF for stable regulator output.
This regulator current capability (IOREG) is 30mA (min) at (VREG1×0.95). This regulator over current protection is a
drooping characteristic type. It has drooping characteristic at over current protection function.
Thermal Shut Down Function
When NJW4800 chip temperature exceeds the 170°C, internal thermal shutdown circuit operates and SW function is
stopped. The Fault signal is output simultaneously from the FLT terminal. In order to return SW operation, you should
make chip surface temperature (Junction Temperature: Tj) below the 150°C*.
This function is a circuit to prevent IC at the high temperature from malfunctioning and is not something that urges
positive use. You should make sure to operate inside the junction temperature range rated. (* Design value)
Ver.2010-09-29
- 13 -
NJW4800
Under Voltage Lockout(UVLO)
The UVLO circuit operating is released above V+=6.6V(typ.) and IC operation starts. When power supply voltage is low,
because the UVLO circuit operates, IC does not operate. There is 0.25V width hysteresis voltage at rise and decay of
power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.
FAULT Signal Output
This Terminal is Open Drain Output Type. You should connect through Pull-up Resister to REG Terminal (7-pin) or
External Power Supply. It outputs Low Level under normal operating condition and outputs High Level under Abnormal
Conditions.
The following information is output as FAULT signal.
・Stop Operation at Under Voltage Lockout (UVLO)
・Over Current Protection Function
・Thermal Shut Down
At the time of standby state, it outputs High Level.
When outputting the FAULT signal, it has stopped SW operation, but the internal regulator continues operation.
Because of this 30mA it is flowing via the OUT terminal from the regulator circuit.
Standby Function
NJW4800 stops the operating and becomes standby status when 2.4V or more is supplied to STBY terminal.
You should connect the terminal with GND level to prevent the malfunction by a noise when you do not use this function.
- 14 -
Ver.2010-09-29
NJW4800
APPLICATION TIPS
In the application that does a high-speed switching of NJW4800, because the current flow corresponds to the input
frequency, the substrate (PCB) layout becomes an important.
NJW4800 is driving the High-side/Low-side SW gate with high speed to reduce switching losses. The transient voltage
is generated by parasitic inductance and a high-speed current change of high side and low side SW.
You should attempt the transition voltage decrease by making a current loop area minimize as much as possible.
Therefore, you should make a current flowing line thick and short as much as possible.
You should insert a bypass capacitor between VDD terminal and GND terminal to prevent malfunction by generating
over voltage and/or exceed maximum input voltage rating. The recommended bypass capacitor is 1µF or more high
frequency capacitor.
A 100µF aluminum electrolysis capacitor is recommended for smoothing condenser. However, you should use larger
capacitor by sufficient evaluation (assessment) due to load condition and/or application use environment. (There is a
possibility that the supply voltage rises by inductive kickback when the supply current of the inductive load is large.)
The bypass capacitors should be connected as much as possible near VDD terminal.
Ex. Bill of Materials
Components
Parts Name
CIN
−
CP
GRM21BB11H104KA01B
CREG
GRM31MB31H105KA87B
CBS
GRM21BR71H474KA88B
RFLT
RK73B1JT473
Ver.2010-09-29
Functions
Aluminum-Cap.
Ceramic-Cap. 0.1µF, 50V (B-val)
Ceramic-Cap. 1µF, 50V (B-val)
Ceramic-Cap. 0.1µF, 50V (X7R-val)
47kΩ
Manufacturers
Nippon Chemi-con
Murata
Murata
Murata
KOA
- 15 -
NJW4800
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 16 -
Ver.2010-09-29