TI TPS65921B1ZQZ

TPS65921
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
Power Management and USB Single Chip
Check for Samples: TPS65921
FEATURES
1
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3 Step-Down Converters:
– Up to 1.2 A of output current for VDD1
– TPS65921B supports VDD1 up to 1.2 A
– TPS65921B1 supports VDD1 up to 1.4 A
(necessary for 1-GHz operation)
– SmartReflex™ dynamic voltage
management
– 3.2 MHz fixed frequency operation
– VIN range from 2.7 to 4.5 V
– Typical 30 µA quiescent per converter
4 general-purpose configurable LDOs:
– Dynamic voltage scaling
– 220 mA maximum current for one LDO
– VIN range from 2.7 to 4.5 V
– 2 LDOs with low noise and high PSRR
RTC with alarm wake up mechanism
Clock management
– 32-kHz crystal oscillator
– Clock slicer for 26, 19.2, and 38.4 MHz
– HF clock output buffer
USB:
– USB HS 2.0 transceiver
– USB 1.3 OTG-compliant
– 12-bit ULPI 1.1 interface
– USB power supply (5-V CP for VBUS)
Control
– High-speed I2C™ interface
– All resource configurable by I2C
Keypad interface up to 8 × 8
10-bit A/D converter
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Hot-die, thermal shutdown protection
µ*BGA 120 balls ZQZ
APPLICATIONS
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Mobile phones and smart phones
MP3 players
Handheld devices
E-Books
OMAP™ and low power DSP supply
DESCRIPTION
The TPS65921 device is a highly integrated powermanagement circuit (IC) that supports the power and
peripheral requirements of the OMAP application
processors. The device contains power management,
a universal serial bus (USB) high-speed (HS)
transceiver, an analog-to-digital converter (ADC), a
real-time clock (RTC), a keypad interface, and an
embedded power control (EPC). The power portion of
the device contains three buck converters, two
controllable by a dedicated SmartReflex™ class-3
interface, multiple low-dropout (LDO) regulators, an
EPC to manage the power-sequencing requirements
of OMAP, and an RTC module. The USB module
provides a HS 2.0 transceiver suitable for direct
connection to the OMAP universal transceiver
macrocell interface (UTMI) + low pin interface (ULPI)
with an integrated charge pump (CP).
The device also provides auxiliary modules: ADC,
keypad interface, and general-purpose inputs/outputs
(GPIOs) muxed with the JTAG functions. The keypad
interface implements a built-in scanning algorithm to
decode hardware-based key presses and to reduce
software use, with multiple additional GPIOs that can
be used as interrupts when they are configured as
inputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS65921
SWCS048F – MARCH 2010 – REVISED MARCH 2012
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
0.0
5.0
V
–0.3
1.0 × Supply + 0.3
V
Main battery supply
voltage (2)
Where supply represents the voltage
applied to the power supply pin
associated with the input (4)
Voltage on any input (3)
NOM
VBUS input
–0.3
7
V
Storage temperature range
–55
125
°C
Operating ambient
temperature (TA)
–40
85
°C
–40
125
°C
–40
150
°C
–40
85
°C
Operating junction
temperature (TJ)
Absolute maximum rating
Operating junction
temperature (TJ)
For parametric compliance
Ambient temperature for
parametric compliance
With maximum 125°C as junction
temperature (TJ)
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
The product will have negligible reliability impact if voltage spikes of 5.2 V occur for a total (cumulative over lifetime) duration of 10
milliseconds.
Excepts VBAT input pads and VBUS pad.
Supply equals the reference level of each pin.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
7
V
Power and USB Path
VBAT/VBAT.USB main battery supply voltage and
VBUS
0
HFCLKIN Input Clock
Frequency 1/tC(HFCLKIN)
19.2, 26 or 38.4
Pulse duration, HFCLKIN low or high (BP)
MHz
0.55 ×
0.45 × tC(HFCLKIN)
HFCLKIN stability
ns
tC(HFCLKIN)
–150
150
ppm
Rise time of HFCLKIN (BP)
0
5
ns
Fall time of HFCLKIN (BP)
0
5
ns
1.45
Vpp
1.85 (1)
Vpp
–25
dBc
LP/HP (sine wave)
Input dynamic range
0.3
BP/PD (square wave)
0.7
0
Harmonic content of input signal (with 0.7-VPP amplitude): Second
component - LP/HP (sine wave)
VIH voltage input
high (1)
VIL voltage input low
BP (square mode)
(1)
0.65 × IO.1P8
V
BP (square mode)
0.35 × IO.1P8
V
Crystal Oscillator
Parallel resonance crystal frequency 1/tC(32KHZ)
32.768
Input voltage, Vin (normal mode)
1.0
Crystal tolerance at room temperature, 25°C
Crystal tolerance versus temperature range (–40°C to 85°C)
Crystal quality factor
1.3
V
–30
30
ppm
–200
200
ppm
13k
54k
Maximum drive power
Operating drive level
(1)
2
kHz
1.55
1
µW
0.5
µW
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
32KXIN 32KXOUT
duty cycle
Crystal
40%
60%
Square wave
45%
55%
32-kHz clock rise/fall
time
Square wave with capacitive load equivalent to
30 pF
VIH voltage input high
Square wave in bypass mode (1)
VIL voltage input low
Square wave in bypass mode
0.1 × tC(32KHZ)
0.65 × VBRTC
µs
V
(1)
0.35 × VBRTC
V
DCDC Converters and LDOs
VDD1.IN, VDD2.IN, VDD3.IN input voltage range for step-down converter
VDD1, VDD2, VIO
VMMC1.IN input voltage range for LDO VMMC1
2.7
3.6
4.5
V
Maximum (2.7,
output voltage
selected + 250 mV)
3.6
4.5
V
VDAC.IN input voltage range for LDO VDAC
2.7
3.6
4.5
V
VAUX12S.IN input voltage range for LDO VAUX2
Maximum (2.7,
output voltage
selected + 250 mV)
3.6
4.5
V
VINT.IN input voltage range for LDO VINTANA1, VINTANA2, VINTDIG
and VRTC
Maximum (2.7,
output voltage
selected + 200 mV)
3.6
4.5
V
VPLLA3R.IN input voltage range for LDO VPLL1
2.7
3.6
4.5
V
VDD1.OUT ouput voltage range for VDD1 step-down converter
0.6
1.45
V
VDD2.OUT ouput voltage range for VDD2 step-down converter
0.6
1.5
V
VIO.OUT ouput voltage range for VIO step-down converter
1.8/1.85
V
VMMC1.OUT output voltage range for LDO VMMC1
1.85
3.15
V
VDAC.OUT output voltage range for LDO VDAC
1.2
1.8
V
VAUX2.OUT output voltage range for LDO VAUX2
1.3
2.8
V
VPLL1.OUT output voltage range for LDO VPLL1
1.0
1.8
V
VINTANA1.OUT output voltage for LDO VINTANA1
1.5
V
VINTANA2.OUT output voltage for LDO VINTANA2
2.5/2.75
V
VINTUSB1P5V.OUT output voltage for LDO VINTUSB1P5
1.35
1.5
1.65
V
VINTUSB1P8V.OUT output voltage for LDO VINTUSB1P8
1.62
1.8
1.98
V
VUSB3P1V.OUT output voltage for LDO VUSB3P1
3.1
VINTDIG.OUT output voltage range for LDO VINTDIG
VRTC.OUT output
voltage range
V
1.35
1.5
1.65
V
Normal mode
1.45
1.5
1.55
V
Backup mode
1.0
1.3
1.55
V
9
10
External Components
Crystal: Nominal load cap on each oscillator input CXIN and CXOUT (2)
12.5
pF
Crystal ESR (3)
90
kΩ
Crystal shunt capacitance, CO
1
pF
1.3
µH
0.1
Ω
Value
External coil for VDD1
(2)
(3)
0.7
DCR
1
Saturation current for TPS65921B
1.8
A
Saturation current for TPS65921B1
2.1
A
Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc × 2 – (Cint + Cpin). Cosc is the load capacitor
defined in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor.
The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula:
æ
C ö
ESR = Rm ç 1 + 0 ÷
è CL ø
2
Measured with the load capacitance specified by the crystal manufacturer. In fact, if CXIN = CXOUT = 10 pF, then CL = 5 pF. Parasitic
capacitance from the package and board must also be considered.
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
Value
External coil for VDD2
and VIO
0.7
1
DCR
1.3
0.1
Saturation current
900
External capacitor for
Value (4)
VDD1, VDD2, VIO
connected to VDD1.IN,
VDD2.IN, VDD3.IN,
ESR at switching frequency
and VDD1.OUT,
VDD2.OUT, VIO.OUT
µH
Ω
mA
5
10
1
μF
20
mΩ
2.7
µF
600
mΩ
6.5
µF
600
mΩ
Filtering capacitor for
VMCC1.IN, VDAC.IN,
VAUX12S.IN,
VPPLA3R.IN, VINT.IN,
VBAT.USB,
VMMC1.OUT,
VDAC.OUT,
VAUX2.OUT, VPPL1,
VINTDIG, VINTANA1,
VINTANA2, VRRTC
Value
0.3
ESR
20
Filtering capacitor for
VUSB3V1, VUSB1V8,
VUSB1V5
Value
0.5
ESR
20
Connected from VREF to REFGND
0.3
1
2.7
µF
Filtering capacitor (Connected between
VBUS.CPOUT and GND) and called CVBUS
1.41 (The minimum
can be reduced to
1.2 µF, provided the
charge-pump is only
used to supply
VUSB3V1 LDO)
4.7
6.5
µF
Flying capacitor (Connected between CP.CAPP
and CP.CAPM) called CVBUS.FC
1.32 (The minimum
can be reduced to
1.2 µF, provided the
charge-pump is only
used to supply
VUSB3V1 LDO)
2.2
3.08
µF
20
mΩ
Filtering capacitor for
voltage reference
External capacitor for
charge pump and
VBUS
1
15
2.2
Filtering capacitor ESR for CVUSB.IN and
CVBUS.FC
Filtering capacitor CVBUS.IN
External capacitor for
power reference filter
(4)
Filtering capacitor
5
10
15
µF
0.3
1
2.7
µF
For TPS65921B1, in case of OMAP frequency ≥ 1 GHz, replace 10-µF capacitor on VDD1.OUT by two 22-µF capacitors. One capacitor
must be placed near the PMIC and one near the OMAP device.
ELECTRICAL CHARACTERISTICS
CRYSTAL OSCILLATOR
When selecting a crystal, the system designer must consider the temperature and aging characteristics of a
crystal versus the user environment and expected lifetime of the system. The following table lists the switching
characteristics of the oscillator.
Table 1. Base Oscillator Switching Characteristics
PARAMETER
Crystal: Internal capacitor on each input (Cint)
MIN
TYP
MAX
UNIT
8
10
12
pF
Crystal: Parallel input capacitance (Cpin)
1.0
Parallel resonance crystal frequency
32.768
Pin-to-pin capacitance
4
1.6
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pF
kHz
1.8
pF
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
Table 1. Base Oscillator Switching Characteristics (continued)
PARAMETER
MIN
TYP
Maximum drive power
Operating drive level
Crystal quality factor
13k
tSX
MAX
UNIT
1.0
µW
0.5
µW
54k
Start-up time, all conditions
500
Start-up time, 25°C
360
IDDA
Active current
consumption (configured
through the LOJIT bit)
IDDQ
Current consumption
High jitter mode
1.8
Low jitter mode
0.8
Low battery mode (1.2 V)
1
Startup
8
ms
µA
µA
CLOCK SLICER
MODE (1)
PARAMETER
Internal coupling capacitor
Parallel input resistance over 10 to 40 MHz range
Parallel input capacitance over 10 to 40 MHz range
Output duty cycle with VIN = 0.2 VPP
Propagation delay
Power supply rejection ratio sideband (1% RMS of supply voltage added
sine 5 MHz)
MIN
TYP
MAX
UNIT
4.2
5
5.7
pF
kΩ
LP
15
60
HP
30
75
kΩ
BP/PD
1
100
MΩ
LP
0.3
0.8
HP
0.3
0.7
BP/PD
0.08
1
BP/PD
40
LP/HP
40%
pF
230
50%
60%
LP
4
18
HP
3
15
BP/PD
0.2
3
LP/HP
26
ns
dBc
LP
175
µA
HP
235
µA
BP/PD
39
nA
Power-up time
LP/HP
1
ms
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency below 300 kHz
LP/HP
0.2%
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency above 300 kHz
LP/HP
1.0%
Current consumption at maximum input of 40 MHz
(1)
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface.
32KCLKOUT OUTPUT CLOCK
NAME
PARAMETER DESCRIPTION
f
Frequency
CL
Load capacitance
MIN
TYP
MAX
32.768
kHz
40
(1)
pF
VOUT
Output clock voltage, depending on output
reference level IO.1P8
VOH
Voltage output high
VOUT – 0.45
VOUT
V
VOL
Voltage output low
0
0.45
V
(1)
1.8
UNIT
V
The output voltage depends on output reference level which is IO.1P8.
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The following table details the output clock timing characteristics. The following figure shows the 32KCLKOUT
output clock waveform.
NAME
CK0
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
1/tC(32KCLKOUT)
Frequency
tW(32KCLKOUT)
Pulse duration,
32KCLKOUT low or high
CK2
tR(32KCLKOUT)
Rise time, 32KCLKOUT (1)
16
ns
CK3
tF(32KCLKOUT)
Fall time, 32KCLKOUT (1)
16
ns
SSB Phase Noise
At 1-kHz offset from the
carrier
–110
dBc/Hz
CK1
(1)
32.768
kHz
0.40 ×
0.60 ×
tC(32KCLKOUT)
tC(32KCLKOUT)
ns
The output capacitive load is equivalent to 30 pF.
CK0
CK1
CK1
32KCLKOUT
SWCS048-001
Figure 1. 32KCLKOUT Output Clock
HFCLKOUT OUTPUT CLOCK
The following table summarizes the HFCLKOUT output clock electrical characteristics.
Table 2. HFCLKOUT Output Clock Electrical Characteristics
NAME
PARAMETER DESCRIPTION
MIN
TYP
MAX
Frequency
CL
Load capacitance
VOUT
Output clock voltage, depending on
output reference level IO.1P8
VOH
Voltage output high
VOUT – 0.45
VOUT
V
VOL
Voltage output low
0
0.45
V
(1)
19.2, 26, or 38.4
UNIT
f
MHz
30
pF
1.8 (1)
V
The output voltage depends on output reference level which is IO.1P8.
The following table details the HFCLKOUT output clock timing characteristics.
Table 3. HFCLKOUT Output Clock Switching Characteristics
NAME
PARAMETER
DESCRIPTION
CHO1
1/tC(HFCLKOUT)
Frequency
CHO2
tW(HFCLKOUT)
Pulse duration, HFCLKOUT low
or high
MIN
TYP
MAX
19.2, 26, or 38.4
0.4 ×
tC(HFCLKOUT)
UNIT
MHz
0.6 ×
tC(HFCLKOUT)
ns
Rise time, HFCLKOUT, low
drive (1)
CHO3
(1)
6
tR(HFCLKOUT)
- Load: 5 pF
3.8
- Load: 10 pF
5.5
Rise time, HFCLKOUT, high
drive (1)
- Load: 10 pF
2.9
- Load: 20 pF
5.0
ns
Low drive: MISC_CFG[CLK_HF_DRV] = 0 (default)
High drive: MISC_CFG[CLK_HF_DRV] = 1
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Table 3. HFCLKOUT Output Clock Switching Characteristics (continued)
NAME
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Fall time, HFCLKOUT, low
drive (1)
CHO4
tF(HFCLKOUT)
- Load: 5 pF
3.5
- Load: 10 pF
5.1
ns
Fall time, HFCLKOUT, high
drive (1)
- Load: 10 pF
2.7
- Load: 20 pF
4.7
Figure 2 shows the HFCLKOUT output clock waveform.
CHO1
CHO1
CHO2
HFCLKOUT
SWCS048-002
Figure 2. HFCLKOUT Output Clock
Figure 3 shows the 32KCLKOUT and HFCLKOUT clock stabilization time.
XIN
Starting_Event
Tstartup
CLK32KOUTEN
CLK32KOUT
CLKEN
Delay1
HFCLKOUTEN
HFCLKOUT
Delay2
NRESPWRON
SWCS048-003
A.
Tstartup, Delay1, Delay2, and Delay3 depend on the boot mode (See Power timing chapter).
Figure 3. 32KCLKOUT and HFCLKOUT Clock Stabilization Time
HFCLKIN
HFCLKOUT
SWCS048-004
Figure 4. HFCLKOUT Behavior
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VDD1 DCDC CONVERTER
MIN
TYP
MAX
UNIT
Input voltage range
PARAMETER
COMMENTS
2.7
3.6
4.5
V
Output voltage
0.6
1.45
V
Output voltage step
0.6 to 1.45 V
Output accuracy (1)
0.6 to < 0.8 V
–6%
12.5
0.8 to 1.45 V
–5%
Switching frequency
Conversion efficiency (2)
Output current
Ground current (IQ)
5%
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
600 mA < IO < 800 mA
75%
1.2
A
Active mode
Output Voltage 1.2 V to 1.45 V
for TPS65921B1
1.4
A
Sleep mode
10
mA
Off at 30°C
3
Sleep, unloaded
Short-circuit current
VIN = VMAX
Load regulation
0 < IO < IMAX
Transient load regulation at 1.2 A (3)
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
30
50
2.2
–65
300 mVPP ac input, 10-μs rise and fall
time
Start-up time
From sleep to on with constant load
Slew rate (rising or falling) (4)
4
A
20
mV
50
mV
10
mV
10
mV
ms
0.25
1
< 10
100
µs
8
16
mV/µs
mV
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
Output pulldown resistance
In Off mode
Output ripple
(1)
(2)
(3)
(4)
8
µA
300
Line regulation
Recovery time
MHz
Active mode
Output voltage 0.6 V to 1.45 V
for TPS65921B/TPS65921B1
Active, unloaded, not switching
Transient line regulation
mV
6%
mA
5%
500
700
Ω
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
VBAT = 3.6 V, VDD1 = 1.2 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
For negative transient load, the output voltage must discharge completely and settle to its final value within 100 ms. Transient load is
specified at Vout max with a ±50% external capacitor accuracy and includes temperature and procress variation.
Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
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VDD2 DCDC CONVERTER
MIN
TYP
MAX
UNIT
Input voltage range
PARAMETER
COMMENTS
2.7
3.6
4.5
V
Output voltage
0.6
1.0
1.5
V
Output voltage step
0.6 to 1.45 V
Output accuracy (1)
0.6 to < 0.8 V
–6%
12.5
0.8 to 1.45 V
–5%
Switching frequency
Conversion efficiency (2)
Output current
Ground current (IQ)
5%
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 300 mA
85%
300 mA < IO < 500 mA
80%
600
mA
Sleep mode
10
mA
Off at 30°C
1
Sleep, unloaded
Short-circuit current
VIN = VMAX
Load regulation
0 < IO < IMAX
Transient load regulation (3)
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
30
50
1.2
Transient line regulation
300 mVPP ac input, 10-μs rise and fall
time
Output pulldown resistance
In OFF mode
–65
Start-up time
From sleep to on with constant load
Slew rate (rising or falling) (4)
4
A
20
mV
50
mV
10
mV
10
mV
500
700
Ω
0.25
1
ms
25
100
µs
8
16
mV/µs
mV
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
(1)
(2)
(3)
(4)
µA
300
Line regulation
Output ripple
MHz
Active mode
Active, unloaded, not switching
Recovery time
mV
6%
mA
5%
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Output voltage must be able to discharge the load current completely and settle to its final value within 100 μs.
Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
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VIO DCDC CONVERTER
PARAMETER
COMMENTS
Input voltage range
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
1.8
1.85
Output voltage (1)
Output accuracy
DC accuracy only
–3%
3%
Including all variations (line and load
regulations, line and load transients,
temperature, and process)
–4%
4%
Switching frequency
Conversion efficiency (2)
Output current
3.2
IO = 10 mA, sleep
85%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
Load regulation
700
mA
Sleep mode
10
mA
1
Sleep, unloaded
30
0 < IO < IMAX
20
mV
10
mV
50
mV
10
mV
0.25
1
ms
< 10
100
µs
8
16
mV/µs
mV
Transient load regulation
Transient line regulation
300 mVPP ac input, 10-μs rise and fall
time
–65
Start-up time
From sleep to on with constant load
Slew rate (rising or falling)
4
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
Output pulldown resistance
In Off mode
(1)
(2)
10
µA
300
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
Output ripple
50
Active, unloaded, not switching
Line regulation
Recovery time
MHz
On mode
Off at 30°C
Ground current (IQ)
V
mA
5%
500
700
Ω
This voltage is tuned according to the platform and transient requirements.
VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
VMMC1 LOW DROPOUT REGULATOR
PARAMETER
VIN
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
3.6
5.5
V
1.7945
2.7645
2.91
3.0555
1.85
2.85
3.0
3.15
1.9055
2.9355
3.09
3.2445
V
On mode
220
mA
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10%
of VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
25
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
VDO
Dropout voltage
(1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
290
Low-power mode, IOUT = 0
17
Low-power mode, IOUT = 5 mA
20
Off mode at 55°C
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 40 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pulldownresistance
Default in off mode
µA
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
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VDAC LOW DROPOUT REGULATOR
PARAMETER
VIN
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
1.164
1.261
1.746
12
1.3
1.8
1.236
1.339
1.854
V
On mode
70
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 20 kHz
65
20 kHz < f < 100 kHz
45
f = 1 MHz
40
mA
dB
VIN = VOUT + 1 V, IO = IMAX
Output noise
Ground current
200 Hz < f < 5 kHz
400
5 kHz < f < 400 kHz
125
400 kHz < f < 10 MHz
50
On mode, IOUT = 0
150
On mode, IOUT = IOUTmax
350
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
25
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
12
Slew: 60 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pull down resistance
Default in off mode
µA
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
nV/√Hz
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
VAUX2 LOW DROPOUT REGULATOR
PARAMETER
VIN
TEST CONDITIONS
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
–3%
1.3
1.5
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.8
+3%
V
On mode
100
mA
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
170
Low-power mode, IOUT = 0
17
Low-power mode, IOUT = 5 mA
20
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
Overshoot
Pulldown resistance
(1)
(2)
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 40 mA/μs
µA
–40
VIN drops 500 mV
Slew: 40 mV/μs
Softstart
250
mV
40
mV
10
mV
3%
Default in off mode
250
Configurable as HighZ in off mode
100
320
450
Ω
MΩ
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
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VPLL1 LOW DROPOUT REGULATOR
PARAMETER
VIN
VOUT
IOUT
MIN
TYP
MAX
UNIT
Input voltage
TEST CONDITIONS
2.7
3.6
4.5
V
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
0.97
1.0
1.03
1.164
1.2
1.236
1.261
1.3
1.339
1.746
1.8
1.854
V
On mode
40
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Rated output current
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
mA
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
110
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
16
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
14
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 60 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pulldown resistance
Default in off mode
µA
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
INTERNAL LDOS
Internal LDOs (except USBCP, which is a boost) are described in following table.
NAME
USAGE
TYPE
VOLTAGE RANGE
(V)
DEFAULT
VOLTAGE (V)
MAXIMUM
CURRENT
VINTANA1
Internal
LDO
1.5
1.5
50 mA
VINTANA2
Internal
LDO
2.5, 2.75
2.75
250 mA
VINTDIG
Internal
LDO
1.5
1.5
100 mA
USBCP
Internal
Charge pump
5
5
100 mA
VUSB1V5
Internal
LDO
1.5
1.5
30 mA
VUSB1V8
Internal
LDO
1.8
1.8
30 mA
VUSB3V1
Internal
LDO
3.1
3.1
14 mA
VRRTC
Internal
LDO
1.5
1.5
30 mA
VBRTC
Internal
LDO
1.3
1.3
100 μA
VOLTAGE REFERENCES
TEST CONDITONS
MIN
TYP
MAX
UNIT
Internal bandgap reference
voltage
PARAMETER
On mode, measured through
TESTV terminal
1.272
1.285
1.298
V
Reference voltage (VREF
terminal)
On mode
0.7425
0.75
0.7575
V
Retention mode reference
On mode
0.492
0.5
0.508
V
0.9
1.0
1.1
µA
IREF NMOS sink
Ground current
Output spot noise
Bandgap
25
IREF block
20
Preregulator
15
VREF buffer
10
Retention reference buffer
10
100 Hz
1
µA
μV/√Hz
A-weighted noise (rms)
200
nV (rms)
P-weighted noise (rms)
150
nV (rms)
2.2
µV
Integrated noise
20 Hz to 100 kHz
IBIAS trim bit LSB
Ripple rejection
< 1 MHz from VBAT
0.1
µA
1
ms
60
dB
Start-up time
BATTERY THRESHOLD LEVELS (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Main battery charged
threshold VMBCH
Measured on VBAT terminal
3.14
3.2
3.3
V
Main battery low threshold
VMBLO
Measured on VBAT terminal (monitored
on terminal ONNOFF)
2.55
2.7
2.8
V
Main battery high threshold
VMBHI
Measured on terminal VBAT
2.5
2.65
3.0
V
Measured on terminal VBAT
1.6
1.8
2.6
V
Measured on terminal VBAT in slave
mode
1.95
2.1
2.6
V
Batteries not present
threshold VBNPR
(1)
Backup ball must always be tied to ground.
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POWER CONSUMPTION
The typical power consumption is obtained in the nominal operating conditions and with the TPS65921
standalone.
MODE
TYPICAL
CONSUMPTION
DESCRIPTION
C021 boot mode
WAIT-ON
ACTIVE No Load
HFCLK = 26 MHz
ACTIVE No Load
HFCLK = 38.4 MHz
SLEEP No Load
The phone is apparently off for the user, a
main battery is present and well-charged.
The RTC registers, registers in backup
domain are maintained. The wak-eup
capabilities (like the PWRON button) are
available.
VBAT = 3.8 V and
Quartz present
Subsystem is powered by the main battery.
All supplies are enabled with no external
load, internal reset is released, and the
associated processor is running. USB
intertupt handler consumes 433 µA (typ).
VBAT = 3.8 V
The main battery powers subsystem.
Selected supplies are enabled but in lowconsumption mode and associated
processor is in low-power mode.
VBAT = 3.8 V
64 µA × 3.8 V =
243.2 μW
(2995 + 433) µA ×
3.8 V = 13026 µW
(3879 + 433) µA ×
3.8 V = 16386 µW
492 µA × 3.8 V =
1870 µW
USB CHARGE PUMP
PARAMETER
VIN
Input voltage
VO
Output voltage
Iload
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
On mode: VIN = VBAT
2.7
3.6
4.5
V
4.625
5.0
5.25
V
VBAT > 3 V at VBUS
0
100
2.7 V < VBAT < 3 V, at VBUS
0
50
Efficiency
ILOAD = 100 mA, VBAT = 3.6 V
55%
Setting time
ILOADmax/2 to ILOADmax in 5 μs
100
400
µs
3
ms
350
450
mA
250
500
mV
250
350
mV
300
350
Start-up time
Short-circuit limitation current
DC load regulation
DC line regulation
250
ILOADmin to ILOADmax
3.0 V to VBATmax
ILOAD = 100 mA
IVBUS_5Vmax/2 – IVBUS_5Vmax
Transient load regulation
50 μs, C = 2 × 4.7 μF
mV
0 – IVBUS_5Vmax/2, 50 μs, C = 2
× 4.7 μF
Transient line regulation
16
VBATmin to VBATmax in 50 μs,
C = 2 × 4.7 μF
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mA
350
300
350
mV
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
HOT-DIE DETECTION AND THERMAL SHUTDOWN
PARAMETER
THRESHOLD (NOMINAL) (1)
Thermal hot-die selection THERM_HDSEL[1:0]
Threshold (nominal) (1)
Rising temp: 120°C
00 (1st hot-die threshold)
Falling temp: 111°C
Rising temp: 130°C
01 (2nd hot-die threshold)
Falling temp: 121°C
Rising temp: 140°C
10 (3rd hot-die threshold)
Falling temp: 131°C
11 (4th hot-die threshold)
Not used
Threshold (nominal) (1) - Rising temp: 150°C
Thermal shutdown enable
(1)
Threshold (nominal) (1) - Falling temp: 140°C
The minimum/maximum range is ±5%
USB
LS/FS SINGLE-ENDED RECEIVERS
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
0
2
ns
USB Single-Ended Receivers
Skew
between VP
and VM
SKWVP_VM
Driver outputs unloaded
Single-ended
hysteresis
VSE_HYS
50
mV
High (driven)
VIH
2
V
Low
VIL
Switching
threshold
VTH
–2
0.8
0.8
V
2
V
MAX
UNIT
LS/FS DIFFERENTIAL RECEIVER
PARAMETER
COMMENTS
MIN
Differential input sensitivity
VDI
Ref. USB2.0
200
Differential common mode
range
VCM
Ref. USB2.0
0.8
Low
VOL
Ref. USB2.0
0
High (driven)
VOH
Ref. USB2.0
Output signal crossover
voltage
VCRS
Ref. USB2.0, covered by eye
diagram
Rise time
TFR
Fall time
TFF
Differential rise and fall time
matching
TFRFM
Low-speed data rate
TFDRATE
TYP
mV
2.5
V
MAX
UNIT
300
mV
2.8
3.6
V
1.3
2.0
V
75
300
ns
75
300
ns
80%
125%
1.4775
1.5225
LS/FS TRANSMITTER
PARAMETER
COMMENTS
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
MIN
TYP
Mbps
Source jitter total (including
frequency tolerance):
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SWCS048F – MARCH 2010 – REVISED MARCH 2012
PARAMETER
- To next transition
TDJ1
- For paired transitions
TDJ2
Source SE0 interval of EOP
TFEOPT
Downstream eye diagram
Differential common mode
range
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COMMENTS
MIN
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
TYP
MAX
UNIT
–25
25
ns
–10
10
1.25
1.5
µs
0.8
2.5
V
MAX
UNIT
Ref. USB2.0, covered by eye
diagram
VCM
Ref. USB2.0
FS TRANSMITTER
PARAMETER
COMMENTS
MIN
TYP
Low
VOL
Ref. USB2.0
0
300
mV
High (driven)
VOH
Ref. USB2.0
2.8
3.6
V
Output signal crossover
voltage
VCRS
Ref. USB2.0, covered by eye
diagram
1.3
2.0
V
Rise time
TFR
Ref. USB2.0
4
20
ns
Fall time
TFF
Ref. USB2.0
4
20
ns
Differential rise and fall time
matching
TFRFM
Ref. USB2.0, covered by eye
diagram
90%
111.11%
Driver output resistance
ZDRV
Ref. USB2.0
28
44
Ω
Full-speed data rate
TFDRATE
Ref. USB2.0, covered by eye
diagram
11.97
12.03
Mbps
- To next transition
TDJ1
Ref. USB2.0, covered by eye
diagram
–2
2
ns
- For paired transitions
TDJ2
–1
1
Source SE0 interval of EOP
TFEOPT
160
175
ns
MAX
UNIT
Source jitter total (including
frequency tolerance):
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
Upstream eye diagram
HS DIFFERENTIAL RECEIVER
PARAMETER
COMMENTS
MIN
TYP
High-speed squelch detection VHSSQ
threshold (differential signal
amplitude)
Ref. USB2.0
100
150
mV
High-speed disconnect
detection threshold
(differential signal amplitude)
Ref. USB2.0
525
625
V
VHSDSC
High-speed differential input
signaling levels
Ref. USB2.0, specified by
eye pattern templates
High-speed data signaling
VHSCM
common mode voltage range
(guidelines for receiver)
Ref. USB2.0
Receiver jitter tolerance
18
mV
–50
Ref. USB2.0, specified by
eye pattern templates
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600
mV
150
ps
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HS TRANSMITTER
PARAMETER
COMMENTS
High-speed idle level
VHSOI
High-speed data signaling
high
VHSOH
High-speed data signaling
low
VHSOL
Chirp J level (differential
voltage)
VCHIRPJ
Chirp K level (differential
voltage)
VCHIRPK
Rise Time (10% – 90%)
MIN
TYP
MAX
UNIT
Ref. USB2.0
–10
10
mV
Ref. USB2.0
360
440
mV
Ref. USB2.0
–10
10
mV
Ref. USB2.0
700
1100
mV
Ref. USB2.0
–825
–500
mV
THSR
Ref. USB2.0, covered by eye
diagram
500
Fall time (10% – 90%)
THSR
Ref. USB2.0, covered by eye
diagram
500
Driver output resistance
(which also serves as highspeed termination)
ZHSDRV
Ref. USB2.0
40.5
49.5
Ω
High-speed data range
THSDRAT
479.76
480.24
Mbps
Ref. USB2.0, covered by eye
diagram
Data source jitter
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
UART TRANSCEIVER
PARAMETER
MIN
MAX
UNIT
tPH_DP_CON
Phone D+ connect time
100
ms
tPH_DISC_DET
Phone D+ disconnect time
150
ms
fUART_DFLT
Default UART signaling rate (typical rate)
PARAMETER
COMMENTS
9600
MIN
bps
TYP
MAX
UNIT
1
Ms
2.4
3.3
3.6
V
0
0.1
0.4
V
UART Transmitter CEA-2011
Phone UART edge rates
tPH_UART_EDGE
DP_PULLDOWN asserted
Serial interface output high
VOH_SER
ISOURCE = 4 mA
Serial interface output low
VOL_SER
ISINK = –4 mA
Serial interface input high
VIH_SER
DP_PULLDOWN asserted
Serial interface input low
VIL_SER
DP_PULLDOWN asserted
Switching threshold
VTH
UART Receiver CEA-2011
2.0
0.8
V
0.8
V
2.0
V
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PULLUP/PULLDOWN RESISTORS
PARAMETER
COMMENTS
MIN
TYP
MAX
0.9
1.1
1.575
2.2
3.09
UNIT
Pullup Resistors
Bus pullup resistor on
upstream port (idle bus)
RPUI
Bus idle
Bus pullup resistor on
upstream port (receiving)
RPUA
Bus driven/driver's outputs
unloaded
1.425
High (floating)
VIHZ
Pullups/pulldowns on both
DP and DM lines
2.7
Phone D+ pullup voltage
VPH_DP_UP
Driver's outputs unloaded
3.0
Driver's outputs unloaded
14.25
Pullups/pulldowns on both
DP and DM lines
2.7
kΩ
3.6
V
3.3
3.6
V
18
24.8
kΩ
3.6
V
75
pF
0.342
V
Pulldown Resistors
Phone D+/– pulldown
RPH_DP_DWN
RPH_DM_DWN
High (floating)
VIHZ
D+/– Data line
Upstream facing port
CINUB
[1.0]
On-the-go device leakage
VOTG_DATA_LKG
[2]
22
Input impedance exclusive
of pullup/pulldown
ZINP
Driver’s outputs unloaded
300
kΩ
OTG VBUS
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
15
µs
VBUS Wakeup Comparator
VBUS wake-up delay
DELVBUS_WK_
UP
VBUS Comparators
A-device session valid
VA_SESS_VLD
0.8
1.1
1.4
V
A-device VBUS valid
VA_VBUS_VLD
4.4
4.5
4.625
V
B-device session end
VB_SESS_END
0.2
0.5
0.8
V
B-device session valid
VB_SESS_VLD
2.1
2.4
2.7
V
100
kΩ
VBUS Line
A-device VBUS input
impedance to ground
RA_BUS_IN
SRP (VBUS pulsing) capable
A-device not driving VBUS
13.77
B-device VBUS SRP
pulldown
RB_SRP_DWN
5.25 V / 8 mA, pullup voltage
=3V
0.656
10
RB_SRP_UP
(5.25 V – 3 V) / 8 mA, pullup
voltage = 3 V
0.85
1.3
B-device VBUS SRP rise
time maximum for OTG-A
communication
tRISE_SRP_UP_
0 to 2.1 V with < 13 μF load
B-device VBUS SRP rise
time minimum for standard
host connection
tRISE_SRP_UP_
B-device VBUS SRP pullup
kΩ
1.75
kΩ
34
ms
MAX
0.8 to 2.0 V with > 97 μF load
46
COMMENTS
MIN
ms
MIN
OTG ID
PARAMETER
TYP
MAX
UNIT
100
kΩ
25
kΩ
VBUS Wakeup Comparator
ID wake-up comparator
RID_WK_UP
Wakeup when ID shorted to
ground.
30
ID Comparators — ID External Resistors Specifications
ID ground comparator
20
RID_GND
ID_GND interrupt
4
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PARAMETER
COMMENTS
MIN
ID Float comparator
RID_FLOAT
ID_FLOAT interrupt
Phone ID pullup to VPH_ID_UP
RPH_ID_UP
ID unloaded (VRUSB)
70
Phone ID pullup voltage
VPH_ID_UP
Connected to VRUSB
2.5
TYP
MAX
UNIT
500
kΩ
286
kΩ
3.2
V
5.25
V
200
ID Line
90
ID line maximum voltage
USB CHARGER DETECTION
USB Charger Detection Debounce Time
MAX
UNIT
Minimum 10 ms
REQUIREMENT
DEBVBUS_TIME
PARAMETER
NB CLOCK
448
ACTIVE/SLEEP mode
TEST CONDITIONS
13.7
MIN
TYP
13.7
ms
Minimum 20 ms
DEBUSBCHG_TIM
E
896
ACTIVE/SLEEP mode
27.3
27.3
ms
Table 4. Voltages
PARAMETER
SYMBOL
MIN
MAX
UNIT
REF
0.8
2.0
V
1.4.4
0.5
0.675
V
VDAT_REF
0.25
0.4
V
VDAT_LKG
0
3.6
V
3.9
MAX
UNIT
REF
710
mA
3.6.2
Logic Threshold
VLGC
D+ Source Voltage
VDP_SRC
Data Detect Voltage
Data Line Leakage Voltage
CONDITIONS
Output current
> 250 µA
Table 5. Currents
PARAMETER
SYMBOL
CONDITIONS
MIN
Portable Device Current from
Charging Host Port during chirp
IDEV_HCHG_CHRP
Data Contact Detect Current
Source
IDP_SRC
7
13
µA
D- Sink Current
IDM_SINK
50
150
µA
Table 6. Resistances
D+ pulldown resistance
RDP_DWN
14.25
24.8
kΩ
D- pulldown resistance
RDM_DWN
14.25
24.8
kΩ
Table 7. USB Charger Detection (Wait and Debounce Timing)
USB Charger Detection (Wait and Debounce Timing)
Requirement
PARAMETER
NB
CLOCK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum 200 us
D+ Current source ontime
TIDP_SRC_ON
8
ACTIVE/SLEEP
mode (1)
244.1
244.1
µs
Minimum 40 ms
D+ Voltage source ontime
TVDP_SRC_ON
1792
ACTIVE/SLEEP
mode (1)
54.7
54.7
ms
Minimum 40 ms
D+ Voltage source off
to high current
TVDP_SRC_HICRNT
1792
ACTIVE/SLEEP
mode (1)
54.7
54.7
ms
Minimum 2 s
DATA_CONTACT_DET
ECT Timeout
TDCD_TIMEOUT
89600
ACTIVE/SLEEP
mode (1)
2.73
2.73
s
(1)
Note: LS Device mode not supported
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MADC
PARAMETER
CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
10
Input dynamic range for external
input ADCIN0
Bit
0
1.5
V
–1
1
LSB
2
LSB
28.5
mV
MADC voltage reference
1.5
Differential nonlinearity
Integral nonlinearity
Best fitting
–2
Offset
Best fitting
–28.5
Input bias
V
μA
1
Input capacitor CBANK
10
pF
Input current leakage
1
μA
MADC Analog Input Range and Prescaler Ratio
MADC CHANNEL
INT/EXT
ADCIN0: Generalpurpose input (1)
External
ADCIN1:7 Reserved
Internal
ADCIN8: VBUS Voltage
(VBUS)
Internal
ADCIN9: Reserved
Internal
ADCIN10:11 Reserved
Internal
ADCIN12: Main battery
voltage (VBAT)
Internal
ADCIN13:15 Reserved
Internal
(1)
(2)
(3)
ANALOG INPUT RANGE
(V)
PRESCALER
OUTPUT RANGE (V)
MIN
MAX
DIVIDER
RATIO
1.5
N/A
N/A
1
N/A
N/A
N/A
N/A
MIN
MAX
0.0
N/A
NOTE
No prescaler
Not used
Prescaler in USB
subchip.
0.0
6.5
0.0
1.5
3/14
N/A
N/A
N/A
N/A
N/A
2.7
4.7
0.675
1.175
0.25
N/A
N/A
N/A
N/A
N/A
Rdivider = (6 × 2.76
kΩ)/(28 × 2.76 kΩ)
(typ) (2)
Not used
Prescaler integrated
Rdivider = 9.85 kΩ/(4 ×
9.85 kΩ) (typ) (3)
General-purpose input has to be tied to ground when TPS65921 internal power supply (VINTANA1) is off.
Tolerance for resistors-type (PL_VHSR): ±19%
Tolerance for resistors-type (PL_HR): ±12%
The table below summarizes the sequence conversion timing characteristics. Figure 5 shows one conversion
sequence general timing diagram.
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
F
Running frequency
1
MHz
T = 1/F
Clock period
1
μs
N
Number of analog inputs to convert in a
single sequence
0
16
Tstart
SW1, SW2, or USB asynchronous request
or real-time STARTADC request
3
4
22
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Tsettling time
Settling time to wait before sampling a
stable analog input (capacitor bank charge
time)
Tsettling is calculated from the max((Rs +
Ron)*Cbank) of all possible input sources
(internal or external). Ron is the resistance
of the selection analog input switches (5
kOHM). This time is software
programmable by OCP register; default
value is 12 µs.
5
12
μs
260
Tstartsar
The successive approximation registers
ADC start time
1
μs
Tadc time
The successive approximation registers
ADC conversion time
10
μs
Tcapture time
Tcapture time is the conversion result
capture time.
2
μs
Tstop
1
2
Full Conversion
Sequence Time
Only one channel (N = 1) (1)
22
39
All channels (2)
352
624
Conversion
Sequence Time
Without Tstart and Tstop: Only one channel
(N = 1) (1)
18
33
Without Tstart and Tstop: All channels (1)
288
528
STARTADC pulse
duration
(1)
(2)
STARTADC period is T
μs
μs
μs
μs
0.33
General-purpose input ADCIN0 must be tied to ground when TPS65921 internal power supplies (VINTANA1) is off.
Total Sequence Conversion Time General Formula: Tstart + N × (1 + Tsettling + Tadc + Tcapture) + Tstop.
This table is illustrated in Figure 5. The Busy parameter indicates that a conversion sequence is running, and the
channel N result register parameter corresponds to the result register of RT/GP selected channel.
T one conversion
Tstart
Tstartsar
Tcapture
Tsettling
Tadc
Tstop
madc_clk
Busy
mux_sel_lowv[3:0]
Channel N selected
Acquire_lowv
start_sar_lowv
out_lowv[9:0]
Channel N
result register
New channel N value
Channel X value
Old value
New value
SWCS048-005
Figure 5. One Conversion Sequence General Timing Diagram
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MADC Power Consumption
PARAMETER
TEST CONDITIONS
Power on consumption
MIN
TYP
Running frequency f = 1 MHz
(1)
UNIT
mA
1
μA
1
Power down consumption
MAX
(1)
The consumption is given in stand-alone mode.
TPS65921 INTERFACE TARGET FREQUENCIES
Table below assumes testing over the recommended operating conditions.
I/O INTERFACE
INTERFACE DESIGNATION
TARGET FREQUENCY
1.5 V
SmartReflex I2C
I2C Interface
General-purpose I2C
USB
USB
JTAG
Slave high-speed mode
3.6 Mbps
Slave fast-speed mode
400 kbps
Slave standard mode
100 kbps
High speed
480 Mbps
Full speed
12 Mbps
Low speed
1.5 Mbps
Real/View® ICE tool
30 MHz
XDS560 and XDS510 tools
30 MHz
Lauterbach™ tool
30 MHz
I2C Timing
The TPS65921 provides two I2C HS slave interfaces (one for general-purpose and one for SmartReflex). These
interfaces support the standard mode (100 kbps), fast mode (400 kbps), and HS mode (3.5 Mbps). The generalpurpose I2C module embeds four different slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and
ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5). The master mode is not
supported.
Table 8 and Table 9 assume testing over the recommended operating conditions.
START
I1
I2C.SCL
RESTART
I2
1
8
9
1
I8
8
9
I8
I3
I2C.SDA
STOP
I4
I7
MSB
LSB
ACK
I9
MSB
LSB
ACK
SWCS048-006
2
Figure 6. I C Interface—Transmit and Receive in Slave Mode
24
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Table 8. I2C Interface Timing Requirements (1) (2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-Speed Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
100
ns
70
ns
Slave Fast-Speed Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
µs
0
0.9
µs
Slave Standard Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
250
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
4.7
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
4
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
4
µs
(1)
(2)
The input timing requirements are given by considering a rising or falling time of:
80 ns in high-speed mode (3.4 Mbits/s)
300 ns in fast-speed mode (400 Kbits/s)
1000 ns in standard mode (100 Kbits/s)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
Table 9. I2C Interface Switching Requirements (1) (2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
Slave Fast-speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
1.3
µs
I2
tw(SCLH)
Pulse duration, SCL high
0.6
µs
Slave Standard Mode
I1
tw(SCLL)
Pulse duration, SCL low
4.7
µs
I2
tw(SCLH)
Pulse duration, SCL high
4
µs
(1)
(2)
The capacitive load is equivalent to:
100 pF in high-speed mode (3.4 Mbits/s)
400 pF in fast-speed mode (400 Kbits/s)
400 pF in standard mode (100 Kbits/s)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
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JTAG INTERFACES
Table 10 and Table 11 assume testing over the recommended operating conditions.
JL1
JL2
JL2
JTAG.TCK
JL3
JL4
JL5
JL6
JTAG.TDI
JTAG.TMS
JL7
JTAG.TDO
SWCS048-007
Figure 7. JTAG Interface Timing
The input timing requirements are given by considering a rising or falling edge of 7 ns.
JTAG Interface Timing Requirements
Table 10. JTAG Interface Timing Requirements
NO.
PARAMETER
MIN
MAX
UNIT
Clock
JL1
tc(TCK)
Cycle time, JTAG.TCK period
JL2
tw(TCK)
Pulse duration, JTAG.TCK high or
low (1)
30
JL3
tsu(TDIV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
8
ns
JL4
th(TDIV-TCKH)
Hold time, JTAG.TDI valid after
JTAG.TCK high
5
ns
JL5
tsu(TMSV-TCKH)
Setup time, JTAG.TMS valid before
JTAG.TCK high
8
ns
JL6
th(TMSV-TCKH)
Hold time, JTAG.TMS valid after
JTAG.TCK high
5
ns
0.48 × P
ns
0.52 × P
ns
Read Timing
(1)
P = JTAG.TCK clock period
The capacitive load is equivalent to 35 pF.
26
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JTAG Interface Switching Characteristics
Table 11. JTAG Interface Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
0
14
ns
MIN
MAX
UNIT
Write Timing
td(TCK-TDOV))
JL7
NO.
Delay time, JTAG, TCK active edge to
JTAG.TDO valid
PARAMETER
Clock
JL1
tc(TCK)
Cycle time, JTAG.TCK period
JL2
tw(TCK)
Pulse duration, JTAG.TCK high or
low (1)
30
ns
JL3
tsu(TDIV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
8
ns
JL4
th(TDIV-TCKH)
Hold time, JTAG.TDI valid after
JTAG.TCK high
5
ns
JL5
tsu(TMSV-TCKH)
Setup time, JTAG.TMS valid before
JTAG.TCK high
8
ns
JL6
th(TMSV-TCKH)
Hold time, JTAG.TMS valid after
JTAG.TCK high
5
ns
0.48 × P
0.52 × P
ns
Read Timing
(1)
P = JTAG.TCK clock period
Debouncing Time
Debounce times are listed in Table 12.
Table 12. Debouncing Time
DEBOUNCING FUNCTIONS
BLOCK
PROGRAMMABLE
DEBOUNCING
TIME
DEFAULT
No
580 μs
580 μs
Main battery low threshold detection (<2.7 V)
No
60 μs
60 μs
Main battery plug detection
No
60 μs
60 μs
Main battery charged threshold (<3.2 V)
Battery monitoring
Debouncing functions interrupt generation
debounce
POWER
No
125.6 μs
125.6 μs
Plug/unplug detection VBUS (1)
USB
Yes
0 to 250 ms
(32/32768-second
stgif)
30 ms
Plug/unplug detection ID (2)
USB
Yes
0 to 250 ms
(32/32768-second
stgif)
50 ms
Debouncing functions interrupt generation
debounce for VBUS and ID (3)
POWER
Yes
0 to 233 ms
28 ms
Hot-die detection
Thermistor
No
60 μs
60 μs
No
60 μs
60 μs
31.25 ms
31.25 ms
Thermal shutdown detection
PWRON (4)
Start/stop button
No
NRESWARM
Button reset
No
60 μs
60 μs
Yes
0 or 28 ms ± 2
ms
0 ms
MMC1/2 (plug/unplug)
(1)
(2)
(3)
(4)
GPIO
Programmable in the VBUS_DEBOUNCE register.
Programmable in the ID_DEBOUNCE register.
Programmable in the RESERVED_E[2:0] CFG_VBUSDEB register
The PWRON signal is debounced 1024 × CLK32K (maximum 1026 × CLK32K) falling edge in master mode.
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DEVICE INFORMATION
Figure 8 shows the ball locations for the 120-ball plastic ball grid array (PBGA) package and is used in
conjunction with ball description to locate signal names and ball grid numbers.
6,10
SQ
5,90
5,00 TYP
0,50
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
0,50
5,00 TYP
1 2 3 4 5 6 7 8 9 10 11
Bottom View
0,77
0,71
1,00 MAX
Seating Plane
0,35
0,25
Ø 0,05 M
0,08
0,25
0,15
SWCS048-008
Figure 8. PBGA Bottom View
Table 13. Terminal/Pin Functions
NAME
ADCIN0
BALL
SUPPLIES
F2
TYPE
I/O
DESCRIPTION
PU/PD
Analog
I/O
General-purpose ADC input
NO
ADC conversion
request/JTAG test data
input
NO
STARTADC
H7
VDDIO/DGND
Digital
I
I2C.CNTL.SDA
C4
VDDIO/DGND
Digital
I/O
I2C bidirectional data signal
External PU
External PU
External PU
I2C.CNTL.SCL
B3
VDDIO/DGND
Digital
I/O
I2C bidirectional clock
signal
I2C.SR.SDA
D4
VDDIO/DGND
Digital
I/O
HS I2C bidirectional data
signal
2
I2C.SR.SCL
A3
VDDIO/DGND
Digital
I/O
HS I C bidirectional Clock
signal
External PU
PWRON
D5
VBAT/GND
Digital
I
Input detects a control
command to start or stop
the system.
External PU
REGEN
G3
Digital
O
Enable signal for external
LDO
PU
28
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Table 13. Terminal/Pin Functions (continued)
MSECURE
G8
VDDIO/DGND
Digital
I
Security and digital rights
management
BOOT0
E5
VBAT/GND
Digital
I
Power-up sequence
selection
Programmable
PD (default
active)
BOOT1
F6
VBAT/GND
Digital
I
Power-up sequence
selection
Programmable
PD (default
active)
NRESPWRON
E7
VDDIO/DGND
Digital
O
Output control the
NRESPWRON of the
application processor
NO
NRESWARM
H8
VDDIO/DGND
Digital
I
Warm reset signal
PU
NO
NO
NSLEEP1
K4
VDDIO/DGND
Digital
I
ACTIVE-SLEEP state
transition control signal
INT1
A9
VDDIO/DGND
Digital
O
Output line interrupt
NO
SYSEN
B9
VDDIO/DGND
Digital
O
System enable output
NO
CLKEN
F10
VDDIO/DGND
Digital
O
Clock Enable
NO
PD disabled in
ACTIVE state
32KCLKOUT
G6
VDDIO/DGND
Digital
O
32-kHz clock output
32KXOUT
G11
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
NO
32KXIN
H11
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
NO
NO
HFCLKIN
C8
VDDIO/DGND
Analog
I
Sine wave or square wave
input
HFCLKOUT
K8
VDDIO/DGND
Digital
O
50% duty cycle square
wave output
NO
G10
VREF/REFGND
Analog
O
Bandgap voltage
NO
K7
AGND
Analog
I/O
Substrate ground
NO
AGND
H10
REFGND
Analog
I/O
Reference ground
NO
DGND
B8
DGND
Power
I/O
Digital ground
NO
NO
VREF
GND_AGND
Power
I
Supply for I/O buffers
(VDDIO)
Power
I
Not used. Must be
grounded
NO
E9, E10, E11
Power
I
VDD1 DCDC input
NO
VDD1.GND
A11, B10,
B11
Power
I/O
VDD1 DCDC power ground
NO
VDD1.L
C10, C11,
D10
Power
O
VDD1 DCDC switched
output
NO
IO.1P8
A10
BKBAT
G9
VDD1.IN
VDD1.OUT
VBACKUP/AGND
D11
Analog
I
VDD1 feedback voltage
PD
VDD2.IN
K10, L10
Power
I
VDD2 DCDC input
NO
VDD2.GND
J10, J11
Power
I/O
VDD2 DCDC power ground
NO
VDD2.L
K11, L11
Power
O
VDD2 DCDC switched
output
NO
H9
Analog
I
VDD2 feedback voltage
PD
VIO.IN
K2, L2
Power
I
VIO DCDC input
NO
VIO.GND
J1, J2
Power
I/O
VIO DCDC power ground
NO
VIO.L
K1, L1
Power
O
VIO DCDC switched output
NO
H1
Analog
I
VIO feedback voltage
PD
VAUX12S.IN
F1
Power
I
VAUX2 LDO input
NO
VAUX2.OUT
G1
Power
O
VAUX2 regulator output
PD
VPLLA3R.IN
A6
Power
I
VPLL1/VRTC LDO input
NO
VPLL1.OUT
A8
Power
O
VPLL1 LDO regulator
output
PD
VDD2.OUT
VIO.OUT
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Table 13. Terminal/Pin Functions (continued)
VRTC.OUT
B5
Power
O
VRTC internal LDO
regulator output (internal
use only)
PD
VINT.IN
A7
Power
I
VINTDIG LDO input
NO
PD
VINTANA1.OUT
D1
Power
O
VINTANA1 internal LDO
regulator output (internal
use only)
VINTANA2.OUT
A2
Power
O
VINTANA2 internal LDO
regulator output (internal
use only)
PD
VDAC.IN
C1
Power
I
VDAC/VINTANA1/VINTAN2
LDO input
NO
VDAC.OUT
E1
Power
O
VDAC LDO regulator output
PD
VINTDIG.OUT
B7
Power
O
VINTDIG internal LDO
regulator output (internal
use only)
PD
VMMC1.OUT
A1
Power
O
VMMC1 LDO regulator
output
PD
VBAT.USB
K6
Power
I
VINTUSBiP5,VINTUSB1P8,
VUSB.3P1 input regulator
NO
VUSB.3P1
L6
Power
O
VUSB.3P1 LDO regulator
output
PD
VINTUSB1P8.OUT
J6
Power
O
VUSB1P8 LDO regulator
output (internal use only)
PD
VINTUSB1P5.OUT
J5
Power
O
VUSB1P5 LDO regulator
output (internal use only)
PD
TESTV1
H2
Analog
IO
Analog test pin 1
NO
TESTV2
C9
Analog
IO
Analog test pin 2
NO
PD
TEST
D3
VDDIO/DGND
Digital
IO
Selection between JTAG
mode and application mode
AVSS1
F3
AGND
Power
I/O
Analog ground
NO
AVSS2
H6
AGND
Power
I/O
Analog ground
NO
AVSS3
F9
AGND
Power
I/O
Analog ground
NO
AVSS4
A4
AGND
Power
I/O
Analog ground
NO
VBUS
K5
Power
VBUS power rail
NO
DP/UART3.RXD
L7
Analog
I/O
USB differential data line
NO
DN/UART3.TXD
L8
Analog
I/O
USB differential data line
NO
ID
J7
VDDIO/DGND
Digital
I/O
USB ID
NO
UCLK
D6
VDDIO/DGND
Digital
I/O
HS USB Clock
NO
STP/GPIO.9
E6
VDDIO/DGND
Digital
I/O
HS USB Stop
NO
DIR/GPIO.10
A5
VDDIO/DGND
Digital
I/O
HS USB Direction
NO
NXT/GPIO.11
C5
VDDIO/DGND
Digital
I/O
HS USB Next
NO
DATA0/UART4.TXD
B6
VDDIO/DGND
Digital
I/O
HS USB Data0
NO
DATA1/UART4.RXD
C6
VDDIO/DGND
Digital
I/O
HS USB Data1
NO
DATA2/UART4.RTSI
C7
VDDIO/DGND
Digital
I/O
HS USB Data2
NO
DATA3/UART4.CTSO/
GPIO.12
D7
VDDIO/DGND
Digital
I/O
HS USB Data3
NO
DATA4/GPIO.14
F8
VDDIO/DGND
Digital
I/O
HS USB Data4
NO
DATA5/GPIO.3
F11
VDDIO/DGND
Digital
I/O
HS USB Data5
NO
DATA6/GPIO.4
E8
VDDIO/DGND
Digital
I/O
HS USB Data6
NO
DATA7/GPIO.5
D9
VDDIO/DGND
Digital
I/O
HS USB Data7
NO
CP.IN
L4
Power
I/O
Charge pump input voltage
NO
CP.GND
J3
Power Gnd
I/O
Charge pump ground
NO
30
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Table 13. Terminal/Pin Functions (continued)
CP.CAPP
L5
Analog
I/O
Charge pump flying
capacitor P
NO
CP.CAPM
L3
Analog
I/O
Charge pump flying
capacitor M
NO
KPD.C0
B4
VDDIO/DGND
Open Drain
O
Keypad column 0
PU
KPD.C1
D2
VDDIO/DGND
Open Drain
O
Keypad column 1
PU
KPD.C2
E2
VDDIO/DGND
Open Drain
O
Keypad column 2
PU
KPD.C3
B2
VDDIO/DGND
Open Drain
O
Keypad column 3
PU
KPD.C4
C2
VDDIO/DGND
Open Drain
O
Keypad column 4
PU
KPD.C5
E4
VDDIO/DGND
Open Drain
O
Keypad column 5
PU
KPD.C6
E3
VDDIO/DGND
Open Drain
O
Keypad column 6
PU
KPD.C7
F4
VDDIO/DGND
Open Drain
O
Keypad column 7
PU
KPD.R0
H5
VDDIO/DGND
Digital
I
Keypad row 0
PU
KPD.R1
G4
VDDIO/DGND
Digital
I
Keypad row 1
PU
KPD.R2
H4
VDDIO/DGND
Digital
I
Keypad row 2
PU
KPD.R3
G5
VDDIO/DGND
Digital
I
Keypad row 3
PU
KPD.R4
J4
VDDIO/DGND
Digital
I
Keypad row 4
PU
KPD.R5
J8
VDDIO/DGND
Digital
I
Keypad row 5
PU
KPD.R6
G7
VDDIO/DGND
Digital
I
Keypad row 6
PU
KPD.R7
F5
VDDIO/DGND
Digital
I
Keypad row 7
PU
Battery input voltage
(Sense)
NO
VBAT
K3
CLKREQ
D8
TEST.RESET
J9
VPROG
H3
JTAG/TCK/BERCLK
F7
VDDIO/DGND
VBAT/GND
VDDIO/DGND
Power
I/O
Digital
I
Clock request line
PD
Digital
I
Reset the device (except
the state-machine)
PD
Analog
I
Reserved. Must be
grounded.
NO
Digital
I
JTAG clock input
NO
PD
PD
GPIO.0/CD1/JTAG.TD
O
L9
VDDIO/DGND
Digital
I/O
JTAG test output or
GPIO0/card detection 1
GPIO.1/CD2/JTAG.TM
S
K9
VDDIO/DGND
Digital
I/O
JTAG test mode state or
GPIO1/card detection 2
GPIO.2/TEST1
G2
VDDIO/DGND
Digital
I
GPIO/Digital test pin
Power
I
VMMC1 input LDO
NO
N/A
N/A
N/A
N/A
VMMC1.IN
B1
N/A
C3
N/A
Programmable
PD
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1
2
3
4
5
6
7
8
9
10
11
A
VMMC1.OUT
VINTANA2.
OUT
VMODE2/
I2C.SR.SCL
AVSS4
DIR/GPIO.10
VPLLA3R.IN
VINT.IN
VPLL1.OUT
INT1
IO.1P8
VDD1.GND
A
B
VMMC1.IN
KPD.C3
I2C.CNTL.
SCL
KPD.C0
VRTC.OUT
DATA0/
UART4.TXD
VINTDIG.
OUT
DGND
SYSEN
VDD1.GND
VDD1.GND
B
C
VDAC.IN
KPD.C4
#N/A
I2C.CNTL.
SDA
NXT/GPIO.11
DATA1/
UART4.RXD
DATA2/
UART4.RTSI
HFCLKIN
TESTV2
VDD1.L
VDD1.L
C
D
VINTANA1.
OUT
KPD.C1
TEST
PWROK2/
12C.SR.SDA
PWRON
UCLK
DATA3/
UART4.
CTSO/
GPIO.12
CLKREQ
DATA7/
GPIO.5
VDD1.L
VDD1.OUT
D
E
VDAC.OUT
KPD.C2
KPD.C6
KPD.C5
BOOT0
DATA6/
GPIO.4
VDD1.IN
VDD1.IN
VDD1.IN
E
F
VAUX12S.IN
ADCIN0
AVSS1
KPD.C7
KPD.R7
BOOT1
JTAG.TCK/
BERCLK
DATA4/
GPIO.14
AVSS3
CLKEN
DATA5/
GPIO.3
F
G
VAUX2.OUT
GPIO.2/
TEST1
REGEN
KPD.R1
KPD.R3
32KCLKOUT
KPD.R6
MSECURE
BKBAT
VREF
32KXOUT
G
H
VIO.OUT
TESTV1
VPROG
KPD.R2
KPD.R0
AVSS2
STARTADC
NRESWARM
VDD2.OUT
AGND
32KXIN
H
J
VIO.GND
VIO.GND
CP.GND
KPD.R4
ID
KPD.R5
TEST.RESET
VDD2.GND
VDD2.GND
J
K
VIO.L
VIO.IN
VBAT
NSLEEP1
VBUS
VBAT.USB
GND_AGND
HFCLKOUT
GPIO.1/CD2/
JTAG.TMS
VDD2.IN
VDD2.L
K
L
VIO.L
VIO.IN
CP.CAPM
CP.IN
CP.CAPP
VUSB.3P1
DP/UART3.
RXD
DN/UART3.
TXD
GPIO.0/CD1/
JTAG.TD0
VDD2.IN
VDD2.L
L
1
2
3
4
5
6
7
8
9
10
11
STP/GPIO.9 NRESPWRON
VINTUSB1P5. VINTUSB1P8.
OUT
OUT
SWCS048-009
Figure 9. Ball Placement (Top View)
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VREF
REFGND
VINTANA2
VINTANA1
VINT.IN
TEST/GPIO
TESTV1
TESTV2
TEST
JTAG.TCK
JTAG.TDO
JTAG.TMS
JTAG.TDI
VPROG
SWCS048F – MARCH 2010 – REVISED MARCH 2012
VRTC_OUT
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REFS
VRTC
AGND
VBAT
VDD1_IN
TEST/MUXed I/O’s
VINTANA2
VINTANA1
VDD1_L
VDD1
IO.1P8
DGND
VDD1_FDBK
SRI2C_SCL
VDD1_GND
VDD2_IN
I2C Smart-Reflex
SRI2C_SDA
VDD2_L
32KXIN
32KXOUT
VDD2
Xtal
32K
HFCLKIN
HFCLKOUT
VDD2_FDBK
RTC
Clock sys
32KCLKOUT
VDD2_GND
VIO_IN
Clock
slicer
VIO_L
VIO
MSECURE
VIO_FDBK
BOOT0
BOOT1
VIO_GND
RESPWRON
NRESWARM
VPLLA3RIN
Power control
PWRON
NSLEEP
VPLL1OUT
Control I/Os
VPLL1
INT
SYSEN
REGEN
CLKEN
TESTRESET
CLKREQ
VDAC.IN
VDAC.OUT
VDAC
CTLI2C_SCL
I2C control
CTLI2C_SDA
Control, Data
and Test
logic
DP
DM
MUX
10- bit
ADC
VMMC1OUT
VMMC1
VAUX12SIN
VAUX2_OUT
ULPI
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
NXT
DIR
STP
UCLK
ID
VBUS
Scalars
VMMC1_IN
ADCIN0
VAUX2
USB 2.0
OTG
CP_IN
USB
CP
USB
PHY
CP_CAPP
CP_CAPM
CP_GND
AVSS1
KPD_R0
KPD_R1
KPD_R2
KPD_R3
KPD_R4
KPD_R5
KPD_R6
KPD_R7
KPD_C7
KPD_C6
KPD_C5
KPD_C4
KPD_C3
KPD_C2
KPD_C1
KPD_C0
VINT.IN
VINTDIG
VINTUSB1P8_OUT
KEY
PAD
VINTDIG
VINTUSB1P5
VBAT_USB
VINTUSB1P8
VINTUSB1P5_OUT
VUSB3P1
VUSB3P1
AVSS2
AVSS3
AVSS4
SWCS048-010
Figure 10. Functional Block Diagram
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DETAILED DESCRIPTION
CLOCK SYSTEM
Figure 11 shows the TPS65921 clock overview.
Device
32KXIN
OR
32KCLKOUT
OR
32KXOUT
32 kHz
OR
HFCLKIN
HFCLKOUT
SWCS048-011
Figure 11. TPS65921 Clock Overview
The TPS65921 accepts two sources of high-stability clock signals:
• 32KXIN/32KXOUT: on-board 32-kHz crystal oscillator (optionally, an external 32-kHz input clock can be
provided)
• HFCLKIN: an external high-frequency clock (19.2, 26, or 38.4 MHz)
The TPS65921 has the capability to provide:
• 32KCLKOUT digital output clock
• HFCLKOUT digital output clock with the same frequency as HFCLKIN input clock
32-kHz OSCILLATOR
It is possible to use the 32-kHz input clock with either an external crystal or clock source. There are four
configuration, one with the external crystal and three without.
• An external 32.768-kHz crystal connected on the 32KXIN / 32KXOUT balls. This configuration is available for
the master mode only.
• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be driven to a dc value of the square- or sine-wave amplitude divided by 2. This
configuration is recommended if a large load is applied on the 32KXOUT pin.
• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The
32KXOUT pin can be left floating. This configuration is used if no charge is applied on the 32KXOUT pin.
• The oscillator is in bypass mode and a square-wave input can be applied to the 32KXIN pin with amplitude of
1.8 V. The 32KXOUT pin can be left floating. This configuration is used if the oscillator is in bypass mode
(default configuration in Slave mode).
Figure 12 shows the block diagram for the 32.768-kHz clock output.
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IO_1P8
(1.8 V)
OR
32KXIN
32-kHz
OSC
OR
32KCLKOUT
32 kHz
32KXOUT
RTC
SWCS048-014
Figure 12. 32.768-kHz Clock Output Block Diagram
The TPS65921 device has an internal 32.768-kHz oscillator connected to an external 32.768-kHz crystal through
the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the 32KXIN input (see Figure 12).
The TPS65921 device also generates a 32.768-kHz digital clock through the 32KCLKOUT pin and can broadcast
it externally to the application processor or any other devices. The 32KCLKOUT clock is broadcast by default in
the TPS65921 active mode but can be disabled if it is not used.
The 32.768-kHz clock (or signal) is also used to clock the RTC (real-time clock) embedded in the TPS65921.
The RTC is not enabled by default. It is up to the host processor to set the correct date and time and to enable
the RTC functionality.
The 32KCLKOUT output buffer can drive several devices (up to 40-pF load). At start-up, the 32.768-kHz output
clock (32KCLKOUT) must be stabilized (frequency/duty cycle) prior to the signal output. Depending on the startup condition, this may delay the start-up sequence.
CLOCK SLICER
Figure 13 shows the clock slicer block diagram.
BYPASS, PWRDN, PWRSEL
PL_HR resistance
HFCLKIN
OR
CDM
clamp
Cc
HFCLKOUT
PWRDN, PWRSEL
SWCS048-015
Figure 13. Clock Slicer Block Diagram
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The clock slicer is disabled by default and enabled when the CLKEN pad is high. The slicer transforms the
HFCLKIN clock input signal into a squared clock signal used internally by the TPS65921 device and also outputs
it for external use. The HFCLKIN input signal can be:
• A sinusoid with peak-to-peak amplitude varying from 0.3 to 1.45 V
• A square clock signal of amplitude 1.85 V maximum. In the case of a square clock signal, the slicer is
configured in bypass or power-down mode. If a square-wave input clock is provided, it is recommended to
switch the block to bypass mode when possible to avoid loading the clock.
The HFCLKIN input clock frequency must be 19.2, 26, or 38.4 MHz.
Four different modes are programmable by register. By default, the slicer is in high-performance application
mode:
• Bypass mode (BP): In BP mode, which overrides all the other modes, the input signal is directly connected to
the output through some buffers. The input is a rail-to-rail square wave.
• Power-down mode (PD): During PD mode, the cell does not consume any current if bypass mode is not
active.
• Low-power application mode (LP): In LP mode, the input sine wave is converted to a CMOS signal (square
wave) with low power consumption.
• High-performance application mode (HP): In HP mode, the input sine wave is converted to a CMOS signal
(square wave). It has lower duty cycle degradation and lower input-to-output delay in comparison to the lowpower mode, but it consumes more current. The drive of the squaring inverter is increased by connecting
additional inverters in parallel. Details can be found in the clock slicer electrical characteristics table.
Figure 14 shows the HFCLKIN clock distribution.
HFCLKIN
Slicer
HFCLKOUT
Clock
generator
Slicer bypass
SLICER_OK
Timer
CLKEN
Main state-machine
CLKREQ
SLEEP1
Optional request
configurable by software
only for legacy support
SWCS048-016
Figure 14. HFCLKIN Clock Distribution
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When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the CLKREQ
pin. As a result, the TPS65921 device immediately sets CLKEN to 1 to warn the clock provider in the system
about the clock request and starts a timer (maximum of 10 ms and uses the 32.768-kHz clock). Once the timer
expires, the TPS65921 device opens a gated clock, the timer automatically reloads the defined value and a highfrequency output clock signal is available through the HFCLKOUT pin. The output drive of HFCLKOUT is
programmable (low drive (MISC_CFG[CLK_HF_DRV] = 0) maximum load 20 pF, high drive
(MISC_CFG[CLK_HF_DRV] = 1) maximum load 30 pF), by default it is programmed to support Low Drive.
CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.
Figure 15 shows an example of the wired-OR clock request.
Device
PERIPH1
VIO
CLKREQ
PERIPH2
VIO
PERIPHn
VIO
SWCS048-017
Figure 15. Example of Wired-OR Clock Request
The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround
support, the NSLEEP1 signal can also be used as a clock request even if it is not its primary goal. By default,
this feature is disabled and must be enabled individually by setting the register bits associated with each signal.
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POWER PATH
Step-Down Converters
Depending on the system requirements, and also to optimize mean consumption, three operating modes are
allowed for each step-down converter:
• Off/power-down mode: Output voltage is not maintained, and power consumption is null
• Active: DCDC can deliver its nominal output voltage with a full load current capability.
• Sleep: The nominal output voltage is maintained with low power consumption, but also with a low load-current
capability.
The SMPS operates with three modulation schemes:
• Light pulse frequency modulation (PFM)
• Pulse skipping mode (PSM)
• Continuous pulse-width modulation (PWM)
Each DCDC, all of which have the same electrical characteristics, has an integrated RC oscillator. The use of
these RC oscillators is configurable through register bits, and by default the RC oscillator of VDD1 is used for all
DCDC.
LDO
The VPLL1 programmable LDO regulator is high-PSRR, low-noise, linear regulator used for the host processor
PLL supply.
The VDAC programmable LDO regulator is a high-PSRR, low-noise, linear regulator that powers the host
processor dual-video DAC. It is controllable with registers through I2C and can be powered down.
The VMMC1 LDO regulator is a programmable linear voltage converter that powers the MMC slot. It includes a
discharge resistor and over-current protection (short circuit). This LDO regulator can also be turned off
automatically when the MMC card extraction is detected (through one dedicated GPIO). The VMMC1 LDO can
be powered through an independent supply other than the battery; for example, a charge pump. In this case, the
input from the VMMC1 LDO can possibly be higher than the battery voltage.
The VAUX2 general-purpose LDO regulator powers the auxiliary devices.
The VRRTC voltage regulator is a programmable, LDO, linear voltage regulator supplying (1.5 V) the embedded
RTC (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC regulator is also the
supply voltage of the power-management digital state-machine. The VRRTC regulator is supplied from the UPR
line, switched on by the main battery. The VRRTC output is present as long as a valid energy source is present.
The VRRTC line is supplied by an LDO when VBAT > 2.7 V, and a clamp circuit when VBAT < 2.7 V.
The VINTDIG LDO regulator supplies the TPS65921 digital blocks.
To supply the TPS65921 analog blocks, there are two LDOs: VINTANA1 (1.5 V) and VINTANA2 (2.75 V/2.5 V).
The 2.5-V setting is selected when the battery voltage falls below 3.0 V.
The VUSB3V1 internal LDO regulator powers the USB PHY, charger detection, and OTG of the USB subchip
inside the TPS65921 device.
It can take its power from two possible sources:
• VBAT.USB (only for high battery voltages)
• VBUS (only in low-power mode)
See Charge-pump section for more details.
The USB standard requires data lines to be biased with pullups biased from a > 3.0 V supply, USB PHY cannot
directly operate from VBAT.USB for battery voltages lower than 3.3 V.
In such case, VBUS should be supplied by a boosted voltage to ensure enough overhead for USB LDO
operation. An internal charge pump (whose output is connected to VBUS) can be used for this purpose.
To select between these two power sources, a power mux is connected to the VUSB3V1 LDO supply.
The VUSB1V8 and VUSB1V5 internal LDO regulators power the USB subchip inside the TPS65921 device.
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The short-circuit current for the LDOs and DCDCs in the TPS65921 device is approximately twice the maximum
load current. In certain cases when the output of the block is shorted to ground, the power dissipation can
exceed the 1.2 W requirement if no action is taken. A short-circuit protection scheme is included in the
TPS65921 device to ensure that if the output of an LDO or DCDC is short-circuited, then the power dissipation
does not exceed the 1.2 W level.
The three USB LDOs VUSB3V1, VUSB1V8, and VUSB1V5 are included in this short circuit protection scheme
which monitors the LDO output voltage at a frequency of 1 Hz, and generates an interrupt when a short circuit is
detected.
The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the LDO
voltage drops below this reference value (0.5 V or 0.75 V programmable). In the case of the VUSB3V1 and
VUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).
If a short circuit is detected on VUSB3V1, then the power subchip FSM switches this LDO to sleep-mode.
If a short circuit is detected on VUSB1V8 or VUSB1V5, then the power subchip FSM switches the relevant LDO
off.
Power Reference
The bandgap voltage reference is filtered (RC filter), using an external capacitor connected across the VREF
output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered inside the
device. The bandgap is started in fast mode (not filtered) and is set automatically by the power state-machine in
slow mode (filtered, less noisy) after switch on.
Power Use Cases
The TPS65921 device has two modes:
• Master: The TPS65921 device decides to power up or down the system and control the other power ICs in
the system with the SYSEN output.
• Slave: The TPS65921 device is controlled by another power IC with a digital signal on the PWRON input.
There is no battery management in slave mode.
The modes corresponding to BOOT0–BOOT1 combination value are:
BOOT0
BOOT1
MC021 (1)
NAME
Master_C021_Generic 10
1
0
SC021
Slave_C021_Generic 11
1
1
(1)
DESCRIPTION
Boot mode for OMAP3430 is c021 Master boot mode.
Process modes define:
• The boot voltage for the host core
• The boot sequence associated with the process
• The DVFS protocol associated with the process
MODE
C021.M
Boot core voltage
1.2 V
Power sequence
VIO followed by VPLL1, VDD2, VDD1
DVFS protocol
SmartReflex interface (I2C high speed)
Regulator states depending on use cases:
REGULATOR
MODE: C021 (MASTER/SLAVE)
BACKUP
WAIT ON
SLEEP NO LOAD
ACTIVE NO LOAD
VAUX2
OFF
OFF
OFF
OFF
VMMC1
OFF
OFF
OFF
OFF
VPLL1
OFF
OFF
SLEEP
ON
VDAC
OFF
OFF
OFF
OFF
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VINTANA1
OFF
OFF
SLEEP
ON
VINTANA2
OFF
OFF
SLEEP
ON
VINTDIG
OFF
OFF
SLEEP
ON
VIO
OFF
OFF
SLEEP
ON
VDD1
OFF
OFF
SLEEP
ON
VDD2
OFF
OFF
SLEEP
ON
VUSB1V5
OFF
OFF
OFF
OFF
VUSB1V8
OFF
OFF
OFF
OFF
VUSB3V1
OFF
OFF
SLEEP
ON
Power Timing
Sequence start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 16.
Sequence start timing depends on the TPS65921 starting event. If the starting event is:
• Main battery insertion, event time is 1.126 ms (time to set up internal LDO and relax internal reset)
• VBUS insertion, event time is 25 cycles of 32k
Starting_Event is main battery insertion
Vbat
1.126 ms
Sequence_Start
Starting_Event is VBUS insertion
Vbus
782 ms = 25 cycle32k
Sequence_Start
Starting_Event is PWRON button
PWRON
Pushbutton debouncing - 30 ms
Sequence_Start
Starting_Event is PWRON rising when device is in slave mode
PWRON
0 ms
Sequence_Start
SWCS048-018
Figure 16. Timings Before Sequence Start
Switch On In MASTER_C021_GENERIC Mode
Figure 17 describes the timing and control that must occur in Master_C021_Generic mode. Sequence_Start is a
symbolic internal signal to ease the description of the power sequences and occurs according to the different
events detailed in Figure 16.
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Sequence_Start
4608 ms battery detection
REGEN
1068 ms - 3 MHz oscillator setting + clock switch
VIO
1.8 V
1179 ms for VIO stabilization
VPLL1
1.8 V
1022 ms for LDO stabilization and start DC-DC ramping
VDD2
1.2 V
1099 ms for VDD2 stabilization and VDD1 start ramping
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
1179 ms for VIO stabilization
CLKEN
29.053 ms
32.410 ms
HFCLKOUT
T1
NRESPWRON
SWCS048-019
Figure 17. Timings—Switch On in Master_C021_Generic Mode
PARAMETER
T1
MIN
MAX
UNIT
10
11
32k clock cycles
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Switch On In SLAVE_C021_GENERIC Mode
Figure 18 describes the timing and control that must occur in Slave_C021_Generic mode. Sequence_Start is a
symbolic internal signal to ease the description of the power sequences and occurs according to the different
events detailed in Figure 16.
PWRON
4791 ms – 3 MHz oscillator setting + internal reg
REGEN
1068 ms for external supply ramp
VIO
1.8 V
1179 ms for VIO DC-DC stablilization
VPLL1
1.8 V
1022 ms
VDD2
1.2 V
1099 ms for VDD2 stabilization
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
CLKEN
1099 ms for VDD2 stabilization
29.053 ms
1953 ms for digital clock setting
HFCLKOUT
T1
NRESPWRON
SWCS048-020
Figure 18. Timings—Switch On in Slave_C021_Generic Model
PARAMETER
T1
MIN
MAX
UNIT
10
11
32k clock cycles
Switch-Off Sequence
This section describes the signal behavior required to switch off the system.
Switch-Off Sequence In Master Modes
Figure 19 describes the timing and control that occur during the switch-off sequence in master modes.
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VBAT
DEVOFF (register)
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
126 ms
CLKEN
3.42 ms before detection of starting event
NEXT_Startup_event
SWCS048-021
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power domains, state machinery priority, etc.).
Figure 19. Switch-Off Sequence in Master Modes
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set accordingly
inside
the
CFG_BOOT
register),
then
the
delay
between
DEVOFF
and
NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to the
internal frequency used by POWER STM switching from 3 MHz to 1.5 MHz in case the value of the HF clock is
19.2 MHz.
The DEVOFF event is the PWRON falling edge in slave mode and the DEVOFF internal register write in master
mode.
Switch-Off Sequence in Slave Mode
Figure 20 describes the timing and control that occur during the switch off-sequence in slave mode.
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VBAT
PWRON
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
3.42 ms before detection of starting event
NEXT_Startup_event
6 ms (see comment in notes
about reducing this interval)
VIO
6 ms
32KXIN
SWCS048-022
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power
domains,
state
machinery
priority,
etc.).
If necessary, the 6-ms period to maintain VIO and 32KXIN after PWRON goes low can be reduced to 150 μs.
Figure 20. Switch-Off Sequence in Slave Mode
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set accordingly
inside the CFG_BOOT register), then the delay between DEVOFF and NRESPWRON/CLK32KOUT/
SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to the internal frequency used by
POWER STM switching from 3 MHz into 1.5 MHz in case the value of the HF clock is 19.2 MHz.
Charge Pump
The charge pump generates a 5.0-V (nominal) power supply voltage from battery to the VBUS CP.OUT/VUSB.IN
pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump operating frequency is 1
MHz.
The charge pump tolerates 6 V on VBUS when it is in power down mode. The charge pump integrates a shortcircuit current limitation at 450 mA.
Figure 21 shows the charge pump.
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Switched 3.3 V
USB connector
VBAT.USB
CP.IN
CP.GND
VBUS
CPOUT
Normal operation
USB @ VBUS > 4.4 V
5.0-V CP
Power-up
USB @ VBAT > 3.20 V
USBIN
USB3P3
TPS65921
DP
DM
USB PHY
ID
SWCS048-023
Figure 21. General Overview of the Charge Pump and Its Interfaces
It can be used to supply USB 3.1 V LDO when battery voltage is lower than this LDO VBATmin voltage (see
electrical characteristics).
USB Transceiver
The TPS65921 device includes a USB OTG transceiver that support USB 480 Mbps HS, 12 Mbps FS, and USB
1.5 Mbps LS through a 4-pin UTMI+ ULPI.
It also includes a module covering Battery Charging Specification v1.0. Figure 22 shows the USB 2.0 PHY
highlight block diagram.
USB OTG device
OMAP
(LINK)
Device
USB PHY
ULPI
Phone connector
(USB)
PC
ADC inputs
(optional)
Charger
SWCS048-024
Figure 22. USB 2.0 PHY Highlight
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Figure 23 shows the USB system application schematic.
VBAT
CVBUS.IN
CVBUS.PC
CUSB.1P3
VUSB.3P1
CUSB3P1
VUSB.1P5
VUSB.1P8
CP.CAPN
CP.CAPP
CP.IN
CP.GND
CUSB.1P5
VBAT
VBAT.USB
CVBAT.USB
CVBUS
VBUS
ULPI_CLK
TPS65921
D+ / RXD
ULPI_STP
USB
PLL
ULPI_DIR
USB
CP
USB
PWR
ULPI_NXT
D– / TXD
ID
USB OTG
connector
OMAP
host
processor
(LINK)
ULP interface
GND
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI
USB 2.0 HS-OTG
transceiver (PHY)
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
Registers
OTG
ULPI_DATA6
Serial interface
ULPI_DATA7
TXEN
DAT
SE0
SWCS048-025
Figure 23. USB System Application Schematic
PHY
The PHY is the physical signaling layer of the USB 2.0. It contains all the drivers and receivers required for
physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard digital interface called the universal transceiver
macro cell interface (UTMI).
The transmitters and receivers inside the PHY are classified into two main classes:
• The FS and LS transceivers. These are the legacy USB1.x transceivers.
• The HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry consisting of:
• A DPLL, which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB, and
also the clock required for the switched capacitor resistance block.
• A switched capacitor resistance block used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry that protects it from an accidental 5 V short on the DP and DM
lines.
LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data lines
D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the FS/LS modes of
operation.
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LS/FS Differential Receiver
A differential input receiver (RX) retrieves the LS/FS differential data signaling. The differential voltage on the line
is converted into digital data by a differential comparator on DP/DM. This data is then sent to a clock and data
recovery circuit, which recovers the clock from the data. In an additional serial mode, the differential data is
directly output on the RXRCV pin.
LS/FS Transmitter
The USB transceiver (TX) uses a differential output driver to drive the USB data signal D+/– onto the USB cable.
The outputs of the driver support 3-state operation to achieve bidirectional half-duplex transactions.
HS Differential Receiver
The HS receiver consists of the following blocks:
• A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and serial-toparallel converter to generate the UTMI DATAOUT
HS Differential Transmitter
The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is
serialized, bit-stuffed, NRZI-encoded, and transmitted as a DC output current on DP or DM depending on the
data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes the
impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the DP and DM
lines.
UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct
access to the FS/LS analog transmitter and receiver.
ULPI
Device
USB connector
DATA0: UART_TX
DP/RXD/MIC
DATA1: UART_RX
DM/TXD/SPKR
SWCS048-026
Figure 24. USB UART Data Flow
The OTG block integrates three main functions:
• The USB plug detection function on VBUS and ID
• The ID resistor detection
• The VBUS level detection
CHARGER DETECTION
To support Battery Charging Specification v1.1 [BCS v1.1], a charger detection module is included in the
TPS65921 USB module.
The detection mechanism aims distinguishing several types of power sources that can be connected on VBUS
line:
• Dedicated charger port
• Standard host port
• Charging host port
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The hardware includes:
• A dedicated voltage referenced pullup on DP line
• A dedicated current controlled pulldown on DM line
• A detection comparator on DM line
• A control/detection state-machine including timers
Additional circuitry is added on DP/DM respectively for data line symmetry (required for HS operation) and for
possible future extension
ID pin status detection (as defined per OTG v1.3 standard) and DP/DM single-ended receivers (as defined per
USB v2.0 standard) are also used to determine the type of device plugged on the USB connector.
For details on the detection mechanism, refer to [BCS v1.1] (1).
The charging detection feature has two modes (description of each mode follows):
1. Software CTL mode: Software has direct control of current source and USB charger detection comparator on
DP/DM (enabled when USB_SW_CTRL_EN=1) using USB_CHRG_CTRL registers bits.
2. Software FSM mode: Software can start and stop USB charger detection state-machine.
For both modes, DPPULLDOWN and DMPULLDOWN bits in OTG_CTRL register are 1 by default. This can
cause errors in charger detection. Therefore, both bits must be cleared to 0 before software begins charger
detection sequence.
1- Software CTL Mode (Manual detection):
When in this mode the charger detection circuitry is fully under control of software. Refer to POWER_CONTROL
register
bits
as
to
how
to
control
the
detection
circuitry.
Conditions:
• The TPS65921 device is powered and is in active mode.
• USB_SW_CHRG_CTRL_EN = 1, register bit set by the software
• USB_CHG_DET_EN_SW = 1, register bit set by the software
Control the USB_SW_CHRF_CTRL register to achieve charger detection.
2- Software FSM Mode (Automatic detection):
The TPS65921 also supports automated battery charger detection through the USB battery charger detection
FSM in Figure 25 while the chip is in active mode. This mode is set by software using the SW_USB_DET bit.
When in this mode, the automated charger detection finite state-machine (FSM) is enabled. Refer to the statemachine
diagram
for
details.
Conditions:
• The TPS65921 device is powered and is in active mode.
• USB_HW_CHRG_DET_EN = 1
See the Register Map for more details.
The TPS65921 device also supports automated data contact detection in the FSM through the
DATA_CONTACT_DET_EN bit which should be set at the same time as SW_USB_DET above, before setting
SW_CONTROL bit. This enables a block of the FSM, which performs data contact detect for a maximum of
DCD_TIMEOUT before automatically skipping to charger detection.
See Figure 25,USB Battery Charger FSM, for details of how context is stored if SW_CONTROL bit is set while in
software FSM mode.
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USB_DET_ON
INIT
CHGD_INIT
DATA_CONTACT_DET_EN=0
CHGDCTRL=”000_0000"
CHGDCTRL=”011_0110"
DATA_CONTACT_DET_EN=1
CHGD_SETUP
DCD_INIT
Wait TVDP_SCR_ON
CHGDCTRL=”011_1010"
Dcounter=DCD_TIMEOUT
Or
CHGD_SERX_DP_DEB=0
DCD_SETUP
End wait
CHGD CHECK
_
Dcounter=0
Wait TIDP_SRC_ON
Always ON
End wait
CHGD_SERX_DM_DEB=0
and
CHGD_VDM_DEB=1
DCD_CHECK
Dcounter=Dcounter+1
USB500_WAIT
CHGDCTRL=010_0000
Wait TVDP_SRC_HICRNT
End wait
Dcounter<DCD_TIMEOUT
USB500_DETECTED
CHGDCTRL=100_0000
USP_P=0
USP_P=1
and
(USB_HW_CHRG_DET_EN=1 or
USB_SW_CHRG_DET_EN=1)
(USB_HW_CHRG_DET_EN=0 and
USB_SW_CHRG_DET_EN=0)
USB_P=0
or
(USB_HW_CHRG_DET_EN=0 and
USB_SW_CHRG_DET_EN=0)
USB_DET_STS
USB_DET_OFF
CHGDCTRL=xxx_0000
USB charger status is memorized
CHGDCTRL=000_0000
SWCS048-027
Figure 25. USB Battery Charger Detection FSM
USB charger detection status bit definition:
• USBVBUS_PRES: Detect presence of valid VBUS. Comparator output is debounced for DEBVBUS_TIME
(minimum 10 ms) on CKCHG and generates a USB_P signal. USB_P is computed only if a battery presence
is detected.
• USBCHRG_PRES: Detect presence of USB charger on DP/DM. The feature is enabled through the
USB_DET_EN signal, then USBPHY performs checks on DP/DM and return status USB_DET_RESULT:
– 1 : USB 500-mA charger is detected.
– 0 : USB 100-mA charger is detected.
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USB_DET_STATUS: 500-mA/100-mA USB charger detect presence comparator output is debounced during
DEBUSBCHG_TIME (minimum 20 ms) on CKCHG, debounced signal is USB_DET_RESULT (set to 1 in
case of 500-mA charger)
Two signals are the result of the charger detection state machine:
– USB100_P: Valid 100-mA charger (VBUS supplier) is detected.
– USB500_P: Valid 500-mA charger (USB charger) is detected.
USB Battery Charger FSM
The FSM uses the control signals CHGDCTRL[6:0] described below to control and observe battery charger
detection.
When the SW_CONTROL bit is set to 1, the current context of the FSM and the state of charger detection is
latched in POWER_CONTROL register bits HWDETECT, DP_VSRC_EN, VDAT_DET, and DET_COMP, after
which FSM control signals CHGDCTRL[6:0] are ignored, and charger detection hardware and the CHGR_DET
pin are controlled by the software.
The CHGD_IDP_SRC_EN bit is not latched when the SW_CONTROL bit is set (for example, if the FSM is
performing data-contact detection at the time the SW_CONTROL is set to 1, the CHGD_IDP_SRC_EN bit is
unchanged — its default value is 0).
FSM Control Signals
Table 14. USB Charger Detect FSM I/O Control Signals
CONTROL SIGNAL
CONTROL SIGNAL
DESCRIPTION
TYPE
Bit(6)
USB500_P
500-mA USB charging can be enabled
Bit(5)
USB100_P
100-mA USB charging can be enabled
Input
Bit(4)
CHGD_DET_EN
Enable charger detection (used to enable
CHGD IBIAS block)
Output
Bit(3)
CHGD_IDP_SRC_EN
Enable IDP_SRC and RDM_DWN
Output
Bit(2)
CHGD_VDP_SRC_EN
Enable VDP_SRC buffer, IDM_SINK, and
VDAT_REF_DM comp
Output
Bit(1)
CHGD_SERX_EN
Enable SERX comparators on DP and DM
Output
Bit(0)
Reserved
Reserved
Output
Input
Table 14 shows control signals used to control the charger detection analog block from the FSM. The bit number
in the left-handed column indicates control bit position used in the charger detection state-machine. Both SERX
comparator outputs (CHGD_SERX_DP, CHGD_SERX_DM) are available for register read in the
VENDOR_SPECIFIC3 register.
Example:
State:
Control:
Bit(6):
Bit(5):
Bit(4):
Bit(3):
Bit(2):
Bit(1):
Bit(0): Reserved = 0
CHGDCTRL[6:0]
USB500_P
USB100_P
CHGD_DET_EN
CHGD_IDP_SRC_EN
CHGD_VDP_SRC_EN
CHGD_SERX_EN
=
=
=
=
=
=
=
DCD_INIT
011_1010
0
1
1
1
0
1
MADC
The Monitoring Analog-to-Digital Convertor (MADC) enables the host processors to monitor analog signals using
Analog-to-Digital Conversion (ADC). After the conversion is complete, the host processor reads the results of the
conversion through the inter-integrated circuit (I2C) interface.
The MADC has the following features:
• 10-bit ADC
• External input (ADCIN0)
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•
•
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Internal inputs (VBUS and battery voltage)
MADC resource shared among multiple users, including system host processors and the internal USB
Four ways of starting analog-to-digital (ADC) conversion
Quarter-bit accuracy if the averaging function is used for modem-initiated real-time (RT) conversion requests
Management of potential concurrent conversion requests and priority between different resource users
Interrupt signal to the primary interrupt handler (PIH) module at the end-of-sequence of conversions
Averaging feature to sample the input channel on four consecutive conversion cycles instead of once, and to
provide the average value of four conversions
Because the MADC is shared by users, there are four ways to start the ADC conversion. Three of these requests
can be triggered by external host processors, and one request is issued by USB:
• Hardware or RT conversion request: This request is initiated by the external host processor to request RT
signal conversion. This conversion request is most useful when tied to a modem processor request for battery
voltage level, in synchronization with a signal frame boundary. The host processor can request conversion on
all ADC input channels using this conversion request.
• SW1 software conversion request: This request can be initiated by the first external host processor to request
non-RT conversions. This request is also called an asynchronous or GP conversion (GPC) request.
• SW2 software conversion request: This request can be initiated by the second external host processor to
request non-RT conversions. This request is also called an asynchronous or GPC request.
• USB conversion request: This is a GPC request triggered by the USB through TPS65921 internal signals.
This conversion request is for the ADCIN12 channel.
It is possible to delay the conversion by programming the acquisition time (ACQUISITION register).
JTAG INTERFACES
The TPS65921 JTAG TAP controller handles standard IEEE JTAG interfaces. This section describes the timing
requirements for the tools used to test the TPS65921 power management.
The JTAG/TAP module provides a JTAG interface according to IEEE Std1149.1a. This interface uses the four
I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device, which makes their
state high when they are not driven. The output TDO is a 3-state output, which is high impedance except when
data are shifted between TDI and TDO.
• TCK is the test clock signal.
• TMS is the test mode select signal.
• TDI is the scan path input.
• TDO is the scan path output.
TMS and TDO are multiplexed at the top level with the CPIO0 and CPIO1 pins. The dedicated external TEST pin
switches from functional mode (GPIO0/GPIO1) to JTAG mode (TMS/TDO). The JTAG operations are controlled
by a state-machine that follows the IEEE Std1149.1a state diagram. This state-machine is reset by the
TPS65921 internal power-on reset. A test mode is selected by writing a 6-bit word (instruction) into the instruction
register and then accessing the related data register.
Keyboard
The keyboard is connected to the chip using:
• KBR (7:0) input pins for row lines
• KBC (7:0) output pins for column lines
Figure 26 shows the keyboard connection.
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VCC
Internal
pullup
Keyboard controller
8x8
Keyboard matrix
kbd_r_0
kbd_r_1
kbd_r_2
kbd_r_3
kbd_r_4
kbd_r_5
kbd_r_6
kbd_r_7
kbd_c_0
kbd_c_1
kbd_c_2
kbd_c_3
kbd_c_4
kbd_c_5
kbd_c_6
kbd_c_7
SWCS048-028
Figure 26. Keyboard Connection
When a key button of the keyboard matrix is pressed, the corresponding row and column lines are shorted
together. To allow key press detection, all input pins (KBR) are pulled up to VCC and all output pins (KBC) driven
to a low level.
Any action on a button generates an interrupt to the sequencer.
The decoding sequence is written to allow detection of simultaneous press actions on several key buttons.
The keyboard interface can be used with a smaller keyboard area than 8 × 8. To use a 6 × 6 keyboard, KBR(6)
and KBR(7) must be tied high to prevent any scanning process distribution.
52
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Product Folder Link(s): TPS65921
TPS65921
www.ti.com
SWCS048F – MARCH 2010 – REVISED MARCH 2012
PACKAGING INFORMATION
Table 15. TPS65921 Nomenclature Description
FIELDS
MEANING
P
Marking used to note prototype (X), preproduction (P), or qualified/production device
(Blank) (1)
A
Mask set version descriptor (initial silicon = BLANK, first silicon revision = A, second silicon
revision = B,...) (2)
YM
Year month
LLLLS
Lot code
$
Fab planning code
(1)
(2)
Blank in the symbol or part number are collapsed so there are no gaps between characters.
Initial silicon version is ES1.0; first revision can be named ES2.0, ES1.1, or ES1.01 depending on the level of change.
NOTE: Device name maximum is 10 characters.
Thermal Characteristics
Table 16. TPS65921 Thermal Resistance Characteristics
Package
TPS65921ZQZ
(1)
θJA(°C/W)
θJB(°C/W)
θJC(top)(°C/W)
Board Type
46
17
20
2S2P (1)
The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package
Thermal Measurements).
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Product Folder Link(s): TPS65921
53
TPS65921
SWCS048F – MARCH 2010 – REVISED MARCH 2012
www.ti.com
Revision History
Table 17. REVISION HISTORY
(1)
54
Version
Literature Number
Date
F
SWCS048
March 2012
Notes
See
(1)
.
TPS65921 Data Manual, SWCS048F - Table 13: Swapped REFGND and AGND descriptions.
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Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65921
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS65921B1ZQZ
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQZ
120
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65921B1ZQZR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQZ
120
2000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65921BZQZ
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQZ
120
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
TPS65921BZQZR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQZ
120
2000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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