Product Specification PE43703 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-6.0 GHz, VssEXT option Product Description The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0 dB steps. The customer can choose which step size and associated specifications are best suited for their application. The Peregrine 50Ω RF DSA provides multiple CMOS control interfaces and an optional external Vss feature. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with Vdd due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. Features • HaRP™-enhanced UltraCMOS™ device • Attenuation options: 0.25 dB, 0.5 dB, or 1.0 dB steps to 31.75 dB • 0.25 dB monotonicity for ≤ 4.0 GHz • 0.5 dB monotonicity for ≤ 5.0 GHz • 1 dB monotonicity for ≤ 6.0 GHz • High Linearity: Typical +59 dBm IIP3 • Excellent low-frequency performance • Optional External Vss Control (VssEXT) • 3.3 V or 5.0 V Power Supply Voltage The PE43703 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. • Fast switch settling time • Programming Modes: • Direct Parallel Latched Parallel • Serial-Addressable: Program up to eight addresses 000 - 111 • High-attenuation state @ power-up (PUP) • Figure 1. Package Type 32-lead 5x5x0.85 mm QFN Package • CMOS Compatible • No DC blocking capacitors required Figure 2. Functional Schematic Diagram Switched Attenuator Array RF Output RF Input Parallel Control 7 Serial In Control Logic Interface CLK LE A0 A1 Document No. 70-0245-04 │ www.psemi.com A2 P/S (optional) VssEXT ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 15 PE43703 Product Specification Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Test Conditions Frequency Min Frequency Range Typical Max Units DC – 4 Attenuation Range 0.25 dB Step DC ≤ 4 GHz Insertion Loss 0 dB - 7.75 dB Attenuation settings 8 dB - 31.75 dB Attenuation settings 0 dB - 31.75 dB Attenuation settings Attenuation Error GHz 0 – 31.75 DC < 3 GHz DC < 3 GHz 3 GHz ≤ 4 GHz Return Loss DC - 4 GHz Relative Phase All States DC - 4 GHz P1dB Input 20 MHz - 4 GHz IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz Typical Spurious Value1 VssEXT grounded 1MHz dB 1.9 2.4 dB ±(0.2+1.5%) ±(0.15+4%) ±(0.25+4.5%) dB dB dB 18 30 Video Feed Through dB 44 deg 32 dBm 59 dBm -110 dBm 10 mVpp Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns Settling Time RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. 4 25 µs Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 0.25 dB state Figure 4. 0.25dB Attenuation vs. Attenuation State Figure 3. 0.25 dB Step Error vs. Frequency* 200 MHz 2200 MHz 900 MHz 3000 MHz 0.25-dB PE43701 Attenuation 1800 MHz 35 0.500 900 MHz 1800 MHz 2200 MHz 3000 MHz 30 Attenuation dB Attenuation dB Step Error (dB.) 0.400 0.300 0.200 0.100 25 20 15 10 5 0 0.000 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 0 Attenuation Setting (dB.) 5 10 2.00 0.25dB State 0.5 dB State 1dB State 2dB State 4dB State 8dB State 16dB State 31.75dB State 30 35 Figure 6. 0.25 dB Attenuation Error vs. Frequency 1.500 1.50 200 MHz 900 MHz 1800 MHz 2200 MHZ 3000 MHz 4000 MHz 1.000 1.00 Attenuation Error (dB.) Bit Error (dB.) 25 Attenuation State *Monotonicity is held so long as Step-Error does not cross zero Figure 5. 0.25 dB Major State Bit Error 15 20 Attenuation State 0.50 0.00 -0.50 -1.00 0.500 0.000 -0.500 -1.000 -1.50 -2.00 -1.500 0.0 1.0 2.0 Frequency (GHz) 3.0 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 15 4.0 0.0 4.0 8.0 12.0 16.0 20.0 Attenuation Setting (dB.) Document No. 70-0245-04 24.0 28.0 32.0 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Test Conditions Frequency Min Typical Frequency Range Attenuation Range 0.5 dB Step DC ≤ 5 GHz Insertion Loss 0 dB - 31.5 dB Attenuation settings 0 dB - 16.5 dB Attenuation settings 17 dB - 31.5 dB Attenuation settings Attenuation Error All States DC - 5 GHz P1dB Input 20 MHz - 5 GHz Two tones at +18 dBm, 20 MHz spacing 20 MHz - 5 GHz VssEXT grounded 1 MHz 1 Typical Spurious Value dB 2.6 dB ±(0.25+4.5%) ±(0.3+5%) ±(1.3+0%) dB dB dB 18 Relative Phase IIP3 0 – 31.5 2.0 DC - 5 GHz Units GHz DC < 4 GHz 4 ≤ 5 GHz 4 ≤ 5 GHz Return Loss Max DC – 5 30 Video Feed Through dB 56 deg 32 dBm 57 dBm -110 dBm 10 mVpp Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. 400 ns Settling Time 4 25 µs Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 0.5 dB state Figure 7. 0.5 dB Step-Error vs. Frequency* 200 MHz 3000 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz Figure 8. 0.5 dB Attenuation vs. Attenuation State 0.5-dB PE43703 Attenuation 2200 MHz 35 1.000 Attenuation dBdB Attenuation 30 Step Error (dB.) 0.750 0.500 0.250 900 MHz 2200 MHz 3800 MHz 5000 MHz 25 20 15 10 5 0.000 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 0 32.0 0 Attenuation Se tting (dB.) 5 10 *Monotonicity is held so long as Step-Error does not cross zero 1dB State 16dB State 25 30 35 Attenuation State Figure 10. 0.5 dB Attenuation Error vs. Frequency Figure 9. 0.5 dB Major State Bit Error 0.5dB State 8dB State 15 20 Attenuation State 2dB State 31.5dB State 4dB State 200 MHz 3000 MHz 2.00 900 MHz 4000 MHz 1800 MHz 5000 MHz 2200 MHz 1.500 1.50 1.000 Attenuation Error (dB.) Bit Error (dB.) 1.00 0.50 0.00 -0.50 -1.00 0.500 0.000 -0.500 -1.000 -1.50 -2.00 -1.500 0.0 1.0 2.0 3.0 Frequency (GHz) Document No. 70-0245-04 │ www.psemi.com 4.0 5.0 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Atte nuation Setting (dB.) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 15 PE43703 Product Specification Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Test Conditions Frequency range Attenuation Range Frequency Min Typical Max Units DC – 6 0 - 31 1 dB Step DC ≤ 6 GHz Insertion Loss GHz dB 2.3 2.8 dB ±(0.25+4.5%) +0.4+8% +1.4+0% -0.2-3% dB dB dB dB 0 dB - 31 dB Attenuation settings 0 dB - 12 dB Attenuation settings 13 dB - 31 dB Attenuation setting 0 dB - 31 dB Attenuation settings DC – 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz DC - 6 GHz 18 dB Relative Phase All States DC - 6 GHz 74 deg P1dB Input 20 MHz - 6 GHz 32 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 6 GHz 53 dBm Typical Spurious Value1 VssEXT grounded 1 MHz Attenuation Error Return Loss 30 -110 dBm 10 mVpp Video Feed Through Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns Settling Time RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. 4 25 µs Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 1 dB state Figure 11. 1 dB Step-Error vs. Frequency* 200 MHz 3000 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz Figure 12. 1 dB Attenuation vs Attenuation State 2200 MHz 6000 MHz 1-dB PE43703 Attenuation 2.000 35 1.750 30 Attenuation Attenuation dBdB Step Error (dB.) 1.500 1.250 1.000 0.750 0.500 900 MHz 2200 MHz 3800 MHz 5800 MHz 25 20 15 10 5 0.250 0 0.000 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 0 Attenuation Setting (dB.) 5 10 *Monotonicity is held so long as Step-Error does not cross zero 1dB State 8dB State 2dB State 16dB State 30 35 Figure 14. 1dB Attenuation Error vs. Frequency 4dB State 31dB State 200 MHz 900 MHz 1800 MHz 2200 MHz 1.500 1.50 1.000 Attenuation Error (dB.) 1.00 Bit Error (dB.) 25 Attenuation State Figure 13. 1 dB Major State Bit Error 2.00 15 20 Attenuation State 0.50 0.00 -0.50 -1.00 0.500 0.000 -0.500 -1.000 -1.50 -2.00 -1.500 0.0 1.0 2.0 3.0 4.0 5.0 Frequency (GHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 15 6.0 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Performance Plots, 1 dB state (continued) Figure 15. 1 dB Attenuation Error vs. Frequency 3000 MHz 4000 MHz 5000 MHz Figure 16. Insertion Loss vs. Temperature -40C 6000 MHz +25C +85C 0 1.500 -0.5 -1 -1.5 Insertion Loss (dBm.) Attenuation Error (dB.) 1.000 0.500 0.000 -0.500 -2 -2.5 -3 -3.5 -4 -1.000 -4.5 -1.500 -5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 0.0 1.0 2.0 3.0 Atte nuation Setting (dB.) Figure 17. Input Return Loss vs. Attenuation T = +25C 0 0dB 0.25dB 0.5dB 1dB 4dB 8dB 16dB 31.75dB 2dB 0dB 4dB 0 7.0 8.0 9.0 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB -10 -20 Return Loss (dB.) Return Loss (dB.) 6.0 Figure 18. Output Return Loss vs. Attenuation T = +25C -10 -30 -40 -50 -20 -30 -40 -50 -60 -70 -60 0 1 2 3 4 5 6 Frequency (GHz.) 7 8 9 Figure 19. Input Return Loss vs. Temperature 16dB State -40C 25C 0 1 2 3 4 5 Frequency (GHz.) 6 7 8 9 Figure 20. Output Return Loss vs. Temperature 16dB State 85C 0 -40C 0 25C 85C -5 -5 -10 -10 Return Loss (dB.) Return Loss (dB.) 4.0 5.0 Frequency (GHz) -15 -20 -25 -30 -15 -20 -25 -30 -35 -40 -35 -45 -40 -50 0 1 2 3 4 5 6 Frequency (GHz.) Document No. 70-0245-04 │ www.psemi.com 7 8 9 0 1 2 3 4 5 6 Frequency (GHz.) 7 8 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 15 9 PE43703 Product Specification Performance Plots (continued) Figure 21. Relative Phase vs. Frequency 0.25dB 0.5dB 1dB 4dB 8dB 16dB 31.75dB Figure 22. Relative Phase vs. Temperature 31.75dB State 2dB 900 MHz 35.00 80 60 40 20 3000 MHz 25.00 20.00 15.00 10.00 5.00 0.00 0 0 1 2 3 4 5 6 7 -40 8 -20 0 Figure 23. Attenuation Error vs. Attenuation Setting @ 900 MHz 900 MHz @ T=+25 C 900 MHz @ T= -40C 20 40 60 80 Temperature (Deg. C.) Frequency (GHz.) Figure 24. Attenuation Error vs. Attenuation Setting @ 1800 MHz 1800 MHz @ T= +25C 900 MHz @ T= +85C 0.500 0.500 0.300 0.300 Attenuation Error (dB.) Attenuation Error (dB.) 1800 MHz 30.00 100 Phase (deg.) Relative Phase Error (Deg.) 120 0dB 0.100 -0.100 -0.300 1800 MHz @ T= -40C 1800 MHz @ T= +85C 0.100 -0.100 -0.300 -0.500 -0.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 0.0 4.0 8.0 Attenuation Setting (dB.) Figure 25. Attenuation Error vs. Attenuation Setting @ 3000 MHz 3000 MHz @ T= +25C 3000 MHz @ T= -40C 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) Figure 26. Input IP3 vs. Frequency 3000 MHz @ T= +85C 0.500 0dB 0.25dB 0.5dB 1dB 4dB 8dB 16dB 31.75dB 2dB 70 65 Input IP3 (dBm.) Attenuation Error (dB.) 0.300 0.100 -0.100 60 55 50 45 40 -0.300 35 30 -0.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 15 0 1000 2000 3000 4000 5000 6000 7000 Frequency (MHz.) Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification C0.5 C1 C2 C4 C8 C16 32 31 30 29 28 27 26 SI C0.25 Figure 27. Pin Configuration (Top View) 25 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. NC 1 24 CLK VDD 2 23 LE P/S 3 22 A1 Latch-Up Avoidance A0 4 21 A2 GND 5 20 VssEXT Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. GND 6 19 GND RF1 7 18 RF2 GND 8 17 GND 11 12 13 14 15 GND GND GND GND 16 GND 10 GND GND 9 GND Exposed Solder pad Table 4. Pin Descriptions Optional External Vss Control (VssEXT) For proper operation, the VssEXT control must be grounded or at the Vss voltage specified in the Operating Ranges table. When the VssEXT control pin on the package is grounded the switch FET’s are biased with an internal low spur negative voltage generator. For applications that require the lowest possible spur performance, VssEXT can be applied to bypass the internal negative voltage generator to eliminate the spurs. Pin No. Pin Name 1 N/C No Connect Description Switching Frequency 2 VDD Power supply pin 3 P/S Serial/Parallel mode select 4 A0 Address Bit A0 (LSB) 5 GND Ground The PE43703 has a maximum 25 kHz switching rate when VssEXT is grounded. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. 6 GND Ground Moisture Sensitivity Level 7 RF1 RF1 port 8 - 17 GND Ground The Moisture Sensitivity Level rating for the PE43703 in the 5x5 QFN package is MSL1. 18 RF2 RF2 port 19 GND Ground Exposed Solder Pad Connection 20 VssEXT External Vss Control 21 A2 Address Bit A2 The exposed solder pad on the bottom of the package must be grounded for proper device operation. 22 A1 Address Bit A1 23 LE Latch Enable input 24 CLK Serial interface clock input 25 SI 26 C16 Serial Interface input Attenuation control bit, 16 dB 27 C8 Attenuation control bit, 8 dB 28 C4 Attenuation control bit, 4 dB 29 C2 Attenuation control bit, 2 dB 30 C1 Attenuation control bit, 1 dB 31 C0.5 Attenuation control bit, 0.5 dB 32 C0.25 Attenuation control bit, 0.25 dB Paddle GND Ground for proper operation Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 15 PE43703 Product Specification Table 5. Operating Ranges Parameter VDD Power Supply Voltage Min Typ 3.0 3.3 VDD Power Supply Voltage VssEXT Negative Power Supply Voltage1 -3.0 IDD Power Supply Current Digital Input High Table 6. Absolute Maximum Ratings Max VDD Parameter/Conditions Min Max Units Power supply voltage -0.3 6.0 V Vss External Negative Power Supply Voltage (optional) -4.0 0.3 V VI Voltage on any Digital input -0.3 5.8 V V PIN Input power (50Ω) 1 Hz ≤ 20 MHz 20 MHz ≤ 6 GHz See fig. 28 +23 dBm dBm See fig. 28 +23 dBm dBm TST Storage temperature range 150 °C 85 °C VESD ESD voltage (HBM)1 ESD voltage (Machine Model) 500 100 V V 5.5 V -2.7 -2.4 V 70 350 µA 5.5 PIN Input power (50Ω): 1 Hz ≤ 20 MHz 20 MHz ≤ 6 GHz -40 Symbol V 5.0 2.6 TOP Operating temperature range Digital Input Low Units 25 0 Digital Input Leakage 1 V 15 µA VssEXT -65 Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Note: 1. Applied only when external VSS power supply used. Pin 20 must be grounded when using internal Vss supply Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Figure 28. Maximum Power Handling Capability: Z0 = 50 Ω 30.0 25.0 Pin dBm 20.0 15.0 10.0 5.0 0.0 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 Hz ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 15 Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Table 7. Control Voltage State Table 10. Serial Address Word Truth Table Bias Condition Address Word Low 0 to +1.0 Vdc at 2 µA (typ) A7 (MSB) High +2.6 to +5 Vdc at 10 µA (typ) X X X X X L X X X X X L Table 8. Latch and Clock Specifications A6 A5 A4 A3 A2 A0 Address Setting L L 000 L H 001 A1 X X X X X L H L 010 X X X X X L H H 011 L L 100 Latch Enable Shift Clock Function X X X X X H 0 ↑ Shift Register Clocked X X X X X H L H 101 Contents of shift register transferred to attenuator core X X X X X H H L 110 X X X X X H H H 111 ↑ X Table 9. Parallel Truth Table Table 11. Serial Attenuation Word Truth Table Parallel Control Setting Attenuation Word D1 D0 (LSB) Attenuation Setting RF1-RF2 D6 D5 D4 D3 D2 D1 D0 Attenuation Setting RF1-RF2 L L L L L L L Reference I.L. X L L L L L L L Reference I.L. L L L L L L H 0.25 dB X L L L L L L H 0.25 dB L L L L L H L 0.5 dB X L L L L L H L 0.5 dB L L L L H L L 1 dB X L L L L H L L 1 dB L L L H L L L 2 dB X L L L H L L L 2 dB L L H L L L L 4 dB D7 D6 D5 D4 D3 D2 L L H L L L L 4 dB X L H L L L L L 8 dB X L H L L L L L 8 dB H L L L L L L 16 dB X H L L L L L L 16 dB H H H H H H H 31.75 dB X H H H H H H H 31.75 dB Table 12. Serial-Addressable Register Map Bits can either be set to logic high or logic low MSB (last in) LSB (first in) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Address Word Attenuation Word Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state at address 3: Address word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → X1001001 Serial Input: XXXXX011X1001001 Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 15 PE43703 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43703. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the attenuation word. Parallel Mode Interface The parallel interface consists of seven CMOScompatible control lines that select the desired attenuation state, as shown in Table 9. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 10 & Table 11, respectively. A programming example of the serial-addressable register is illustrated in Table 12. The serial-addressable timing diagram is illustrated in Fig. 29. The parallel interface timing requirements are defined by Fig. 30 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 30) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial-addressable interface is a 16-bit serialin, parallel-out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 29 illustrates a example timing diagram for programming a state. It is recommended that all parallel control inputs be grounded when the DSA is used in Serial Mode. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 15 Power-up Control Settings The PE43703 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the parallel control pins prior to powerup. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Figure 29. Serial-Addressable Timing Diagram Bits can either be set to logic high or logic low DI[6:0] TDISU ADD[2:0] TDIH VALID TASU TAH P/S TPSSU TPSH D[0] SI TSISU D[1] D[2] D[3] D[4] D[5] D[6] A[0] A[1] A[2] TSIH CLK TCLKL TCLKH TLESU LE TLEPW DO[6:0] TPD VALID Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram P/S TPSSU DI[6:0] TPSH VALID TDISU TDIH LE TLEPW DO[6:0] VALID TDIPD TPD Table 13. Serial Interface AC Characteristics VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Min Max Unit FCLK Serial clock frequency - 10 MHz TCLKH Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - ns TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 - ns TLEPW Latch Enable min. pulse width 30 - ns TSISU Serial data setup time 10 - ns TSIH Serial data hold time 10 - Symbol Parameter Min Max Unit Latch Enable minimum pulse width 30 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns ns TPSIH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Digital register delay (internal, direct mode only) - 5 ns Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TASU Address setup time 100 - ns Address hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Note: VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified TLEPW TDISU TAH Table 14. Parallel and Direct Interface AC Characteristics TDIPD fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 15 PE43703 Product Specification Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE43703 Digital Step Attenuator. Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J1 & Serial header pin and set the D0-D6 SP3T switches to the ‘MIDDLE’ toggle position. Position the Parallel/ Serial (P/S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or SerialAddressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J1 and Serial header pins. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to VDD. Switches D0-D6 are SP3T switches which enable the user to manually program the parallel bits. When any input D0-D6 is toggled ‘UP’, logic high is presented to the parallel input. When toggled ‘DOWN’, logic low is presented to the parallel input. Setting D0-D6 to the ‘MIDDLE’ toggle position presents an OPEN, which forces an on-chip logic low. Table 9 depicts the parallel programming truth table and Fig. 30 illustrates the parallel programming timing diagram. Figure 31. Evaluation Board Layout Peregrine Specification 101-0312 Note: Reference Fig. 32 for Evaluation Board Schematic Serial-Addressable Programming Procedure Position the Parallel/Serial (P/S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A0-A2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then 000 become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that Latched-Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from 0V to VDD and back to 0V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 15 Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Figure 32. Evaluation Board Schematic Peregrine Specification 102-0381 Note: Capacitors C1-C8, C13, & C14 may be omitted. Figure 33. Package Drawing QFN 5x5 mm A MAX 0.900 NOM 0.850 MIN 0.800 Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 15 PE43703 Product Specification Figure 34. Tape and Reel Drawing Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Figure 35. Marking Specifications 43703 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 15. Ordering Information Order Code Part Marking Description Package Shipping Method PE43703MLI 43703 PE43703 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel PE43703MLI-Z 43703 PE43703 G – 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R EK43703-01 43703 PE43703 G – 32QFN 5x5mm-EK Evaluation Kit 1 / Box ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 15 Document No. 70-0245-04 │ UltraCMOS™ RFIC Solutions PE43703 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 High-Reliability and Defense Products Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0245-04 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 15