PEREGRINE PE43503

Product Specification
PE43503
50 Ω RF Digital Attenuator
5-bit, 31 dB, DC-6.0 GHz
Product Description
The PE43503 is a HaRP™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA) covering a 31 dB attenuation
range in 1 dB steps. The Peregrine 50Ω RF DSA provides a
serial CMOS control interface. It maintains high attenuation
accuracy over frequency and temperature and exhibits very low
insertion loss and low power consumption. Performance does
not change with Vdd due to on-board regulator. This next
generation Peregrine DSA is available in a 4x4 mm 24-lead
QFN footprint.
Features
• HaRP™-enhanced UltraCMOS™ device
The PE43503 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• Programming Modes:
• Attenuation: 1 dB steps to 31 dB
• High Linearity: Typical +58 dBm IP3
•
Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
•
•
Direct Parallel
Latched Parallel
•
Serial
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
Figure 1. Package Type
• No DC blocking capacitors required
24-lead 4x4x0.85 mm QFN Package
• Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Output
RF Input
Parallel Control
5
Serial In
Control Logic Interface
CLK
LE
A0
A1
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A2
P/S
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE43503
Product Specification
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V
Parameter
Test Conditions
Frequency
Min.
Typical
Frequency Range
Max.
Units
DC – 6
Attenuation Range
1 dB Step
0 – 31
DC ≤ 6 GHz
Insertion Loss
DC ≤ 6 GHz
Relative Phase
All States
P1dB
Input
20 MHz - 6 GHz
Input IP3
Two tones at +18 dBm, 20 MHz spacing
Return Loss
Switching Speed
dB
2.4
DC ≤ 4 GHz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
0dB - 31dB Attenuation settings
0dB - 21dB Attenuation settings
22dB - 31dB Attenuation settings
0dB - 31dB Attenuation settings
Attenuation Error
GHz
Settling Time
RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON.
dB
dB
dB
dB
°
dBm
20 MHz – 6 GHz
+58
dBm
DC ≤ 6 GHz
17
dB
650
ns
-115
dBm
Video Feed Through
10% / 90% RF
±(0.3+3%)
+0.4+9%
+2.4+0%
-0.2-3%
72
1 MHz
RF Trise/Tfall
dB
32
30
50% DC CTRL to 10% / 90% RF
Typical Spurious Value
2.9
10
mVpp
400
ns
4
µs
Performance Plots
Figure 3. 1dB Step Error vs. Frequency *
200MHz
4000MHz
1.6
900MHz
5000MHz
1800MHz
6000MHz
Figure 4. 1dB Attenuation vs. Attenuation State
2200MHz
Attenuation
35
1.4
Attenuation (dB)
dB
30
Step Error (dB.)
1.2
1
0.8
0.6
0.4
900 MHz
2200 MHz
3800 MHz
5800 MHz
25
20
15
10
5
0.2
0
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
Attenuation State
*Monotonicity is held so long as Step-Error does not cross zero
Figure 5. 1dB Major State Bit Error
2dB State
16dB State
Figure 6. 1dB Attenuation Error vs. Frequency
4dB State
31dB State
2.00
2
1.50
1.5
1.00
1
Attenuation Error (dB.)
Bit Error (dB.)
1dB State
8dB State
0.50
0.00
-0.50
-1.00
-1.50
200MHz
4000MHz
2200MHz
5000MHz
3000MHz
6000MHz
0.5
0
-0.5
-1
-1.5
-2.00
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Frequency (GHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
-2
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
Document No. 70-0252-04
│ UltraCMOS™ RFIC Solutions
PE43503
Product Specification
Figure 7. Insertion Loss vs. Temperature
+25C
0dB
4dB
+85C
0
0
-0.5
-5
Input Return Loss (dB.)
Insertion Loss (dB)
-40C
Figure 8. Input Return Loss vs. Attenuation
@ T = +25C
-1
-1.5
-2
-2.5
-3
0.5dB
8dB
-10
-15
-20
-25
-30
-40
0
2
4
6
8
10
0
1
2
3
Frequency (GHz.)
0dB
4dB
0
4
5
6
7
8
9
Frequency (GHz.)
Figure 10. Relative Phase vs. Frequency
Figure 9. Output Return Loss vs. Attenuation
@ T = +25C
0.5dB
8dB
1dB
16dB
2dB
31dB
0dB
8dB
140
Relative Phase Error (Deg.)
-5
-10
Return Loss (dB.)
2dB
31dB
-35
-3.5
-15
-20
-25
-30
-35
-40
1dB
16dB
2dB
31dB
4dB
120
100
80
60
40
20
-45
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
Frequency (GHz.)
-40C
+25C
4
5
6
7
8
Frequency (GHz.)
Figure 12. Input IP3 vs. Frequency
Figure 11. Attenuation Error vs. Temperature
@ 6 GHz
0dB
8dB
+85C
2
70
1.5
65
1
60
Input IP3 (dBm.)
Attenuation Error (dB.)
1dB
16dB
0.5
0
-0.5
1dB
16dB
2dB
31dB
4dB
55
50
45
-1
40
-1.5
35
30
-2
0
5
10
15
20
Attenuation Setting (dB.)
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25
30
35
0
500
1000
1500
2000
2500
3000
3500
4000
4500
Frequency (MHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE43503
Product Specification
Figure 13. Pin Configuration (Top View)
Table 3. Operating Ranges
GND C1 C2 C4 C8 C16
24
23
22
21
20
Parameter
19
VDD Power Supply Voltage
Min
Typ
3.0
3.3
Max
Units
V
NC
1
18
SI
VDD
2
17
CLK
VDD Power Supply Voltage
5.0
5.5
V
16
LE
IDD Power Supply Current
70
350
µA
15
5.5
V
Fig. 14
+23
dBm
dBm
85
°C
P/S
3
GND
4
GND
Digital Input High
RF1
5
14
RF2
GND
6
13
GND
PIN Input power (50Ω):
1 Hz ≤ 20 MHz
20 MHz ≤ 4 GHz
7
8
9
10
11
12
GND
GND
GND
GND
GND
GND
Exposed
Solder Pad
TOP Operating temperature range
Pin Name
NC
No Connect
2
VDD
Power supply pin
3
P/S
Serial/Parallel mode select
4
GND
Ground
VDD
5
RF1
RF1 port
GND
Ground
GND
Ground
13
GND
Ground
14
RF2
RF2 port
15
GND
Ground
0
16
LE
17
CLK
Latch Enable input
18
SI
19
C16
Attenuation control bit, 16 dB
20
C8
Attenuation control bit, 8 dB
21
C4
Attenuation control bit, 4 dB
22
C2
Attenuation control bit, 2 dB
23
C1
Attenuation control bit, 1 dB
24
GND
Serial interface clock input
Serial Interface input
1
V
15
µA
Units
Note 1. Input leakage current per Control pin
1
6
25
Digital Input Leakage1
Description
7 - 12
-40
Digital Input Low
Table 2. Pin Descriptions
Pin No.
2.6
Table 4. Absolute Maximum Ratings
Symbol
Min
Max
Power supply voltage
Parameter/Conditions
-0.3
6.0
V
VI
Voltage on any Digital input
-0.3
5.8
V
TST
Storage temperature range
-65
150
°C
Fig. 14
+23
500
100
dBm
dBm
V
V
Input power (50Ω)
1 Hz ≤ 20 MHz
20 MHz ≤ 4 GHz
ESD voltage (HBM)1
ESD voltage (Machine Model)
PIN
VESD
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Figure 14. Maximum Power Handling Capability
Ground
30.0
Ground C1 C2, C4, C8, C16 if not in use.
25.0
Exposed Solder Pad Connection
20.0
Pin dBm
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
15.0
10.0
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43503 in
the 24-lead 4x4 QFN package is MSL1.
5.0
0.0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Switching Frequency
The PE43503 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
1.0E+07
1.0E+08
1.0E+09
Hz
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESDsensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Document No. 70-0252-04
│ UltraCMOS™ RFIC Solutions
PE43503
Product Specification
Table 5. Control Voltage
State
Bias Condition
Low
0 to +1.0 Vdc at 2 µA (typ)
High
+2.6 to +5 Vdc at 10 µA (typ)
Table 6. Latch and Clock Specifications
Latch Enable
Shift Clock
Function
X
↑
↑
X
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
Table 8. Attenuation Word Truth Table
Attenuation Word
D1
D0
(LSB)
Attenuation
Setting
RF1-RF2
D6
D5
D4
D3
D2
Attenuation Setting
RF1-RF2
L
L
L
L
L
Reference I.L.
X
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
H
1 dB
X
L
L
L
L
H
L
L
1 dB
L
L
L
H
L
2 dB
X
L
L
L
H
L
L
L
2 dB
L
L
H
L
L
4 dB
X
L
L
H
L
L
L
L
4 dB
L
H
L
L
L
8 dB
X
L
H
L
L
L
L
L
8 dB
H
L
L
L
L
16 dB
X
H
L
L
L
L
L
L
16 dB
H
H
H
H
H
31 dB
X
H
H
H
H
H
H
H
31 dB
D7
D6
D5
D4
D3
D2
Table 9. Serial Register Map
MSB (last in)
LSB (first in)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
D6
D5
D4
D3
D2
D1
D0
Bits can either be set to logic high or logic low
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 13 dB state:
Attenuation Word: Multiply by 4 and convert to binary → 4 *13 dB → 52 → X0110100
Serial Input: X0110100
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Page 5 of 11
PE43503
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE43503. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of five CMOScompatible control lines that select the desired
attenuation state, as shown in Table 7.
The parallel interface timing requirements are
defined by Fig. 16 (Parallel Interface Timing
Diagram), Table 11 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched-parallel programming the Latch
Enable (LE) should be held LOW while changing
attenuation state control values, then pulse LE
HIGH to LOW (per Fig. 16) to latch new
attenuation state into device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial Interface
The serial interface is a 8-bit serial-in, parallel-out
shift register buffered by a transparent latch. The
8-bits make up the Attenuation Word that controls
the DSA. Fig. 15 illustrates a example timing
diagram for programming a state. When the DSA
is used in serial mode, ground all parallel control
pins (pins 19-23).
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 11
The serial-interface is controlled using three
CMOS-compatible signals: Serial-In (SI), Clock
(CLK), and Latch Enable (LE). The SI and CLK
inputs allow data to be serially entered into the
shift register. Serial data is clocked in LSB first.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from
changing as data is entered. The LE input should
then be toggled HIGH and brought LOW again,
latching the new data into the DSA. Attenuation
Word truth table is listed in Table 8. A
programming example of the serial register is
illustrated in Table 9. The serial timing diagram is
illustrated in Fig. 15.
Power-up Control Settings
The PE43503 will always initialize to the maximum
attenuation setting (31 dB) on power-up for the
latched-parallel mode of operation and will remain
in this setting until the user latches in the next
programming word. In direct-parallel mode, the
DSA can be preset to any state within the 31 dB
range by pre-setting the parallel control pins prior
to power-up. In this mode, there is a 400-µs delay
between the time the DSA is powered-up to the
time the desired state is set. During this power-up
delay, the device attenuates to the maximum
attenuation setting (31 dB) before defaulting to the
user defined state. If the control pins are left
floating in this mode during power-up, the device
will default to the minimum attenuation setting
(insertion loss state).
Document No. 70-0252-04
│ UltraCMOS™ RFIC Solutions
PE43503
Product Specification
Figure 15. Serial Timing Diagram
Bits can either be set to logic high or logic low
TDISU
TDIH
P/S
TPSSU
TPSIH
D[6]
SI
TSISU
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
TSIH
CLK
TCLKL
TCLKH
TLESU
LE
TLEPW
TPD
VALID
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU
DI[6:0]
TPSIH
VALID
TDISU
TDIH
LE
TLEPW
DO[6:0]
VALID
TDIPD
TPD
Table 10. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
FCLK
Serial clock frequency
-
10
MHz
TCLKH
Serial clock HIGH time
30
-
ns
TCLKL
Serial clock LOW time
30
-
ns
TLESU
Last serial clock rising edge
setup time to Latch Enable
rising edge
10
-
ns
TLEPW
Latch Enable min. pulse width
30
-
ns
TSISU
Serial data setup time
10
-
ns
TSIH
Serial data hold time
10
-
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
TLEPW
Latch Enable minimum
pulse width
30
-
ns
TDISU
Parallel data setup time
100
-
ns
TDIH
Parallel data hold time
100
-
ns
TPSSU
Parallel/Serial setup time
100
-
ns
ns
TPSIH
Parallel/Serial hold time
100
-
ns
TPD
Digital register delay
(internal)
-
10
ns
Digital register delay
(internal, direct mode only)
-
5
ns
TDISU
Parallel data setup time
100
-
ns
TDIH
Parallel data hold time
100
-
ns
TASU
Address setup time
100
-
ns
Address hold time
100
-
ns
TPSSU
Parallel/Serial setup time
100
-
ns
TPSH
Parallel/Serial hold time
100
-
ns
TPD
Digital register delay (internal)
-
10
ns
TAH
Table 11. Parallel and Direct Interface AC
Characteristics
TDIPD
Note: fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE43503
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE43503 Digital Step Attenuator.
Figure 17. Evaluation Board Layout
Peregrine Specification 101-0310
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D6 SP3T switches to
the ‘MIDDLE’ toggle position. Position the
Parallel/Serial (P/S) select switch to the Parallel
(or left) position. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Direct-Parallel mode.
Using the software, enable or disable each setting
to the desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Parallel/Serial (P/S) select switch to the Parallel
(or left) position. The LE pin on the Serial header
must be tied to VDD. Switches D0-D6 are SP3T
switches which enable the user to manually
program the parallel bits. When any input D0-D6
is toggled ‘UP’, logic high is presented to the
parallel input. When toggled ‘DOWN’, logic low is
presented to the parallel input. Setting D0-D6 to
the ‘MIDDLE’ toggle position presents an OPEN,
which forces an on-chip logic low. Table 9 depicts
the parallel programming truth table and Fig. 16
illustrates the parallel programming timing
diagram.
Latched-Parallel Programming Procedure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel
method. The user only must ensure that LatchedParallel is selected in the software.
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
the LE pin on the Serial header must be logic low
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 11
Note: Reference Figure 18 for Evaluation Board Schematic
as the parallel bits are applied. The user must
then pulse LE from 0V to VDD and back to 0V to
latch the programming word into the DSA. LE
must be logic low prior to programming the next
word.
Serial Programming Procedure
Position the Parallel/Serial (P/S) select switch to
the Serial (or right) position. The evaluation
software is written to operate the DSA in either
Parallel or Serial Mode. Ensure that the software
is set to program in Serial mode. Using the
software, enable or disable each setting to the
desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
Document No. 70-0252-04
│ UltraCMOS™ RFIC Solutions
PE43503
Product Specification
Figure 18. Evaluation Board Schematic
Peregrine Specification 102-0379
4
2
1
4
3
3
D6
D6
D5
3
D4
3
D3
3
D2
2
1
4
2
1
4
2
1
4
2
1
4
D1
3
D5
D4
D3
D2
D0
P/ S
5
D1
3
D0
P/S
2
1
4
2
1
6
4
VDD
J1
HEADER 14
D0
1
3
5
7
9
11
13
D1
D2
D3
D4
D5
D6
2
D5
D3
D6
19
21
22
20
C8
C16
18
17
LE
16
GND
15
5
RF1
RF2
14
6
GND
GND
13
J5
SMA
1
Z=50 Ohm
J7
SMA
1
2
2
1
43X0X DSA 50 Ohm 4x4 MLP24
SI
CLK
CLOCK
DATA
LE
GND
2
Z=50 Ohm
1
De-embeding trace
Z=50 Ohm
GND
GND
100pF
J4
SMA
J6
SMA
4
U1
GND
100pF
S/P
1
2
3
4
12
100pF
3
C14
11
100pF
0.1µF
C13
VDD
GND
C8
CP25
2
GND
C10
1
P/S
7
C9
D0
VDD
GND
1
2
C4
CP5
VDD
J3
CON2
C2
100pF
100pF
9
100pF
SERIAL
HEADER 4
CLK
DATA
LE
C4
C3
24
100pF
D4
D1
100pF
C2
10
C1
C7
D2
C6
100pF
23
C5
100pF
C1
1
3
5
7
9
11
13
GND
2
4
6
8
10
12
14
8
2
4
6
8
10
12
14
Note: Capacitors C1-C8, C13, & C14 may be omitted.
Figure 19. Package Drawing
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE43503
Product Specification
Figure 20. Tape and Reel Drawing
Tape Feed Direction
Pin 1
A0 = 4.35
B0 = 4.35
K0 = 1.1
Top of
Device
Device Orientation in Tape
Figure 21. Marking Specifications
43503
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 12. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
EK-43503-01
PE43503 -EK
PE43503 – 24QFN 4x4mm-EK
Evaluation Kit
1 / Box
PE43503 MLI
43503
PE43503 G - 24QFN 4x4mm-75A
Green 24-lead 4x4mm QFN
Bulk or tape cut from reel
PE43503 MLI-Z
43503
PE43503 G – 24QFN 4x4mm-3000C
Green 24-lead 4x4mm QFN
3000 units / T&R
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 11
PE43503
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
High-Reliability and Defense Products
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Fax: +82-31-728-3940
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0252-04
│ UltraCMOS™ RFIC Solutions