SSM2307N
P-CHANNEL ENHANCEMENT MODE POWER MOSFET
Simple drive requirement
Small package outline
D
Surface-mount device
BV DSS
-16V
R DS(ON)
60mΩ
- 4A
ID
S
SOT-23 G
Description
D
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
low on-resistance and cost-effectiveness.
G
S
The SOT-23 package is widely preferred for commercial and
industrial surface mount applications and is well suited for low
voltage applications such as DC/DC converters.
Absolute Maximum Ratings
Symbol
Parameter
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
-16
V
±8
V
3
-4
A
3
-3.3
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
-12
A
PD @ TA=25°C
Total Power Dissipation
1.38
W
Linear Derating Factor
0.01
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
Rev.1.01 4/06/2004
Parameter
Thermal Resistance Junction-ambient
3
Max.
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Value
Unit
90
°C/W
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SSM2307N
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
-16
-
-
V
-
-0.01
-
V/°C
VGS=-4.5V, ID=-4A
-
-
60
mΩ
VGS=-2.5V, ID=-3.0A
-
-
70
mΩ
VGS=-1.8V, ID=-2.0A
-
-
90
mΩ
VDS=VGS, ID=-250uA
-
-
-1.0
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA
RDS(ON)
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
2
VDS=-5V, ID=-4A
-
12
-
S
o
VDS=-16V, VGS=0V
-
-
-1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=-12V, VGS=0V
-
-
-25
uA
Gate-Source Leakage
VGS=±8V
-
-
±100
nA
ID=-4A
-
15
24
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=-250uA
Max. Units
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=-12V
-
1.3
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
4
-
nC
VDS=-10V
-
8
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
-
11
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=-10V
-
54
-
ns
tf
Fall Time
RD=10Ω
-
36
-
ns
Ciss
Input Capacitance
VGS=0V
-
985
1580
pF
Coss
Output Capacitance
VDS=-15V
-
180
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
160
-
pF
Min.
Typ.
IS=-1.2A, VGS=0V
-
-
-1.2
V
IS=-4A, VGS=0V,
-
39
-
ns
dI/dt=100A/µs
-
26
-
nC
Source-Drain Diode
Symbol
VSD
Parameter
2
Forward On Voltage
2
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Test Conditions
Max. Units
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 270°C/W when mounted on min. copper pad.
Rev.1.01 4/06/2004
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SSM2307N
16
14
12
10
-5.0V
-4.5V
-3.0V
-2.5V
T A = 150 o C
12
ID , Drain Current (A)
T A =25 o C
14
-ID , Drain Current (A)
-5.0V
-4.5V
-3.0V
-2.5V
V G = - 1.8 V
8
6
10
V G = - 1.8 V
8
6
4
4
2
2
0
0
0
1
2
3
4
5
0
6
-V DS , Drain-to-Source Voltage (V)
2
4
6
8
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
70
1.6
I D =-3A
ID= -4A
V G = -4.5V
1.4
Normalized RDS(ON)
T A =25 o C
RDS(ON) Ω
60
50
1.2
1.0
0.8
40
0.6
1
3
5
7
9
-50
0
50
100
150
o
-V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
3
2.0
Normalized -VGS(th) (V)
1.5
-IS(A)
2
T j =150 o C
T j =25 o C
1
0
0.5
0.0
0
0.2
0.4
0.6
0.8
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Rev.1.01 4/06/2004
1.0
1
-50
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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SSM2307N
-VGS , Gate to Source Voltage (V)
8
f=1.0MHz
10000
I D =-4A
V DS =-16V
C (pF)
6
4
C iss
1000
2
C oss
C rss
0
100
0
8
16
24
32
1
5
9
13
17
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100.00
Normalized Thermal Response (Rthja)
Duty factor=0.5
10.00
-ID (A)
1ms
1.00
10ms
100ms
0.10
o
T A =25 C
Single Pulse
1s
DC
0.01
0.2
0.1
0.1
0.05
PDM
0.01
t
T
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
Rthja = 270°C/W
0.001
0.1
1
10
100
0.0001
0.001
0.01
-V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Charge
Q
Fig 12. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.1.01 4/06/2004
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