SSM4224M
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFET
Low on-resistance
D2
Simple drive requirement
D2
D1
D1
Dual N-MOSFET package
BV DSS
30V
R DS(ON)
14mΩ
10A
ID
G2
S2
SO-8
S1
G1
Description
Advanced power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
D2
D1
G2
G1
S2
S1
Absolute Maximum Ratings
Symbol
Parameter
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
30
V
±20
V
3
10
A
3
8
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
30
A
PD @ TA=25°C
Total Power Dissipation
2
W
Linear Derating Factor
0.016
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
Rev.1.01 4/06/2004
Parameter
Thermal Resistance Junction-ambient
3
Max.
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Value
Unit
62.5
°C/W
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SSM4224M
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Typ.
Max. Units
30
-
-
V
V/°C
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.03
-
RDS(ON)
Static Drain-Source On-Resistance2
VGS=10V, ID=10A
-
-
14
mΩ
VGS=4.5V, ID=7A
-
-
20
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=10V, ID=10A
-
16
-
S
o
VDS=30V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=24V, VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±20V
-
-
±100
nA
ID=10A
-
23
35
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Min.
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=24V
-
6
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
14
-
nC
VDS=15V
-
12
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
8
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω , VGS=10V
-
34
-
ns
tf
Fall Time
RD=15Ω
-
16
-
ns
Ciss
Input Capacitance
VGS=0V
-
1910 3070
pF
Coss
Output Capacitance
VDS=25V
-
400
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
280
-
pF
Rg
Gate Resistance
f=1.0MHz
-
0.9
-
Ω
Min.
Typ.
IS=1.7A, VGS=0V
-
-
1.2
V
Source-Drain Diode
Symbol
VSD
Parameter
2
Forward On Voltage
2
Test Conditions
Max. Units
trr
Reverse Recovery Time
IS=10A, VGS=0V,
-
30
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
24
-
nC
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300µs , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad.
Rev.1.01 4/06/2004
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2 of 4
SSM4224M
180
140
T A = 25 o C
10V
7.0V
T A = 150 o C
120
10V
7.0V
100
ID , Drain Current (A)
ID , Drain Current (A)
150
120
90
5.0V
60
4.5V
80
5.0V
60
4.5V
40
30
V G = 3 .0V
20
V G = 3 .0V
0
0
0
1
2
3
4
0
5
2
3
4
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
20
1.8
ID=7A
T A =25 ℃
18
I D =1 0 A
V G =10V
1.6
Normalized R DS(ON)
16
RDS(ON) (mΩ )
1
V DS , Drain-to-Source Voltage (V)
14
12
1.4
1.2
1.0
0.8
10
0.6
8
3
5
7
9
-50
11
V GS , Gate-to-Source Voltage (V)
0
50
100
150
o
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
3.0
10
8
2.5
IS(A)
VGS(th) (V)
6
o
o
T j =150 C
4
T j =25 C
2.0
1.5
2
0
1.0
0
0.2
0.4
0.6
0.8
1
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Rev.1.01 4/06/2004
1.2
-50
0
50
100
150
T j , Junction Temperature ( o C)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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3 of 4
SSM4224M
f=1.0MHz
10000
16
V DS =15V
V DS =20V
V DS =24V
12
C iss
C (pF)
VGS , Gate to Source Voltage (V)
ID=10A
8
1000
C oss
C rss
4
0
100
0
10
20
30
40
50
1
5
Fig 7. Gate Charge Characteristics
13
17
21
25
29
Fig 8. Typical Capacitance Characteristics
1
Normalized Thermal Response (Rthja)
100
1ms
10
ID (A)
9
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
10ms
1
100ms
1s
0.1
T A =25 o C
Single Pulse
DC
0.01
Duty factor=0.5
0.2
0.1
0.1
0.05
PDM
0.02
t
T
0.01
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
Rthja = 135℃
℃ /W
0.001
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Charge
Q
Fig 12. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.1.01 4/06/2004
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