SSM9915K
N-CHANNEL ENHANCEMENT MODE POWER MOSFET
Simple drive requirement
D
Lower gate charge
Fast switching characteristic
BVDSS
20V
RDS(ON)
50mΩ
6.2A
ID
S
D
SOT-223 G
Description
D
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
low on-resistance and cost-effectiveness.
G
S
Absolute Maximum Ratings
Parameter
Symbol
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Continuous Drain Current
3
Continuous Drain Current
3
1
Rating
Units
20
V
±12
V
6.2
A
5
A
30
A
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
3.2
W
Linear Derating Factor
0.025
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
Rev.1.01 4/06/2004
Parameter
Thermal Resistance Junction-ambient
3
Max.
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Value
Unit
40
°C/W
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SSM9915K
Electrical Characteristics @ T j=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
20
-
-
V
-
0.03
-
V/°C
VGS=4.5V, ID=6A
-
-
50
mΩ
VGS=2.5V, ID=4A
-
-
80
mΩ
0.5
-
1.2
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
RDS(ON)
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
2
VDS=VGS, ID=250uA
VDS=10V, ID=5A
-
13
-
S
o
VDS=20V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=16V ,VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±12V
-
-
±100
nA
ID=10A
-
5
8
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Max. Units
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=16V
-
1
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
2
-
nC
2
td(on)
Turn-on Delay Time
VDS=10V
-
8
-
ns
tr
Rise Time
ID=10A
-
55
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω, VGS=5V
-
10
-
ns
tf
Fall Time
RD=1Ω
-
3
-
ns
Ciss
Input Capacitance
VGS=0V
-
360
580
pF
Coss
Output Capacitance
VDS=20V
-
70
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
50
-
pF
Rg
Gate Resistance
f=1.0MHz
-
0.78
-
Ω
Min.
Typ.
IS=2.5A, VGS=0V
-
-
1.3
V
Source-Drain Diode
Symbol
VSD
Parameter
Forward On Voltage
2
2
Test Conditions
Max. Units
trr
Reverse Recovery Time
IS=10A, VGS=0V,
-
17
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
9
-
nC
Notes:
1.Pulse width limited by safe operating area.
2.Pulse width <300us , duty cycle <2%.
2
3.t≦10sec , Surface mounted on 1 in copper pad of FR4 board.
Rev.1.01 4/06/2004
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2 of 4
SSM9915K
50
40
o
T A =25 C
T A =150 o C
ID , Drain Current (A)
ID , Drain Current (A)
4.5V
40
30
3.5V
20
2.5V
10
30
4.5V
20
3.5V
10
2.5V
V G =1.5V
V G =1.5V
0
0
0
1
2
3
4
0
5
Fig 1. Typical Output Characteristics
2
3
4
5
6
Fig 2. Typical Output Characteristics
80
1.8
ID=4A
I D =6A
1.6
T A =25 o C
V G =4.5V
Normalized R DS(ON)
70
R DS(ON) (mΩ )
1
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
60
50
1.4
1.2
1.0
40
0.8
0.6
30
1
2
3
4
5
V GS , Gate-to-Source Voltage (V)
100
150
o
Fig 4. Normalized On-Resistance
vs. Junction Temperature
1.2
10
0.95
VGS(th) (V)
100
IS (A)
50
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
1
T j =150 o C
0
-50
6
o
T j =25 C
0.7
0.45
0.1
0.2
0.01
0
0.4
0.8
1.2
V SD , Source -to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Rev.1.01 4/06/2004
-50
0
50
100
150
o
T j , Junction Temperature ( C )
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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3 of 4
SSM9915K
f=1.0MHz
1000
I D =6A
12
C iss
V DS =16V
V DS =12V
V DS =10V
10
8
C (pF)
VGS , Gate to Source Voltage (V)
14
6
100
C oss
C rss
4
2
10
0
0
2
4
6
8
10
12
1
14
5
9
Fig 7. Gate Charge Characteristics
17
21
25
29
Fig 8. Typical Capacitance Characteristics
1
Normalized Thermal Response (Rthja)
100
10
1ms
ID (A)
13
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
1
10ms
100ms
1s
10s
DC
0.1
o
T A =25 C
Single Pulse
0.01
Duty factor=0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
Single Pulse
t
0.01
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=90oC/W Per Unit Base
0.001
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Charge
Q
Fig 12. Gate Charge Waveform
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guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.1.01 4/06/2004
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