BB INA205AIDGSTG4

 INA203
INA204
INA205
INA
203
INA2
03
INA
203
SBOS393 – MARCH 2007
Unidirectional Measurement
Current-Shunt Monitor with Dual Comparators
FEATURES
•
•
•
•
•
•
•
DESCRIPTION
COMPLETE CURRENT SENSE SOLUTION
DUAL COMPARATORS:
– Comparator 1 with Latch
– Comparator 2 with Optional Delay
COMMON-MODE RANGE: –16V to +80V
HIGH ACCURACY: 3.5% (max) Over
Temperature
BANDWIDTH: 500kHz
QUIESCENT CURRENT: 1.8mA
PACKAGES: SO-14, TSSOP-14, MSOP-10
APPLICATIONS
•
•
•
•
•
•
•
NOTEBOOK COMPUTERS
CELL PHONES
TELECOM EQUIPMENT
AUTOMOTIVE
POWER MANAGEMENT
BATTERY CHARGERS
WELDING EQUIPMENT
1
OUT
2
1.2V REF
The INA203, INA204, and INA205 also incorporate
two open-drain comparators with internal 0.6V
references. On 14-pin versions, the comparator
references can be overridden by external inputs.
Comparator 1 includes a latching capability, and
Comparator 2 has a user-programmable delay.
14-pin versions also provide a 1.2V reference output.
The INA203, INA204, and INA205 operate from a
single +2.7V to +18V supply. They are specified over
the extended operating temperature range of –40°C
to +125°C.
INA203-INA205
VS
1
10 VIN+
OUT
2
9
VIN-
14 VIN+
CMP1 IN+
3
8
CMP1 OUT
13 VIN-
CMP2 IN+
4
7
CMP2 OUT
GND
5
6
CMP1 RESET
INA203-INA205
VS
The INA203, INA204, and INA205 are a family of
unidirectional, current-shunt monitors with voltage
output, dual comparators, and voltage reference. The
INA203, INA204, and INA205 can sense drops
across shunts at common-mode voltages from –16V
to +80V. The INA203, INA204, and INA205 are
available with three output voltage scales: 20V/V,
50V/V, and 100V/V, with up to 500kHz bandwidth.
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
0.6V REF
MSOP-10
DEVICE
GAIN
INA203
20V/V
INA204
50V/V
INA205
100V/V
SO-14, TSSOP-14
RELATED PRODUCTS
FEATURES
PRODUCT
Variant of INA203–INA205 Comparator 2 polarity
INA206–INA208
Current-shunt monitor with single Comparator
and VREF
INA200–INA202
Current-shunt monitor only
INA193–INA198
Current-shunt monitor with split stages for filter
options
INA270–INA271
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
INA203
INA204
INA205
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SBOS393 – MARCH 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
INA203
INA204
INA205
(1)
(2)
GAIN
PACKAGE
DESIGNATOR
PACKAGE
MARKING
1.2V
REF OUT
EXTERNAL
COMP1 AND
COMP2
REF INPUTS
SO-14 (2)
D
INA203A
X
X
MSOP-10
DGS
BQN
TSSOP-14 (2)
PW
INA203A
X
X
X
X
SO-14 (2)
D
INA204A
X
X
X
X
MSOP-10
DGS
BQO
TSSOP-14 (2)
PW
INA204A
X
X
X
X
SO-14 (2)
D
INA205A
X
X
X
X
MSOP-10
DGS
BQP
TSSOP-14 (2)
PW
INA205A
PACKAGELEAD
20V/V
50V/V
100V/V
INTERNAL
COMP1 AND
COMP2
0.6V REF
COMP2
DELAY
PIN
X
X
X
X
X
X
X
X
X
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Available Q3, 2007.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
18
V
Differential (VIN+) – (VIN–)
–18 to +18
V
Common-Mode
–16 to +80
V
Comparator Analog Input and Reset Pins
GND – 0.3 to (V+) + 0.3
V
Analog Output, Out Pin
Supply Voltage, V+
Current-Shunt Monitor Analog Inputs, VIN+and VIN–:
GND – 0.3 to (V+) + 0.3
V
Comparator Output, Out Pin
GND – 0.3 to 18
V
VREF and CMP2 Delay Pin
GND – 0.3 to 10
V
Input Current Into Any Pin
5
mA
Operating Temperature
–55 to +150
°C
Storage Temperature
–65 to +150
°C
Junction Temperature
+150
°C
Human Body Model (HBM)
4000
V
Charged Device Model (CDM)
1000
V
ESD Ratings:
(1)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
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INA204
INA205
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SBOS393 – MARCH 2007
ELECTRICAL CHARACTERISTICS: CURRENT-SHUNT MONITOR
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted.
INA203, INA204, INA205
CURRENT-SHUNT MONITOR PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
0.15
(VS – 0.25)/Gain
V
INPUT
Full-Scale Sense Input Voltage
Common-Mode Input Range
Common-Mode Rejection Ratio
VSENSE
CMRR
Over Temperature
Offset Voltage, RTI (1)
VSENSE = VIN+ – VIN–
VCM
–16
VCM = –16V to +80V
80
VCM = +12V to +80V
100
80
100
123
±0.5
VOS
+25°C to +125°C
vs Temperature
vs Power Supply
Input Bias Current, VIN– Pin
dB
±2.5
mV
±3
mV
±3.5
–40°C to +25°C
dVOS/dT
PSR
V
dB
mV
µV/°C
TMIN to TMAX
5
VOUT = 2V, VCM = +18V, 2.7V
2.5
100
µV/V
±9
±16
µA
IB
OUTPUT (VSENSE ≥ 20mV)
Gain:
G
INA203
20
V/V
INA204
50
V/V
INA205
100
Gain Error
VSENSE = 20mV to 100mV
Over Temperature
VSENSE = 20mV to 100mV
Total Output Error (2)
VSENSE = 120mV, VS = +16V
Over Temperature
±0.75
VSENSE = 120mV, VS = +16V
Nonlinearity Error (3)
Output Impedance, Pin 2
±0.2
VSENSE = 20mV to 100mV
%
±2
%
±2.2
%
±3.5
%
±0.002
%
1.5
Ω
No Sustained Oscillation
10
nF
–16V ≤ VCM < 0V
300
RO
Maximum Capacitive Load
V/V
±1
OUTPUT (VSENSE < 20mV) (4)
INA203, INA204, INA205
mV
INA203
0V ≤ VCM ≤ VS, VS = 5V
0.4
V
INA204
0V ≤ VCM ≤ VS, VS = 5V
1
V
INA205
0V ≤ VCM ≤ VS, VS = 5V
VS < VCM ≤ 80V
INA203, INA204, INA205
2
300
V
mV
VOLTAGE OUTPUT (5)
Output Swing to the Positive Rail
VIN– = 11V, VIN+ = 12V
(V+) – 0.15
(V+) – 0.25
V
Output Swing to GND (6)
VIN– = 0V, VIN+ = –0.5V
(VGND) + 0.004
(VGND) + 0.05
V
INA203
CLOAD = 5pF
500
kHz
INA204
CLOAD = 5pF
300
kHz
INA205
CLOAD = 5pF
200
kHz
Phase Margin
CLOAD < 10nF
40
Degrees
1
V/µs
2
µs
40
nV/√Hz
FREQUENCY RESPONSE
Bandwidth:
Slew Rate
Settling Time (1%)
BW
SR
VSENSE = 10mVPP to 100mVPP,
CLOAD = 5pF
NOISE, RTI
Output Voltage Noise Density
(1)
(2)
(3)
(4)
(5)
(6)
Offset is extrapolated from measurements of the output at 20mV and 100mV VSENSE.
Total output error includes effects of gain error and VOS.
Linearity is best fit to a straight line.
For details on this region of operation, see the Accuracy Variations section in the Applications Information.
See Typical Characteristic curve Positive Output Voltage Swing vs Output Current (Figure 8).
Specified by design; not production tested.
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INA204
INA205
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SBOS393 – MARCH 2007
ELECTRICAL CHARACTERISTICS: COMPARATOR
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from
CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.
INA203, INA204, INA205
COMPARATOR PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Offset Voltage
Comparator Common-Mode Voltage = Threshold Voltage
Offset Voltage Drift, Comparator 1
Offset Voltage Drift, Comparator 2
2
mV
±2
µV/°C
µV/°C
+5.4
Threshold
TA = +25°C
590
Over Temperature
600
586
610
mV
614
mV
Hysteresis (1), CMP1
TA = –40°C to +85°C
–8
mV
Hysteresis (1),
TA = –40°C to +85°C
8
mV
CMP2
INPUT BIAS CURRENT (2)
CMP1 IN+, CMP2 IN+
0.005
vs Temperature
10
nA
15
nA
INPUT IMPEDANCE
Pins 3 and 6 (14-pin packages only)
10
kΩ
CMP1 IN+ and CMP2 IN+
0V to VS – 1.5V
V
Pins 3 and 6 (14-pin packages only) (3)
0V to VS – 1.5V
V
INPUT RANGE
OUTPUT
CMP VOUT 1V to 4V, RL ≥ 15kΩ Connected to 5V
200
High-Level Output Current
VID = 0.4V, VOH = VS
0.0001
1
µA
Low-Level Output Voltage
VID = –0.6V, IOL = 2.35mA
220
300
mV
Comparator 1
RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive
1.3
µs
Comparator 2
RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive,
CDELAY Pin Open
1.3
µs
Large-Signal Differential Voltage Gain
V/mV
RESPONSE TIME (4)
RESET
RESET Threshold (5)
Logic Input Impedance
Minimum RESET Pulse Width
Comparator 2 Delay
(1)
(2)
(3)
(4)
(5)
(6)
tD
MΩ
1.5
µs
3
µs
µF
0.5
s
CDELAY = 0.1µF
Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to Figure 1.
Specified by design; not production tested.
See the Comparator Maximum Input Voltage Range section in the Applications Information.
The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4V.
The CMP1 RESET input has an internal 2MΩ (typical) pull-down. Leaving the CMP1 RESET open results in a LOW state, with
transparent comparator operation.
The Comparator 2 delay applies to both rising and falling edges of the comparator output.
VTHRESHOLD
0.592
VTHRESHOLD
0.6
0.6
0.608
Input Voltage
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
Hysteresis = VTHRESHOLD - 8mV
a) CMP1
b) CMP2
Figure 1. Comparator Hysteresis
4
V
2
CDELAY = tD/5
RESET Propagation Delay
Comparator 2 Delay Equation (6)
1.1
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INA204
INA205
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SBOS393 – MARCH 2007
ELECTRICAL CHARACTERISTICS: REFERENCE
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from
CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.
INA203, INA204, INA205
REFERENCE PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
1.188
1.2
1.212
V
40
100
ppm/°C
REFERENCE VOLTAGE
1.2VREFOUT Output Voltage
Reference Drift
dVOUT/dT
TA = –40°C to +85°C
0.6VREF Output Voltage (Pins 3 and 6 of 14-pin packages only)
Reference Drift
0.6
dVOUT/dT
LOAD REGULATION
V
TA = –40°C to +85°C
40
100
ppm/°C
0mA < ISOURCE < 0.5mA
0.4
2
mV/mA
0mA < ISINK < 0.5mA
0.4
mV/mA
1
mA
2.7V < VS < 18V
30
µV/V
No Sustained Oscillations
10
nF
10
kΩ
dVOUT/dILOAD
Sourcing
Sinking
LOAD CURRENT
ILOAD
LINE REGULATION
dVOUT/dVS
CAPACITIVE LOAD
Reference Output Maximum Capacitive Load
OUTPUT IMPEDANCE
Pins 3 and 6 of 14-Pin Packages Only
ELECTRICAL CHARACTERISTICS: GENERAL
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
All specifications at TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each
connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted.
INA203, INA204, INA205
GENERAL PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Operating Power Supply
Quiescent Current
VS
IQ
Over Temperature
+2.7
VOUT = 2V
1.8
VSENSE = 0mV
Comparator Power-On Reset Threshold (1)
+18
V
2.2
mA
2.8
mA
1.5
V
TEMPERATURE
Specified Temperature Range
–40
+125
°C
Operating Temperature Range
–55
+150
°C
Storage Temperature Range
–65
+150
°C
Thermal Resistance
(1)
θJA
MSOP-10 Surface-Mount
200
°C/W
SO-14, TSSOP-14 Surface-Mount
150
°C/W
The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET is
open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator
assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output
comes up high and requires a reset to assume a low state, if appropriate.
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INA204
INA205
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SBOS393 – MARCH 2007
TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
GAIN vs FREQUENCY
45
G = 50
35
Gain (dB)
30
G = 100
40
G = 50
35
Gain (dB)
CLOAD = 1000pF
G = 100
40
GAIN vs FREQUENCY
45
G = 20
25
20
30
20
15
15
10
10
5
5
10k
100k
G = 20
25
CLOAD = 0
10k
1M
100k
Frequency (Hz)
Figure 2.
Figure 3.
GAIN PLOT
COMMON-MODE AND POWER-SUPPLY REJECTION
vs FREQUENCY
20
140
18
130
Common-Mode and
Power-Supply Rejection (dB)
100V/V
16
VOUT (V)
14
50V/V
12
10
8
20V/V
6
4
CMR
110
100
90
PSR
80
70
60
40
0
20
100
200
300
400
500
600
700
800
900
10
100
1k
10k
100k
VSENSE (mV)
Frequency (Hz)
Figure 4.
Figure 5.
TOTAL OUTPUT ERROR vs VSENSE
TOTAL OUTPUT ERROR vs COMMON-MODE VOLTAGE
4.0
0.1
3.5
0.09
3.0
Total Output Error (%)
Total Output Error
(% error of the ideal output value)
120
50
2
2.5
2.0
1.5
1.0
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.5
0.01
0
0
50
100 150
200
250 300
350 400 450 500
0
-16 -12 -8 -4
VSENSE (mV)
0
4
8
12 16 20
Common-Mode Voltage (V)
Figure 6.
6
1M
Frequency (Hz)
Figure 7.
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INA204
INA205
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SBOS393 – MARCH 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
POSITIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT
QUIESCENT CURRENT vs OUTPUT VOLTAGE
3.5
12
11
VS = 12V
10
2.5
+25°C
8
-40°C
+125°C
7
6
VS = 3V
5
Sourcing Current
+25°C
4
-40°C
Output stage is designed
to source current. Current
sinking capability is
approximately 400mA.
3
2
1
+125°C
0
0
IQ (mA)
Output Voltage (V)
3.0
Sourcing Current
9
2.0
1.5
1.0
0.5
0
5
10
20
15
25
30
0
1
2
Output Current (mA)
5
7
9
10
9.5 10.5 11.5 17
18
6
8
Figure 8.
Figure 9.
QUIESCENT CURRENT
vs COMMON-MODE VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs SUPPLY VOLTAGE
34
VSENSE = 100mV
1.75
VS = 2.7V
VS = 12V
1.50
1.25
VS = 12V
1.00
VS = 2.7V
VSENSE = 0mV
0.75
0.50
-16 -12 -8 -4
-40°C
30
+25°C
26
+125°C
22
18
14
10
6
0
4
8
12 16 20 24 28 32 36
2.5 3.5
VCM (V)
4.5
5.5 6.5
7.5
8.5
Supply Voltage (V)
Figure 10.
Figure 11.
STEP RESPONSE
STEP RESPONSE
G = 20
G = 20
Output Voltage (500mV/div)
Output Voltage (50mV/div)
IQ (mA)
4
Output Voltage (V)
Output Short-Circuit Current (mA)
2.00
3
VSENSE = 10mV to 20mV
VSENSE = 10mV to 100mV
Time (2ms/div)
Time (2ms/div)
Figure 12.
Figure 13.
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INA204
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SBOS393 – MARCH 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
STEP RESPONSE
STEP RESPONSE
G = 50
Output Voltage (50mV/div)
Output Voltage (100mV/div)
G = 20
VSENSE = 90mV to 100mV
VSENSE = 10mV to 20mV
Time (2ms/div)
Time (5ms/div)
Figure 14.
Figure 15.
STEP RESPONSE
STEP RESPONSE
G = 50
Output Voltage (1V/div)
Output Voltage (100mV/div)
G = 50
VSENSE = 90mV to 100mV
VSENSE = 10mV to 100mV
Time (5ms/div)
Time (5ms/div)
Figure 16.
Figure 17.
STEP RESPONSE
COMPARATOR VOL vs ISINK
600
G = 100
Output Voltage (2V/div)
500
VOL (mV)
400
300
200
100
VSENSE = 10mV to 100mV
0
Time (10ms/div)
0
1
2
3
ISINK (mA)
Figure 18.
8
Figure 19.
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5
6
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INA204
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SBOS393 – MARCH 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
COMPARATOR TRIP POINT vs SUPPLY VOLTAGE
COMPARATOR TRIP POINT vs TEMPERATURE
600
602
Comparator Trip Point (mV)
Comparator Trip Point (mV)
599
598
597
596
595
594
593
592
601
600
599
598
597
591
596
590
2
4
6
8
10
12
14
16
18
-25
-50
0
Supply Voltage (V)
25
50
75
100
125
Temperature (°C)
Figure 20.
Figure 21.
COMPARATOR 1 PROPAGATION DELAY
vs OVERDRIVE VOLTAGE
COMPARATOR 2 PROPAGATION DELAY
vs OVERDRIVE VOLTAGE
200
14
Propagation Delay (ms)
Propagation Delay (ns)
175
150
125
100
13
12
11
75
50
10
0
20
40
60
80
100 120 140
160 180
0
200
20
40
60
80
100 120 140
160 180
200
Overdrive Voltage (mV)
Figure 22.
Figure 23.
COMPARATOR RESET VOLTAGE vs
SUPPLY VOLTAGE
COMPARATOR 1 PROPAGATION DELAY vs
TEMPERATURE
1.2
300
1.0
275
Propagation Delay (ns)
Reset Voltage (V)
Overdrive Voltage (mV)
0.8
0.6
0.4
0.2
250
225
200
175
150
0
2
4
6
8
10
12
14
16
18
125
-50
Supply Voltage (V)
-25
0
25
50
75
100
125
Temperature (°C)
Figure 24.
Figure 25.
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SBOS393 – MARCH 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted.
COMPARATOR 2 PROPAGATION DELAY
vs CAPACITANCE
COMPARATOR 1 PROPAGATION DELAY
Propagation Delay (ms)
1000
100
Input
200mV/div
10
1
Output
2V/div
0.1
VOD = 5mV
0.01
0.001
0.01
0.1
1
10
2ms/div
100
Delay Capacitance (nF)
Figure 26.
Figure 27.
COMPARATOR 2 PROPAGATION DELAY
REFERENCE VOLTAGE vs TEMPERATURE
1.22
Input
200mV/div
VREF (V)
1.21
Output
2V/div
1.20
1.19
VOD = 5mV
5ms/div
1.18
-50
-25
0
25
50
Temperature (°C)
Figure 28.
10
Figure 29.
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100
125
INA203
INA204
INA205
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SBOS393 – MARCH 2007
APPLICATIONS INFORMATION
This section addresses the accuracy of
specific operating regions:
• Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS
• Normal Case 2: VSENSE ≥ 20mV, VCM < VS
• Low VSENSE Case 1: VSENSE < 20mV, –16V
<0
• Low VSENSE Case 2: VSENSE < 20mV, 0V ≤
VS
• Low VSENSE Case 3: VSENSE < 20mV, VS <
80V
BASIC CONNECTIONS
Figure 30 shows the basic connections of the
INA203, INA204, and INA205. The input pins, VIN+
and VIN–, should be connected as closely as possible
to the shunt resistor to minimize any resistance in
series with the shunt resistance.
Power-supply bypass capacitors are required for
stability. Applications with noisy or high-impedance
power supplies may require additional decoupling
capacitors to reject power-supply noise. Connect
bypass capacitors close to the device pins.
these
≤ VCM
VCM ≤
VCM ≤
Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS
This region of operation provides
accuracy. Here, the input offset
characterized and measured using
method. First, the gain is determined by
VOUT1 - VOUT2
G=
100mV - 20mV
POWER SUPPLY
The input circuitry of the INA203, INA204, and
INA205 can accurately measure beyond the
power-supply voltage, V+. For example, the V+
power supply can be 5V, whereas the load
power-supply voltage is up to +80V. The output
voltage range of the OUT terminal, however, is
limited by the voltages on the power-supply pin.
the highest
voltage is
a two-step
Equation 1.
(1)
where:
VOUT1 = Output Voltage with VSENSE = 100mV
ACCURACY VARIATIONS AS A RESULT OF
VSENSE AND COMMON-MODE VOLTAGE
VOUT2 = Output Voltage with VSENSE = 20mV
Then the offset voltage is measured at VSENSE =
100mV and referred to the input (RTI) of the current
shunt monitor, as shown in Equation 2.
VOUT1
VOSRTI (Referred-To-Input) =
- 100mV
G
(2)
The accuracy of the INA203, INA204, and INA205
current shunt monitors is a function of two main
variables: VSENSE (VIN+ – VIN–) and common-mode
voltage, VCM, relative to the supply voltage, VS. VCM
is expressed as (VIN+ + VIN–)/2; however, in practice,
VCM is seen as the voltage at VIN+ because the
voltage drop across VSENSE is usually small.
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt
Monitor Output
CBYPASS
0.01mF
INA203
x20
OUT
CMP1 IN-/0.6 REF
CMP1 IN+
1.2V REF
VIN+
VIN-
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 OUT
CMP2 IN+
CMP2 IN-/0.6 REF
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 30. INA20x Basic Connection
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INA204
INA205
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SBOS393 – MARCH 2007
Normal Case 2: VSENSE ≥ 20mV, VCM < VS
This region of operation has slightly less accuracy
than Normal Case 1 as a result of the common-mode
operating area in which the part functions, as seen in
the Output Error vs Common-Mode Voltage curve
(Figure 7). As noted, for this graph VS = 12V; for VCM
< 12V, the Output Error increases as VCM becomes
less than 12V, with a typical maximum error of
0.005% at the most negative VCM = –16V.
Low VSENSE Case 1:
VSENSE < 20mV, –16V ≤ VCM < 0; and
Low
VSENSE
Case
3:
VSENSE < 20mV, VS < VCM ≤ 80V
Although the INA203 family of devices are not
designed for accurate operation in either of these
regions, some applications are exposed to these
conditions; for example, when monitoring power
supplies that are switched on and off while VS is still
applied to the INA203, INA204, or INA205. It is
important to know what the behavior of the devices
will be in these regions.
As VSENSE approaches 0mV, in these VCM regions,
the
device
output
accuracy
degrades.
A
larger-than-normal offset can appear at the current
shunt monitor output with a typical maximum value of
VOUT = 300mV for VSENSE = 0mV. As VSENSE
approaches 20mV, VOUT returns to the expected
output value with accuracy as specified in the
Electrical Characteristics. Figure 31 illustrates this
effect using the INA205 (Gain = 100).
Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS
This region of operation is the least accurate for the
INA203 family. To achieve the wide input
common-mode voltage range, these devices use two
op amp front ends in parallel. One op amp front end
operates in the positive input common-mode voltage
range, and the other in the negative input region. For
this case, neither of these two internal amplifiers
dominates and overall loop gain is very low. Within
this region, VOUT approaches voltages close to linear
operation levels for Normal Case 2. This deviation
from linear operation becomes greatest the closer
VSENSE approaches 0V. Within this region, as VSENSE
approaches 20mV, device operation is closer to that
described by Normal Case 2. Figure 32 illustrates
this behavior for the INA205. The VOUT maximum
peak for this case is tested by maintaining a constant
VS, setting VSENSE = 0mV, and sweeping VCM from
0V to VS. The exact VCM at which VOUT peaks during
this test varies from part to part, but the VOUT
maximum peak is tested to be less than the specified
VOUT Tested Limit.
2.4
2.2 INA205 VOUT Tested Limit
(1)
VCM1
2.0
Ideal
1.8
VCM2
1.6
VOUT (V)
In the Typical Characteristics, the Output Error vs
Common-Mode Voltage curve (Figure 7) shows the
highest accuracy for this region of operation. In this
plot, VS = 12V; for VCM ≥ 12V, the output error is at
its minimum. This case is also used to create the
VSENSE ≥ 20mV output specifications in the Electrical
Characteristics table.
1.4
VCM3
1.2
1.0
0.8
VOUT Tested Limit at
VSENSE = 0mV, 0 £ VCM1 £ VS.
VCM4
0.6
VCM2, VCM3, and VCM4 illustrate the variance
from part to part of the VCM that can cause
maximum VOUT with VSENSE < 20mV.
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
VSENSE (mV)
NOTE: (1) INA203 VOUT Tested Limit = 0.4V. INA204 VOUT Tested Limit = 1V.
Figure 32. Example for Low VSENSE Case 2
(INA205, Gain = 100)
2.0
1.8
SELECTING RSHUNT
1.6
VOUT (V)
1.4
1.2
Actual
1.0
0.8
Ideal
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
VSENSE (mV)
The value chosen for the shunt resistor, RSHUNT,
depends on the application and is a compromise
between small-signal accuracy and maximum
permissible voltage loss in the measurement line.
High values of RSHUNT provide better accuracy at
lower currents by minimizing the effects of offset,
while low values of RSHUNT minimize voltage loss in
the supply line. For most applications, best
performance is attained with an RSHUNT value that
provides a full-scale shunt voltage range of 50mV to
100mV. Maximum input voltage for accurate
measurements is (VSHUNT – 0.25)/Gain.
Figure 31. Example for Low VSENSE Cases 1 and 3
(INA205, Gain = 100)
12
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INA204
INA205
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SBOS393 – MARCH 2007
TRANSIENT PROTECTION
illustrated when using the INA205 (a gain of 100
version), where a 100mV full-scale input from the
shunt resistor requires an output voltage swing of
+10V, and a power-supply voltage sufficient to
achieve +10V on the output.
The –16V to +80V common-mode range of the
INA203, INA204, and INA205 is ideal for
withstanding automotive fault conditions ranging from
12V battery reversal up to +80V transients, since no
additional protective components are needed up to
those levels. In the event that the INA203, INA204,
and INA205 are exposed to transients on the inputs
in excess of their ratings, then external transient
absorption with semiconductor transient absorbers
(zeners or Transzorbs) are necessary. Use of metal
oxide varistors (MOVs) or video disk recorders
(VDRs) is not recommended except when they are
used in addition to a semiconductor transient
absorber. Select the transient absorber such that it
will never allow the INA203, INA204, and INA205 to
be exposed to transients greater than +80V (that is,
allow for transient absorber tolerance, as well as
additional voltage because of transient absorber
dynamic impedance). Despite the use of internal
zener-type ESD protection, the INA203, INA204, and
INA205 do not lend themselves to using external
resistors in series with the inputs because the
internal gain resistors can vary up to ±30% but are
closely matched. (If gain accuracy is not important,
then resistors can be added in series with the
INA203, INA204, and INA205 inputs with two equal
resistors on each input.)
INPUT FILTERING
An obvious and straightforward location for filtering is
at the output of the INA203, INA204, and INA205
series; however, this location negates the advantage
of the low output impedance of the internal buffer.
The only other option for filtering is at the input pins
of the INA203, INA204, and INA205, which is
complicated by the internal 5kΩ + 30% input
impedance; this configuration is illustrated in
Figure 33. Using the lowest possible resistor values
minimizes both the initial shift in gain and effects of
tolerance. The effect on initial gain is given by
Equation 3:
5kW
5kW + RFILT
Gain Error % = 100 - 100 ´
(3)
Total effect on gain error can be calculated by
replacing the 5kΩ term with 5kΩ – 30%, (or 3.5kΩ)
or 5kΩ + 30% (or 6.5kΩ). The tolerance extremes of
RFILT can also be inserted into the equation. If a pair
of 100Ω 1% resistors are used on the inputs, the
initial gain error will be 1.96%. Worst-case tolerance
conditions will always occur at the lower excursion of
the internal 5kΩ resistor (3.5kΩ), and the higher
excursion of RFILT – 3% in this case.
OUTPUT VOLTAGE RANGE
The output of the INA203, INA204, and INA205 is
accurate within the output voltage swing range set by
the power-supply pin, V+. This performance is best
RSHUNT << RFILTER
3mW
VSUPPLY
Load
RFILTER < 100W
RFILTER <100W
CFILTER
INA203-INA205
VIN+
VS
1
14
OUT
2
13
CMP1 IN-/0.6V REF
3
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
1.2V REF
VIN-
12 1.2V REF OUT
f-3dB
f-3dB =
1
2p(2RFILTER)CFILTER
SO-14, TSSOP-14
Figure 33. Input Filter (Gain Error: 1.5% to –2.2%)
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INA204
INA205
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SBOS393 – MARCH 2007
Note that the specified accuracy of the INA203,
INA204, and INA205 must then be combined in
addition to these tolerances. While this discussion
treated accuracy worst-case conditions by combining
the extremes of the resistor values, it is appropriate
to use geometric mean or root sum square
calculations to total the effects of accuracy
variations.
REFERENCE
The INA203, INA204, and INA205 include an internal
voltage reference that has a load regulation of
0.4mV/mA (typical), and not more than 100ppm/°C of
drift. Only the 14-pin package allows external access
to reference voltages, where voltages of 1.2V and
0.6V are both available. Output current versus output
voltage is illustrated in the Typical Characteristics
section.
A simplified version of the delay circuit for
Comparator 2 is shown in Figure 34. The delay
comparator consists of two comparator stages with
the delay between them. Note that I1 and I2 cannot
be turned on simultaneously; I1 corresponds to a U1
low output and I2 corresponds to a U1 high output.
Using an initial assumption that the U1 output is low,
I1 is on, then U2 +IN is zero. If U1 goes high, I2
supplies 120nA to CDELAY. The voltage at U2 +IN
begins to ramp toward a 0.6V threshold. When the
voltage crosses this threshold, the U2 output goes
high while the voltage at U2 +IN continues to ramp
up to a maximum of 1.2V when given sufficient time
(twice the value of the delay specified for CDELAY).
This entire sequence is reversed when the
comparator outputs go low, so that returning to low
exhibits the same delay.
1.2V
COMPARATOR
I2
120nA
The INA203, INA204, and INA205 devices
incorporate two open-drain comparators. These
comparators typically have 2mV of offset and a 1.3µs
(typical) response time. The output of Comparator 1
latches and is reset through the CMP1 RESET pin,
as shown in Figure 35. This configuration applies to
both the 10- and 14-pin versions. Figure 34
illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and
INA205 include additional features for comparator
functions. The comparator reference voltage of both
Comparator 1 and Comparator 2 can be overridden
by external inputs for increased design flexibility.
Comparator 2 has a programmable delay.
U1
U2
I1
120nA
0.6V
CDELAY
Figure 34. Simplified Model of the Comparator 2
Delay Circuit
COMPARATOR DELAY (14-Pin Version Only)
The Comparator 2 programmable delay is controlled
by a capacitor connected to the CMP2 Delay Pin;
see Figure 30. The capacitor value (in µF) is
selected by using Equation 4:
t
CDELAY (in mF) = D
5
(4)
0.6V
VIN
0V
CMP Out
RESET
Figure 35. Comparator Latching Capability
14
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INA204
INA205
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SBOS393 – MARCH 2007
It is important to note what will happen if events
occur more rapidly than the delay timeout; for
example, when the U1 output goes high (turning on
I2), but returns low (turning I1 back on) prior to
reaching the 0.6V transition for U2. The voltage at
U2 +IN ramps back down at a rate determined by the
value of CDELAY, and only returns to zero if given
sufficient time.
voltage and whether either or both inputs are subject
to the large voltage. When making this
determination, consider the 20kΩ from each input
back to the comparator. Figure 37 shows the
maximum input voltage that avoids creating a
reference error when driving both inputs (an
equivalent resistance back into the reference of
10kΩ).
In essence, when analyzing Comparator 2 for
behavior with events more rapid than its delay
setting, use the model shown in Figure 34.
£ 1mA
1.2V
20kW
COMPARATOR MAXIMUM INPUT VOLTAGE
RANGE
20kW
CMP1 IN-
The maximum voltage at the comparator input for
normal operation is up to (V+) – 1.5V. There are
special considerations when overdriving the
reference inputs (pins 3 and 6). Driving either or both
inputs high enough to drive 1mA back into the
reference introduces errors into the reference.
Figure 36 shows the basic input structure. A general
guideline is to limit the voltage on both inputs to a
total of 20V. The exact limit depends on the available
CMP2 IN+
Figure 36. Limit Current Into Reference ≤ 1mA
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt Monitor Output
CMP1 IN-/0.6 REF
V < 11.2
INA203
x20
OUT
CBYPASS
0.01mF
1.2V REF
VIN+
VIN-
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 37. Overdriving Comparator Inputs Without Generating a Reference Error
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INA203
INA204
INA205
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SBOS393 – MARCH 2007
Raychem
Polyswitch
Load
< 18V
Battery
+5V Supply
VS+
x20
1.2V REF
CMP1 IN-
3.3kW
Pull-Up
Resistors
VIN+
INA203
OUT
VIN1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Overlimit
Warning
(1)
(1)
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
Figure 38. Polyswitch Warning and Fault Detection Circuit
RSHUNT
0.02W
Load
Q2
NDS8434A
R1
100kW
+5V Supply
R7
1kW
VS+
R5
100kW
R6
6.04kW
R3
14kW
R4
6.04kW
CMP1 IN-
VIN+
INA203
x20
OUT
1.2V REF
Q1
2N3904
VIN-
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
R2
1kW
1.2V REF OUT
Reset
Latch
Figure 39. Lead-Acid Battery Protection Circuit
16
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
INA203AIDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA203AIDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA203AIDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA203AIDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA204AIDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA204AIDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA204AIDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA204AIDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA205AIDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA205AIDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA205AIDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
INA205AIDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
17-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
INA203AIDGSR
DGS
10
MLA
330
12
5.3
3.4
1.4
8
12
PKGORN
T1TR-MS
P
INA203AIDGST
DGS
10
MLA
0
0
5.3
3.4
1.4
8
12
PKGORN
T1TR-MS
P
INA204AIDGSR
DGS
10
MLA
330
12
5.3
3.4
1.4
8
12
PKGORN
T1TR-MS
P
INA204AIDGST
DGS
10
MLA
0
0
5.3
3.4
1.4
8
12
PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
INA203AIDGSR
DGS
10
MLA
390.0
348.0
63.0
INA203AIDGST
DGS
10
MLA
342.9
336.6
28.58
INA204AIDGSR
DGS
10
MLA
390.0
348.0
63.0
INA204AIDGST
DGS
10
MLA
342.9
336.6
28.58
Pack Materials-Page 2
Height (mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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