MultiGEN ™ GF9103 Over-Sampling Color Space Converter for Video Monitoring DATA SHEET FEATURES DEVICE DESCRIPTION • 4:2:2 to over-sampled RGB or YCBCR conversion in a single device The GF9103 is specifically designed to simplify conversions from 4:2:2 component digital video to analog RGB or analog YCBCR component video. The GF9103 simplifies this process by performing 4:2:2 to 8:8:8 interpolation, digital color space conversion and digital SIN X/X correction in a single device. Immediately following the GF9103, three over-sampled channels of RGB or YCBCR data may be passed through Digital to Analog converters and simplified analog reconstruction filters. • single 10 bit 4:2:2 input • internal 4:2:2 de-multiplexer • 4:2:2 to 8:8:8 interpolation filters • internal YCBCR to RGB color space conversion • optional YCBCR (8:8:8) output mode • setup insertion in Luminance channel under user control The GF9103 accepts a single 10 bit stream of 4:2:2 data and internally de-multiplexes it into three 10 bit channels of The YCBCR data is then passed through YCBCR data. three linear phase FIR filters that over-sample the Y data by a factor of 2 and the CB and CR data by a factor of 4. • user selectable digital SIN X/X correction • rounding to 10/8 bit resolution per output channel • 40 MHz maximum clock rate While operating in an over-sampled RGB output mode, the interpolated YCBCR data is passed through the internal color space converter to convert the YCBCR data to RGB data according to CCIR-601. Alternatively, the color space converter may be bypassed to obtain over-sampled YC BCR (8:8:8) output data. While operating in YCBCR output mode, setup may be dynamically inserted into the Luminance channel. • single +5 V power supply APPLICATIONS • Over-Sampling 4:2:2 to Analog RGB Conversions for video monitoring • Over-Sampling 4:2:2 to Analog YCBCR Conversions for video monitoring ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE RANGE GF9103-CPS 68 pin PLCC 0° to 70° C GF9103-CTS 68 pin PLCC Tape 0° to 70° C Prior to output rounding, over-sampled YCBCR or RGB data may be corrected for SIN X/X characteristics of D/A conversion. Output data may be rounded to 10 or 8 bit resolution per channel. CB and CR may be presented as signed or unsigned data. The GF9103 is packaged in a 68 pin PLCC package, operates with a single +5 V power supply and typically consumes only 85 mA of current when operated at 27 MHz. SELECT_MATRIX SETUP Y Y X2 MULTIPLEXED 4:2:2 DATA STREAM IN 10 4:2:2 DEMUX CB CR CLK X4 X4 Y/G Y SETUP CB CR CONVERT BYPASS Y/G CR YCBCR TO RGB MATRIX CB/B Y/G CB/B CR/R CLIP & ROUND 10 2's COMP CLIP & ROUND CR/R SIN X/X Y/G CB/B CB/B SIN X/X CR/R 10 CLIP & ROUND SIN X/X CB OE CB/B CR/R 2's COMP 10 CR/R SYNC FUNCTIONAL BLOCK DIAGRAM Revision Date: August 1997 Document No. 521 - 33 - 04 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com PIN DESCRIPTION PIN NO. SYMBOL 10, 18, 27, 36, 44, 52, 61, 68 VDD ±5 V ± 5% power supply. 1, 6, 7, 9, 26, 30, 35, 40, 43, 60, 64 GND Ground. SCAN_EN Set Low. 3 8, 11-17, 19, 20 SI9..0 DESCRIPTION Input Data Port: Input data port with internal pull-downs. Input data is assumed to be a multiplexed stream of CBYCR [Y] CB..., where [Y] denotes an isolated Luminance sample. SI9 is the Most Significant Bit and SI0 is the Least Significant Bit. 4 OE Output Enable: Active low input with internal pull-up. When OE is high, the output data ports are in high impedance state. 59-53, 51-49 SOA9..0 Output Data Port A: Depending on device configuration, SOA9..0 may output over-sampled Y or G video. SOA9 is the Most Significant Bit and SOA0 is the Least Significant Bit. 48-45, 42, 41, 39-37, 34 SOB9..0 Output Data Port B: Depending on device configuration, SOB9..0 may output over-sampled CB or B video. SOB9 is the Most Significant Bit and SOB0 is the Least Significant Bit. 33-31, 29, 28, 25-21 SOC9..0 Output Data Port C: Depending on device configuration, SOC9..0 may output over-sampled CR or R video. SOC9 is the Most Significant Bit and SOC0 is the Least Significant Bit. 2 CLK 5 SYNC 65 SELECT_MATRIX 66 BYPASS 63 SETUP 62 CONVERT System Clock: All timing information relative to rising edge of clock. Synchronization: Control signal input with internal pull-up. This input is used to synchronize the incoming data by holding SYNC high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until resynchronization is desired or may be toggled at every occurrence of a CB sample. Select Color Space Conversion: Control signal input with internal pull-down. SELECT_MATRIX is used to enable and disable the internal YCBCR to RGB color space converter. Color space conversion is enabled while SELECT_MATRIX is high and is disabled while SELECT_MATRIX is low. Bypass SIN X/X Correction: Control signal input with internal pull-up. When BYPASS is high, SIN X/X correction for the three output channels is enabled. While BYPASS is low, SIN X/X correction is by-passed. Setup: Control signal input with internal pull-down. SETUP is used to enable and disable setup insertion in the Luminance channel. Two's Complement Conversion: Control signal input with internal pull-up. While CONVERT is high, SOB9..0 and SOC9..0 output signed (two’s complement) digital data. While CONVERT is low, SOB9..0 and SOC9..0 output unsigned (offset binary) data. When operating in RGB output mode, the CONVERT pin is over-ridden and both SOB9..0 and SOC9..0 output unsigned digital data. SOA9..0 outputs unsigned digital data in all operating modes. 67 521 - 33 - 04 RND10/8 Output Rounding: Control signal input with internal pull-up. RND10/8 selects rounding to 10 bit resolution per channel when high and rounding to 8 bit resolution per channel when low. 2 CLK GND VDD 5 4 3 2 1 68 67 66 65 64 63 62 61 60 SI8 11 59 SOA9 SI7 12 58 SOA8 SI6 13 57 SOA7 SI5 14 56 SOA6 SI4 15 55 SOA5 SI3 16 54 SOA4 SI2 17 53 SOA3 VDD 18 52 VDD SI1 19 51 SOA2 SI0 20 50 SOA1 SOC0 21 49 SOA0 SOC1 22 48 SOB9 SOC2 23 47 SOB8 SOC3 24 46 SOB7 SOC4 25 45 SOB6 GND VDD GND SOB5 SOB4 GND SOB3 SOB2 VDD SOB1 GND SOB0 SOC9 SOC8 GND SOC7 SOC6 VDD 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SOC5 GND GF9103 TOP VIEW VDD SCAN_EN CONVERT OE 6 SETUP SYNC 7 GND GND SELECT_MATRIX GND 8 BYPASS SI9 9 10 RND10/8 GND VDD Fig. 1 GF9103 Pin Connections VDD VDD n SUBSTRATE n SUBSTRATE p D1 D1 p p+ p+ CONTROL INPUT n+ n+ D2 n n D2 p WELL p WELL GND GND Fig. 2a Equivalent Input Circuit Fig. 2b Equivalent Output Circuit 3 521 - 33 - 04 DEVICE DESCRIPTION The CB and CR data is over-sampled by a linear phase FIR filter providing 0.0 dB DC gain, passband ripple of +0.2 dB/0.2 dB [0.0 to 0.07 ƒs], 6 dB attenuation at ƒs/8 and a stopband attenuation of 28 dB [ 0.17ƒs to 0.50 ƒs]. The GF9103 is composed of five main sections: 1. 4:2:2 De-Multiplexer Figure 5 and Figure 6 present the frequency response of the CB and CR interpolation filters. 2. FIR Filtering and Setup Insertion 3. Color Space Conversion Following the interpolation process, a DC offset may be introduced into the Luminance channel. Setup insertion is enabled and disabled by the SETUP control signal. While SETUP is high, the Luminance data is scaled by a factor of +947/1024 and an offset of +71 (decimal) is added. While SETUP is low, no scaling or offset is applied and the data passes through the stage unmodified. The timing diagram in Figure 10 demonstrates the operation of the SETUP control signal. 4. Digital SIN X/X Correction 5. Output Processing 4:2:2 DE-MULTIPLEXER The de-multiplexer accepts data multiplexed in a SMPTE 125M compliant format from the SI9..0 input data port. SI9 is the Most Significant Bit and SI0 is the Least Significant Bit. The input data stream is assumed to be a multiplexed stream of CB Y CR [Y] CB..., where the three words CB Y CR refer to cosited samples and where [Y] refers to an isolated Luminance sample. When operating the GF9103 with 8 bit input data, SI9..2 should be used to present data to the device and SI1..0 should be set low. COLOR SPACE CONVERSION Two operating modes exist for the color space converter section. These two modes are controlled by the SELECT_MATRIX control signal. While SELECT_MATRIX is low, the de-matrixing 3 x 3 multiplier is bypassed so that over-sampled Y CB CR data is passed through the stage unmodified. While SELECT_MATRIX is high, the 3 x 3 multiplier implements the following color space conversion: At least once during a power cycle, the GF9103 must be synchronized to the incoming data stream. The GF9103 is synchronized by holding SYNC high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until re-synchronization is desired, or it may be toggled at every occurrence of a CB sample. Refer to the timing diagram in Figure 9 for required operation of the SYNC control signal. G B = R The internal de-multiplexer will de-multiplex all data in the input data stream including any ancillary, EDH,VITC, and EAV/SAV ... signals that may be present. Since this data is passed directly to the interpolation filters in the same way that active video would be, it is recommended that such data be replaced with appropriate blanking levels prior to entering the GF9103. 1 1 1 -689/2048 3548/2048 0 -1430/2048 0 2807/2048 Y CB CR SIN X/X CORRECTION The output of the 4:2:2 de-multiplexer consists of three 10 bit channels of YCBCR data. All three channels are then fed to their respective interpolation filter. While BYPASS is high, SIN X/X correction is enabled on each of the three output channels. SIN X/X correction is implemented by passing the data through a FIR filter with the frequency response shown in Figure 7. While BYPASS is low, the FIR filter is bypassed and each channel is passed directly to the output processing section. Total latency through the device is 22 clock cycles when BYPASS is low and 24 clock cycles when BYPASS is high. INTERPOLATION FILTERS OUTPUT PROCESSING Within the interpolation stage, the Luminance data is oversampled by a factor of two and the CB and CR data is oversampled by a factor of four so that the 4:2:2 data is converted to 8:8:8 data. By over-sampling the 4:2:2 data to 8:8:8 data, the size, cost and complexity of the analog reconstruction filters following Digital to Analog converters are reduced. Output data may be rounded to 10 or 8 bit accuracy. RND10/8 should be set high for 10 bit output rounding and set low for 8 bit output rounding. Rounding to 8 bit accuracy is accomplished by adding a rounding bit to SO1 and then zeroing both SO0 and SO1. CB and CR data may be output as signed (two’s complement) or unsigned (offset binary) data depending on the state of the CONVERT control signal. When CONVERT is set high, the CB and CR channels are output as signed (two’s complement) data. When CONVERT is set low, CB and CR are output as unsigned (offset binary) data, obtained by inverting the sign bit of the two's complement number. When operating in RGB output mode, the CONVERT pin is over-ridden and RGB data is always output as unsigned (offset binary) data. The Luminance data is over-sampled by a linear phase FIR filter providing 0.0 dB DC gain, +0.038/-0.025 pass- band ripple [0.0 ƒs to 0.21 ƒs], 6 dB attenuation at ƒs/4, and 47 dB stopband attenuation [0.30 ƒs to 0.50 ƒs]. Figure 3 and Figure 4 present the frequency response of the Luminance interpolation filter. 521 - 33 - 04 4 CONTROL SIGNAL/OPERATING MODE SUMMARY SYNC The SYNC control signal provides synchronization for the internal 4:2:2 de-multiplexer. SYNC should be held high on clock period N and low on clock period N+1 when the first CB sample is presented to the SI9..0 inputs. SYNC may be held low until re-synchronization is desired or may be toggled at every occurrence of a CB sample. SELECT_MATRIX AND SETUP SELECT_MATRIX and SETUP select the color space conversion and offset insertions which the GF9103 is to perform. The following chart presents the available color space conversions and the corresponding states of the SELECT_MATRIX and SETUP control pins. SETUP is a dynamic pin that may be modified every clock cycle. SELECT_MATRIX SETUP DESCRIPTION 0 0 Selects output to be over-sampled YCBCR with no setup in Y channel. 0 1 Selects output to be over-sampled YCBCR with a scaling factor of +947/1024 and an offset of +71 (decimal) applied to the Y channel. 1 X Selects output to be over-sampled RGB with no setup. SIN X/X CORRECTION BYPASS DESCRIPTION 1 SIN X/X correction enabled on all output data channels. Latency through the device is 24 clock cycles. 0 SIN X/X correction disabled. Latency through the device is 22 clock cycles. OUTPUT ROUNDING RND10/8 DESCRIPTION 1 Output data rounded to 10 bit resolution per channel. 0 Output data rounded to 8 bit resolution per channel. TWO’S COMPLEMENT OUTPUT CONVERSION CONVERT SELECT_MATRIX DESCRIPTION 1 0 SOB9..0 and SOC9..0 output signed (two's complement) CB and CR data. 0 0 SOB9..0 and SOC9..0 output unsigned (offset binary) CB and CR data. X 1 SOB9..0 and SOC9..0 output unsigned B and R data. OUTPUT ENABLE OE DESCRIPTION 0 All output data ports are enabled. 1 All output data ports are in high impedance state. 5 521 - 33 - 04 0.10 -8 0.08 -16 0.06 -24 0.04 MAGNITUDE (dB) MAGNITUDE (dB) 0 -32 -40 -48 -56 0.02 0.00 -0.02 -0.04 -64 -0.06 -72 -0.08 -80 -0.10 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 0.00 1.35 4.05 5.40 6.75 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 3 Frequency Response of Luminance Interpolation Filter (Sampling at ƒs=27MHz) Fig. 4 Frequency Response of Luminance Interpolation Filter (Sampling at ƒs=27MHz) 0 1.0 -4 0.8 -8 0.6 -12 0.4 MAGNITUDE (dB) MAGNITUDE (dB) 2.70 -16 -20 -24 -28 -32 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -36 -1.0 -40 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 0.00 0.54 1.08 1.62 2.16 2.70 3.24 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 5 Frequency Response of Chrominance Interpolation Filter (Sampling at ƒs=27MHz) Fig. 6 Frequency Response of Chrominance Interpolation Filter (Sampling at ƒs=27MHz) 2.0 1.8 PARAMETER 1.6 MAGNITUDE (dB) 1.4 Filter Order LUMINANCE FILTER CHROMINANCE FILTER 31 15 1.2 Pass Band Ripple 1.0 +0.038 / -0.025 dB +0.2 / -0.2 dB (0.0 ƒs to 0.21 ƒs) (0.0 ƒs to 0.21 ƒs) 0.0 dB 0.0 dB Attenuation -6.00 dB (at ƒS/4) -6.00 dB (at ƒS/8) Stop Band Attenuation -47 dB -28 dB (0.30 ƒs to 0.50 ƒs) (0.17 ƒs to 0.50 ƒs) 0.8 0.6 DC Gain 0.4 0.2 0.0 -0.2 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 FREQUENCY (MHz) fig. 8 luminance and chrominance filter characteristics Fig. 7 SIN X/X Compensation Filter Frequency Response (Sampling at ƒs=27MHz) 521 - 33 - 04 6 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage -0.3 to +7.0 V Input Voltage Range (any input) +0.5 to (VDD +0.5) V 0°C ≤ TA ≤ 70°C Operating Temperature Range -65°C ≤ TS ≤ 150°C Storage Temperature Range Lead Temperature Range (soldering 10 seconds) 260°C ELECTRICAL CHARACTERISTICS VDD = 5V, TA = 0°C, RL = 150 Ω to GND and 144 Ω AC coupled unless otherwise shown. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.75 5 5.25 V Supply Voltage VDD Supply Current Quiescent IDDQ VDD = Max, VIN = 0V - 5 9 mA Supply Current Unloaded IDDU VDD = Max, OE = VDD, ƒ = 27MHz - 85 150 mA Input Voltage, Logic Low VIL - - 0.2VDD V Input Voltage, Logic High VIH 0.7VDD - - V Switching Threshold VT CMOS - 2.5 - V Input Current: (CMOS Inputs) IIN VIN = VDD or GND -10 ±1 10 µA Inputs with Pulldown Resistors VIN = VDD 35 115 222 µA Inputs with Pullup Resistors V IN = GND -35 -115 -214 µA Output Voltage, Logic Low VOL VDD = Min, IOL = 4mA - 0.2 0.4 V Output Voltage, Logic High VOH VDD = Min, IOH = -4mA 2.4 4.5 - V Hi-Z Output Leakage Current IOZ VDD = Max, OE = 1 -10 ±1 10 µA Short Circuit Output Current IOS VDD = Max, output high one pin to ground, one second duration max - - 140 mA Input Capacitance CIN TA = 25°C, ƒ = 1MHz - - 10 pF COUT TA = 25°C, ƒ = 1MHz - - 10 pF Output Capacitance 0 1 2 CLOCK SI9..0 3 4 tPWH CB tS Y 5 tPWL CR 6 7 tCY Y CB Y CR tH SYNC Fig. 9 Operation of SYNC Control Signal 7 521 - 33 - 04 SWITCHING CHARACTERISTICS TA from 0°C to 70°C unless otherwise specified. NAME tD PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output delay VDD = Min, CL = 25pF 8 9 10 ns tOH Output hold time VDD = Max, CL = 25pF 1 - - ns tEN Output enable VDD = Min, CL = 25pF - - 8 ns tDIS Output disable VDD = Min, CL = 25pF - - 8 ns tCY Cycle time 25 - - ns tPWL Clock pulse width low 10 - - ns tPWH Clock pulse width high 10 - - ns tS Input setup time 8 - - ns tH Input hold time 1 - - ns 0 1 2 3 CLOCK 4 tPWH CB Y SI9..0 tS 5 6 tPWL tCY CR Y 7 CB Y Y tH SETUP Fig. 10 Operation of SETUP Control Signal 0 1 2 3 4 5 6 7 CLOCK tPWH CB SI9..0 tPWL tCY Y CR Y CB 27 28 29 30 Y CR 31 32 tH tS SYNC 25 26 CLOCK tD SOA9..0 SOB9..0 SOC9..0 1 2 tOH 3 4 5 Fig. 11 Input/Output Timing, BYPASS = 1 521 - 33 - 04 8 6 7 8 0 1 2 3 4 CLOCK tPWL tPWH CB SI9..0 CR Y 5 6 7 tCY Y CB Y CR 28 29 30 tS tH SYNC 23 24 25 CLOCK SOA9..0 SOB9..0 SOC9..0 26 tD 1 2 27 tOH 3 4 6 5 tDIS 7 8 tEN OE Fig. 12 Input/Output Timing, BYPASS = 0 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION REVISION NOTES: DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright March 1995 Gennum Corporation. All rights reserved. Printed in Canada. 9 521 - 33 - 04