AD ADV611

a
Closed Circuit TV Digital
Video Codec
ADV611/ADV612
FEATURES
Programmable “Quality Box”
Industrial Temperature Range (ADV612)
Hardware Frame Rate Reduction
100% Bitstream Compatible with the ADV601 and
ADV601LC
Precise Compressed Bit Rate Control
Field Independent Compression
8-Bit Video Interface Supports CCIR-656 and Multiplexed Philips Formats
General Purpose 16- or 32-Bit Host Interface with
512 Deep 32-Bit FIFO
levels. The chips integrate glueless video and host interfaces
with on-chip SRAM to permit low part count, system level
implementations suitable for a broad range of applications.
The ADV611/ADV612 are 100% bitstream compatible with
the ADV601. The ADV611/ADV612 comes in a 120-lead
LQFP package.
The ADV611/ADV612 are video encoders/decoders optimized
for closed circuit TV (CCTV) applications. With the ADV611/
ADV612, you can define a portion of each video field to be at a
higher quality level relative to the rest of the field. This “quality
box” feature significantly increases compression of less important background details, while retaining the image’s overall
context. Additionally, the unique subband coding architecture
of the ADV611/ADV612 offer many application-specific
advantages. A review of the General Theory of Operation and
Applying the ADV611/ADV612 sections will help you get the
most use out of the ADV611/ADV612 in any given application.
PERFORMANCE
Real-Time Compression or Decompression of CCIR-601
to Video:
720 ⴛ 288 @ 50 Fields/Sec — PAL
720 ⴛ 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less to 7500:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
The ADV611/ADV612 accept component digital video through
the Video Interface and outputs a compressed bitstream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV611/ADV612 accept compressed bitstream through the Host
Interface and outputs component digital video through the Video
Interface. The host accesses all of the ADV611/ADV612’s control
and status registers using the Host Interface. Figure 2 summarizes
the basic function of the part.
APPLICATIONS
CCTV Cameras and Systems
Time-Lapse Video Tape Recorders
Time-Lapse Video Disk Recorders
Wireless CCTV Cameras
Fiber CCTV Systems
(continued on page 2)
ANALOG
VIDEO
SIGNAL
GENERAL DESCRIPTION
The ADV611/ADV612 are low cost, single chip, dedicated function, all-digital-CMOS-VLSI devices capable of supporting
visually loss-less to 7500:1 real-time compression and decompression of CCIR-601 digital video at very high image quality
ADV7185
DECODER
ADV611/
ADV612
OR
IMAGE
SENSOR
SIGNAL
ADSP-21xx
DIGITIZER
SERIAL
OR PARALLEL
BITSTREAM FOR
TRANSMISSION
OR STORAGE
QUALITY BOX CONTROLS
FROM REMOTE SITE
Figure 1. Typical Application
FUNCTIONAL BLOCK DIAGRAM
LOCATION, SIZE AND CONTRAST CONTROL
ADV611/
ADV612
COMPONENT
VIDEO I/O
8
DIGITAL
VIDEO
I/O PORT
ON-CHIP
TRANSFORM
BUFFER
QUALITY
BOX
CONTROL
WAVELET
FILTERS,
DECIMATOR &
INTERPOLATOR
DRAM
MANAGER
SUBBAND STATISTICS
QUANTIZER
& ENTROPY
CODING
HOST
I/O PORT
& FIFO
16/32
HOST
BIN WIDTH CONTROL
256K 3 16-BIT DRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADV611/ADV612
TABLE OF CONTENTS
GENERAL DESCRIPTION (Continued from page 1)
This data sheet gives an overview of the ADV611/ADV612’s
functionality and provides details on designing the part into a
system. The text of the data sheet is written for an audience with
a general knowledge of designing digital video systems. Where
appropriate, additional sources of reference material are noted
throughout the data sheet.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
COMPARING THE ADV6xx FAMILY VIDEO CODECS . . . . . 3
INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . 4
GENERAL THEORY OF OPERATION . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THE PROGRAMMABLE QUANTIZER . . . . . . . . . . . . . . . . . 8
THE RUN LENGTH CODER AND HUFFMAN CODER . . . . . 9
Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ADV611/ADV612 REGISTER DESCRIPTIONS . . . . . . . . . . 11
VIDEO AREA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 18
Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Video Formats–CCIR-656 . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Compressed Data-Stream Definition . . . . . . . . . . . . . . . . . . . 24
APPLYING THE ADV611/ADV612 . . . . . . . . . . . . . . . . . . . . 30
Using the ADV611/ADV612 in Computer Applications . . . . . . 30
Using the ADV611/ADV612 in Stand-Alone Applications . . . . 31
Connecting the ADV611/ADV612 to Popular Video
Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GETTING THE MOST OUT OF ADV611/ADV612 . . . . . . . 32
How Much Compression Can Be Expected . . . . . . . . . . . . . . 32
Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Software Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Field Rate Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Edge Enhancement and Detection . . . . . . . . . . . . . . . . . . . . . 32
Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ADV611/ADV612 SPECIFICATIONS . . . . . . . . . . . . . . . . . . 33
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Clock Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CCIR-656 Video Format Timing . . . . . . . . . . . . . . . . . . . . . . 35
Multiplexed Philips Video Timing . . . . . . . . . . . . . . . . . . . . . 37
Host Interface (Indirect Address, Indirect Register Data,
and Interrupt Mask/Status) Register Timing . . . . . . . . . . . 40
Host Interface (Compressed Data) Register Timing . . . . . . . 42
ADV611/ADV612 LQFP PINOUTS . . . . . . . . . . . . . . . . . . . . 44
ADV611/ADV612 PIN CONFIGURATION . . . . . . . . . . . . . . 45
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VIDEO INTERFACE
DIGITAL VIDEO IN
(ENCODE)
DIGITAL VIDEO
OUT (DECODE)
HOST INTERFACE
ADV611/
ADV612
VIDEO CODEC
CCTV DIGITAL
COMPRESSED
VIDEO OUT
(ENCODE)
STATUS AND CONTROL
COMPRESSED VIDEO
IN (DECODE)
Figure 2. Functional Block Diagram
The ADV611/ADV612 adheres to international standard
CCIR-601 for studio quality digital video. The codec also supports a range of field sizes and rates providing high performance
in computer, PAL, NTSC, or still image environments. The
ADV611/ADV612 is designed only for real-time interlaced
video; full frames of video are formed and processed as two
independent fields of data. The ADV611/ADV612 supports the
field rates and sizes in Table I. Note that the maximum active
field size is 720 by 288. The maximum pixel rate is 13.50 MHz.
The ADV611/ADV612 has a generic 16-/32-bit host interface
that includes a 512-position, 32-bit wide FIFO for compressed
video. With additional external hardware, the ADV611/ADV612’s
host interface is suitable (when interfaced to other devices) for
moving compressed video over PCI, ISA, SCSI, SONET, 10 Base
T, ARCnet, HDSL, ADSL and a broad range of digital interfaces. For a full description of the Host Interface, see the Host
Interface section.
The compressed data rate is determined by the input data rate
and the selected compression ratio. The ADV611/ADV612 can
achieve a near constant compressed bit rate by using the current
field statistics in the off-chip bin width calculator on the external DSP or Host. The process of calculating bin widths on a
DSP or Host can be “adaptive,” optimizing the compressed bit
rate in real time. This feature provides a near constant bit rate
out of the host interface in spite of scene changes or other types
of source material changes that would otherwise create bit rate
burst conditions. For more information on the quantizer, see
the Programmable Quantizer section.
The ADV611/ADV612 typically yields visually loss-less compression on natural images at a 4:1 compression ratio. For more
information on compression ratios, see the Getting the Most
Out of the ADV611/ADV612 section. Desired image quality
levels can vary widely in different applications, so it is advisable
to evaluate image quality of known source material at different
compression ratios to find the best compression range for the
application. The subband coding architecture of the ADV611/
ADV612 provides a number of options to stretch compression
performance. These options are outlined in the Applying the
ADV611/ADV612 section.
Table I. ADV611/ADV612 Field Rates and Sizes
Standard
Name
Active
Region
Horizontal
Active
Region
Vertical1
Total
Region
Horizontal
Total
Region
Vertical
Field Rate
(Hz)
Pixel Rate
(MHz)2
CCIR-601/525
CCIR-601/625
720
720
243
288
858
864
262.5
312.5
59.94
50.00
13.50
13.50
NOTES
1
The maximum active field size is 720 by 288.
2
The maximum pixel rate is 13.5 MHz.
–2–
REV. 0
ADV611/ADV612
Original Video Image
Image after compression/decompression shown
with different box size and position
PROGRAMMABLE
QUALITY BOX
VARIABLE CONTRAST
BACKGROUND
Figure 3.
The ADV611/ADV612 are real-time compression integrated
circuits designed for remote video surveillance or closed circuit
television (CCTV) applications. The most important feature of
these two devices is the “Quality Box.” With this feature the
user can define a box of any size and location within each field
of video that will be compressed at full contrast while the remainder outside the box, or background of the image, is compressed at a lower level of contrast. The background contrast
level is controlled by the user. The lower the contrast level, the
more the image will be compressed. The objective in a given
application is to adjust the background contrast to a level that
ensures both a recognizable and useful background as well as
the highest possible compression. Figure 3 shows how this quality box appears in final video.
The ADV611/ADV612 is housed in a plastic LQFP package
suitable for cost-sensitive commercial applications.
COMPARING THE ADV6xx FAMILY VIDEO CODECS
The ADV6xx video codecs support a range of interface, package, and compression features. Table II compares these codecs:
Table II. Differences Between the ADV601, ADV601LC, ADV611 and ADV612
Bits per Component
DSP Serial Port
Package
Pin Assignments
Temperature Range
θJA
θJC
Field Rate Reduction
Stall Mode
Field Truncation
Field Size Register
Field Bit Polarity Control
Evaluation Board
Target Applications
REV. 0
ADV601
ADV601LC
ADV611
ADV612
10
Yes
160 PQFP
Unique
0°C to +70°C
31°C/W
7.5°C/W
Software
No
No
No
No
VideoLab
Professional
8
No
120 LQFP
Unique
0°C to +70°C
35°C/W
5°C/W
Software
No
No
No
No
VideoPipe
Consumer
8
No
120 LQFP
98% Similar to ADV601LC
0°C to +70°C
35°C/W
5°C/W
Hardware
Yes
Yes
Yes
Yes
CCTVPIPE
CCTV
8
No
120 LQFP
98% Similar to ADV601LC
–25°C to +85°C
35°C/W
5°C/W
Hardware
Yes
Yes
Yes
Yes
CCTVPIPE
Industrial CCTV
–3–
ADV611/ADV612
INTERNAL ARCHITECTURE
Programmable Quantizer
The ADV611/ADV612 is composed of eight blocks. Three of
these blocks are interface blocks and five are processing blocks.
The interface blocks are the Digital Video I/O Port, the Host
I/O Port and the external DRAM manager. The processing
blocks are the Wavelet Kernel, the On-Chip Transform Buffer,
the Programmable Quantizer, the Run Length Coder and the
Huffman Coder.
Quantizes wavelet coefficients. Quantize controls are calculated
by the external DSP or host processor during encode operations
and de-quantize controls are extracted from the compressed
bitstream during decode. Each quantizer Bin Width is computed by the BW calculator software to maintain a constant
compressed bit rate or constant quality bit rate. A Bin Width is
a per-block parameter the quantizer uses when determining the
number of bits to allocate to each block (subband).
Digital Video I/O Port
Provides a real-time uncompressed video interface to support a
broad range of component digital video formats, including “D1.”
Quality Box
The quality box is defined using the Video Area Registers that
are described in the Registers Descriptions section. The background contrast is controlled using Background Contrast Registers that are defined later in this document. It is possible to
control both parameters on a per-field basis during Encode
Mode. This enables the quality box to either move slowly across
the image or to instantaneously jump from one location to the
next.
Host I/O Port and FIFO
Carries control, status, and compressed video to and from the
host processor. A 512 position by 32-bit FIFO buffers the compressed video stream between the host and the Huffman Coder.
Hardware Field Rate Reduction
In CCTV applications it is often desirable to reduce the field
rate to achieve the highest possible compression. The ADV611/
ADV612 have special hardware to permit this function. It is
possible to set a register on the ADV611/ADV612 during encode mode that will automatically reduce the field rate. This is a
5-bit register that allows up to 31 fields to be “skipped.”
Run Length Coder
Performs run length coding on zero data and models nonzero
data, encoding or decoding for more efficient Huffman coding.
This data coding is optimized across the subbands and varies
depending on the block being coded.
Stall Mode
Huffman Coder
It is possible to stall or halt the ADV611/ADV612 at any time
during Encode Mode. This allows the user to feed uncompressed
video data to these parts and to stop indefinitely between fields
or even between pixels. This feature is useful when compressing
video that is not coming into the ADV611/ADV612 at sustained
VCLK rates. Stall Mode is enabled by asserting the Stall pin at
any time during encode. Stall mode is enabled on the next clock
cycle after the pin is asserted.
Performs Huffman coder and decoder functions on quantized
run-length coded coefficient values. The Huffman coder/decoder uses three ROM-coded Huffman tables that provide excellent performance for wavelet transformed video.
Field Truncation
It is possible to set a hard upper limit to the field size of each
field during Encode Mode. The Huffman Coder is able to detect if the field size exceeds a preset threshold and then causes
the remaining Mallat block data to be zeroed out, therefore,
truncating the field’s data. The bitstream is truncated in such a
way that all end-of-field markers are inserted. This means that
the compressed bitstream can still be decompressed by any
hardware or software ADV6xx decoder. The only penalty is the
loss of Mallat blocks which, depending on how many are lost,
will degrade the image quality of the truncated field.
Field Size Reporting
The ADV611/ADV612 have a read-only register that allows the
user to read the field size of the most recently compressed field.
This feature is useful in the feedback loop of a precise bit rate
controller. The data is valid after LCODE (unless an entire
compressed field resides in the internal FIFO).
DRAM Manager
Performs all tasks related to writing, reading and refreshing the
external DRAM. The external host buffer DRAM is used for
reordering and buffering quantizer input and output values.
GENERAL THEORY OF OPERATION
The ADV611/ADV612 processor’s compression algorithm is
based on the bi-orthogonal (7, 9) wavelet transform, and implements field independent subband coding. Subband coders transform two-dimensional spatial video data into spatial frequency
filtered subbands. The quantization and entropy encoding processes provide the ADV611/ADV612’s data compression.
Wavelet Kernel (Filters, Decimator, and Interpolator)
Gathers statistics on a per-field basis and includes a block of
filters, interpolators and decimators. The kernel calculates forward and backward bi-orthogonal, two-dimensional, separable
wavelet transforms on horizontal scanned video data. This block
uses the internal transform buffer when performing wavelet
transforms calculated on an entire image’s data and so eliminates any need for extremely fast external memories in an
ADV611/ADV612-based design.
The wavelet theory, on which the ADV611/ADV612 is based, is
a new mathematical apparatus first explicitly introduced by
Morlet and Grossman in their works on geophysics during the
mid 80s. This theory became very popular in theoretical physics
and applied math. The late 80s and 90s have seen a dramatic
growth in wavelet applications such as signal and image processing. For more on wavelet theory by Morlet and Grossman, see
Decomposition of Hardy Functions into Square Integrable Wavelets
of Constant Shape (journal citation listed in References section).
On-Chip Transform Buffer
Provides an internal set of SRAM for use by the wavelet transform kernel. Its function is to provide enough delay line storage
to support calculation of separable two dimensional wavelet
transforms for horizontally scanned images.
–4–
REV. 0
ADV611/ADV612
ENCODE
PATH
WAVELET
KERNEL
FILTER BANK
DECODE
PATH
ADAPTIVE
QUANTIZER
RUN LENGTH
CODER &
HUFFMAN
CODER
image processing, scaling, and a number of other system features possible with little or no computational overhead.
COMPRESSED
DATA
The resultant filtered image is made up of components of the
original image as is shown in Figure 5 (a modified Mallat Tree).
Note that Figure 5 shows how a component of video would be
filtered, but in multiple component video, luminance and color
components are filtered separately. In Figure 6 and Figure 7 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compression has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.
Figure 4. Encode and Decode Paths
References
For more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the following reference texts useful. A reference text for general digital
video principles is:
Jack, K., Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4
Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest performance from the ADV611/ADV612. Consider the following
points:
Three reference texts for wavelet transform background information are:
Vetterli, M., Kovacevic, J., Wavelets And Subband Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8
• The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).
Benedetto, J., Frazier, M., Wavelets: Mathematics And Applications (CRC Press, 1994) ISBN 0-8493-8271-8
Grossman, A., Morlet, J., Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape, Siam. J. Math.
Anal., Vol. 15, No. 4, pp 723-736, 1984
• The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.
• The human visual system is less sensitive to higher frequency
blocks than low ones.
THE WAVELET KERNEL
This block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 8
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broadband nature of images than the sinusoidal waves used in Discrete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).
• Attenuation of the selected blocks in luminance or color components results in control over sharpness, brightness, contrast
and saturation.
• High quality filtered/decimated images can be extracted/created
without computational overhead.
Through leverage of these key points, the ADV611/ADV612
not only compresses video, but offers a host of application
features. Please see the Applying the ADV611/ADV612 section
for details on getting the most out of the ADV611/ADV612’s
subband coding architecture in different applications.
An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image subband data also makes
N
M
L
K
I
F
J
H
C
G
E
A
D
B
BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
Figure 5. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)
REV. 0
–5–
ADV611/ADV612
Figure 6. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts)
Figure 7. Modified Mallat Diagram of Image
–6–
REV. 0
ADV611/ADV612
LUMINANCE AND
COLOR
COMPONENTS (EACH
SEPARATELY)
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
BLOCK
#
Y 2 INDICATES DECIMATE BY TWO IN Y
STAGE 1
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
B
BLOCK
C
BLOCK
D
BLOCK
A
X 2 INDICATES DECIMATE BY TWO IN X
INDICATES
CORRESPONDING
BLOCK LETTER ON
MALLAT DIAGRAM
STAGE 2
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
E
BLOCK
F
BLOCK
G
STAGE 3
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
H
BLOCK
I
BLOCK
J
STAGE 4
HIGH
PASS IN
X
LOW
PASS IN
X
X 2
X 2
HIGH
PASS IN
Y
LOW
PASS IN
Y
HIGH
PASS IN
Y
LOW
PASS IN
Y
Y 2
Y 2
Y 2
Y 2
BLOCK
K
BLOCK
L
BLOCK
M
BLOCK
N
STAGE 5
Figure 8. Wavelet Filter Tree Structure
REV. 0
–7–
ADV611/ADV612
THE PROGRAMMABLE QUANTIZER
This block quantizes the filtered image based on the response
profile of the human visual system. In general, the human eye
cannot resolve high frequencies in images to the same level of
accuracy as lower frequencies. Through intelligent “quantization” of information contained within the filtered image, the
ADV611/ADV612 achieves compression without compromising
the visual quality of the image. Figure 9 shows the encode and
decode data formats used by the quantizer.
QUANTIZER - ENCODE MODE
9.7
WAVELET
DATA
SIGNED SIGNED
UNSIGNED
15.17 DATA
TRNC
15.0 BIN
NUMBER
SAT
9.7
WAVELET
DATA
0.5
6.10
1/BW
1/BW
QUANTIZER - DECODE MODE
Figure 10 shows how a typical quantization pattern applies over
Mallat block data. The high frequency blocks receive much
larger quantization (appear darker) than the low frequency
blocks (appear lighter). Looking at this figure, one sees some key
point concerning quantization: (1) quantization relates directly
to frequency in Mallat block data and (2) levels of quantization
range widely from high to low frequency block. (Note that the
fill is based on a log formula.) The relation between actual
ADV611/ADV612 bin width factors and the Mallat block fill
pattern in Figure 10 appears in Table III.
15.0 BIN
NUMBER
23.8
DE-QUANTIZED
WAVELET DATA
SIGNED SIGNED
UNSIGNED
8.8 BW
BW
Figure 9. Programmable Quantizer Data Flow
Y COMPONENT
39 33
36 30
24
15
27
21
6
12
18
0
9
40 34
37 31
3
Cb COMPONENT
25
16
28
22
7
19
13
1
10
4
41 35
38 32
Cr COMPONENT
26
17
29
23
8
20
14
2
11
5
QUANTIZATION OF MALLAT BLOCKS
LOW
HIGH
Figure 10. Typical Quantization of Mallat Data Blocks (Graphed)
–8–
REV. 0
ADV611/ADV612
Table III. Typical Quantization of Mallat Data Block Data 1
Mallat
Blocks
Bin Width
Factors
Reciprocal Bin
Width Factors
39
40
41
36
33
30
34
35
37
38
31
32
27
24
21
25
26
28
29
22
23
5
18
12
20
19
17
16
14
13
6
9
3
11
10
8
7
5
4
0
2
1
0x007F
0x009A
0x009A
0x00BE
0x00BE
0x00E4
0x00E6
0x00E6
0x00E6
0x00E6
0x0114
0x0114
0x0281
0x0281
0x0301
0x0306
0x0306
0x0306
0x0306
0x03A1
0x03A1
0x0A16
0x0A16
0x0C1A
0x0C2E
0x0C2E
0x0C2E
0x0C2E
0x0E9D
0x0E9D
0x1DDC
0x1DDC
0x23D5
0x2410
0x2410
0x2410
0x2410
0x2B46
0x2B46
0xA417
0xC62B
0xC62B
0x0810
0x06a6
0x06a6
0x0564
0x0564
0x047e
0x0474
0x0474
0x0474
0x0474
0x03b6
0x03b6
0x0199
0x0199
0x0155
0x0153
0x0153
0x0153
0x0153
0x011a
0x011a
0x0066
0x0066
0x0055
0x0054
0x0054
0x0054
0x0054
0x0046
0x0046
0x0022
0x0022
0x001d
0x001c
0x001c
0x001c
0x001c
0x0018
0x0018
0x0006
0x0005
0x0005
THE RUN LENGTH CODER AND HUFFMAN CODER
This block contains two types of entropy coders that achieve
mathematically loss-less compression: run-length and Huffman.
The run-length coder looks for long strings of zeros and replaces
them with short hand symbols. Table IV illustrates an example
of how compression is possible.
The Huffman coder is a digital compressor/decompressor that
can be used for compressing any type of digital data. Essentially,
an ideal Huffman coder creates a table of the most commonly
occurring code sequences (typically zero and small values near
zero) and then replaces those codes with some shorthand. The
ADV611/ADV612 employs three fixed Huffman tables; it does
not create tables.
The filters and the quantizer increase the number of zeros and
strings of zeros, which improves the performance of the entropy
coders. The higher the selected compression ratio, the more
zeros and small value sequences the quantizer needs to generate.
The transformed image in Figure 7 shows that the filter bank
concentrates zeros and small values in the higher frequency
blocks.
Encoding vs. Decoding
The decoding of compressed video follows the exact path as
encoding but in reverse order. There is no need to calculate bin
widths during decode because the bin width is stored in the
compressed image during encode.
PROGRAMMER’S MODEL
A host device configures the ADV611/ADV612 using the Host
I/O Port. The host reads from status registers and writes to
control registers through the Host I/O Port.
Table V. Register Description Conventions
Register Name
Register Type (Indirect or Direct, Read or Write) and Address
Register Functional Description Text
Bit [#] or
Bit or Bit Field Name and Usage Description
Bit Range
[High:Low]
0 Action or Indication When Bit Is Cleared (Equals 0)
1 Action or Indication When Bit Is Set (Equals 1)
NOTE
1
The Mallat block numbers, Bin Width factors, and Reciprocal Bin Width
factors in Table III correspond to the shading per-cent fill) of Mallat blocks in
Figure 10.
Table IV. Uncompressed Versus Compressed Data Using Run-Length Coding
0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)
57 Zeros (Compressed)
REV. 0
–9–
ADV611/ADV612
DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS
REGISTER
ADDRESS
BYTE 3
BYTE 2
0x0
RESERVED
0x4
RESERVED
BYTE 0
INDIRECT REGISTER ADDRESS
INDIRECT REGISTER DATA
RESERVED
INTERRUPT MASK / STATUS
MODE CONTROL*
0x0
0x1
RESET
VALUE
UNDEF
UNDEF
UNDEF
COMPRESSED DATA
0x8
0xC
BYTE 1
FIFO CONTROL
RESERVED
0x00
0x0980
0x88
INDIRECT (INTERNALLY INDEXED) REGISTERS
{ACCESS THESE REGISTERS THROUGH THE
INDIRECT REGISTER ADDRESS AND
INDIRECT REGISTER DATA REGISTERS}
*NOTE:
YOU MUST WRITE 0X0880 TO THE MODE
CONTROL REGISTER ON CHIP RESET TO
SELECT THE CORRECT PIXEL MODE
0x2
HSTART
0x000
0x3
HEND
0x3FF
0x4
VSTART
0x000
0x5
VEND
0x3FF
0x6
RESERVED
UNDEF
0x7 – 0x7F
RESERVED
UNDEF
0x8
COMPRESSED FIELD SIZE LIMIT
0xFFFF
0x9
MODE CONTROL REGISTER 2
0x80 – 0xA9
0x7
SUM OF SQUARES [0 – 41]
UNDEF
0xAA
SUM OF LUMA
UNDEF
0xAB
SUM OF Cb
UNDEF
0xAC
SUM OF Cr
UNDEF
0xAD
MIN LUMA
UNDEF
0xAE
MAX LUMA
UNDEF
0xAF
MIN Cb
UNDEF
0xB0
MAX Cb
UNDEF
0xB1
MIN Cr
UNDEF
0xB2
MAX Cr
UNDEF
0xB3
COMPRESSED FIELD SIZE HI
0x0
0xB4
COMPRESSED FIELD SIZE LO
0x0
0x100
RBW0
UNDEF
0x101
BW0
UNDEF
0x152
RBW41
UNDEF
0x153
BW41
UNDEF
Figure 11. Map of ADV611/ADV612 Direct and Indirect Registers
–10–
REV. 0
ADV611/ADV612
ADV611/ADV612 REGISTER DESCRIPTIONS
Indirect Address Register
Direct (Write) Register Byte Offset 0x00.
This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16 bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.
[15:0]
Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through
the indirect data register (undefined at reset).
[31:16] Reserved (undefined read/write zero)
Indirect Register Data
Direct (Read/Write) Register Byte Offset 0x04
This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register.
[15:0]
Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.
[31:16] Reserved (undefined read/write zero)
Compressed Data Register
Direct (Read/Write) Register Byte Offset 0x08
This register holds a 32-bit sequence from the compressed video bitstream. This register is buffered by a 512 position, 32-bit FIFO.
For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a
description of the data sequence, see the Compressed Data Stream Definition section.
[31:0]
Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.
Interrupt Mask / Status Register
Direct (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s HIRQ pin. With the
seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR), select the conditions that are ORed together to determine the output of the HIRQ pin.
Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
condition coming true, they cannot be read or tested for stable level true conditions multiple times.
The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.
[0]
CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:
0
1
[1]
Statistics Ready, STATSR. This read only status bit indicates the following:
0
1
[2]
REV. 0
No Last Code condition, reset value (LCODE pin LO)
Next read retrieves last word for field in FIFO (LCODE pin HI)
FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:
0
1
[4]
No Statistics Ready condition, reset value (STATS_R pin LO)
Statistics Ready for BW calculator (STATS_R pin HI)
Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be
retrieved from the FIFO on the next read from the host bus.
0
1
[3]
No CCIR-656 Error condition, reset value
Unrecoverable error in CCIR-656 data stream (missing sync codes)
No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)
FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)
FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV611/ADV612’s
compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted
until MERR indicates that the DRAM has also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0
No FIFO Error condition, reset value (FIFO_ERR pin LO)
1
FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
–11–
ADV611/ADV612
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In
decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP
is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely be performed.
This status bit indicates the following:
0
No FIFO Stop condition, reset value (FIFO_STP pin LO)
1
FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit
errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention.
0
No memory error condition, reset value
1
Memory error
Reserved (always read/write zero)
Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0
Disable CCIR-656 data error interrupt, reset value
1
Enable interrupt on error in CCIR-656 data
Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0
Disable Statistics Ready interrupt, reset value
1
Enable interrupt on Statistics Ready
Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0
Disable Last Code Read interrupt, reset value
1
Enable interrupt on Last Code Read from FIFO
Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0
Disable FIFO Service Request interrupt, reset value
1
Enable interrupt on FIFO Service Request
Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0
Disable FIFO Stop interrupt, reset value
1
Enable interrupt on FIFO Stop
Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0
Disable FIFO Error interrupt, reset value
1
Enable interrupt on FIFO Error
Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0
Disable memory error interrupt, reset value
1
Enable interrupt on memory error
Reserved (always read/write zero)
Mode Control Register
Indirect (Read/Write) Register Index 0x00
This register holds configuration data for the ADV611/ADV612’s video interface format and controls several other video interface
features. For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0]
Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0 CCIR-656, reset value
0x2 MLTPX (Philips)
[4]
VCLK Output Divided by two, VCLK2. This bit controls the following:
0
Do not divide VCLK output (VCLKO = VCLK), reset value
1
Divide VCLK output by two (VCLKO = VCLK/2)
[5]
[6]
Video Interface Master/Slave Mode Select, M/S. This bit selects the following:
0
Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value
1
Master mode video interface (ADV611/ADV612 controls video timing, HSYNC-VSYNC are outputs)
Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:
0
525 mode video interface, reset value
1
625 mode video interface
–12–
REV. 0
ADV611/ADV612
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:
0
Decode mode video interface (compressed-to-raw)
1
Encode mode video interface (raw-to-compressed), reset value
Reserved (always write zero)
Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:
0
Bipolar color component mode video interface, reset value
1
Unipolar color component mode video interface
Reserved (always write zero)
Video Interface Software Reset, SWR. This bit has the following effects on ADV611/ADV612 operations:
0
Normal operation
1
Software Reset. This bit is set on hardware reset and must be cleared before the ADV611/ADV612 can begin processing.
(reset value)
When this bit is set during encode, the ADV611/ADV612 completes processing the current field then suspends operation
until the SWR bit is cleared. When this bit is set during decode, the ADV611/ADV612 suspends operation immediately and
does not resume operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode
register is changed.
HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV611/ADV612 operations:
0
HSYNC is HI during blanking, reset value
1
HSYNC is LO during blanking (HI during active)
HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV611/ADV612 operations:
0
HIRQ is active LO, reset value
1
HIRQ is active HI
Quality Box Enable, QBE. This bit has the following effect on ADV611/ADV612 operations:
0
Video area registers (HSTART, HEND, VSTART, VEND). Crop video area, setting cropped area to all 0
quantizations (ADV601 mode), reset value
1
Video area registers (HSTART, HEND, VSTART, VEND). Select Quality Box. Quantization of the area outside
the box is selected with the background Contrast Control register. See the video area registers for more information
on the Quality Box.
Video Stall Enable, VSE. This bit has the following effect on ADV611/ADV612 operations:
0
Video Stall disabled (ADV601 mode), reset value
1
Video Stall enabled.
FIFO Control Register
Indirect (Read/Write) Register Index 0x01
This register holds the service-request settings for the ADV611/ADV612’s host interface FIFO, causing interrupts for the “nearly full” and
“nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by 32
(decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV611/ADV612
uses these settings to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin).
[3:0]
Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condition that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is
512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
ESL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI during encode)
0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)
1000 FIFO is 1/2 full, reset value
1111 FIFO has only 32 positions empty (480 positions filled)
[7:4] Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a
condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO
is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the
register and their meaning.
DSL Interrupt When . . .
0000 Disables service requests (FIFO_SRQ never goes HI)
0001 FIFO has only 32 positions filled (480 positions empty)
1000 FIFO is 1/2 empty, reset value
1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)
[15:8] Reserved (always write zero)
REV. 0
–13–
ADV611/ADV612
VIDEO AREA REGISTERS
When the quality box is disabled (Mode Control register, Bit 14 = 0), the area defined by the HSTART, HEND, VSTART and
VEND registers is the active area that the wavelet kernel processes. Video data outside the active video area is set to minimum luminance and zero chrominance (black) by the ADV611/ADV612. These registers allow cropping of the input video during compression
(encode only), but do not change the image size. Figure 12 shows how the video area registers work together.
Some comments on how these registers work are as follows:
• The vertical numbers include the blanking areas of the video.
HSTART
Specifically, a VSTART value of 21 will include the first line
of active video, and the first pixel in a line corresponds to a
value HSTART of 0 (for NTSC regular).
HEND
0, 0
ZERO
ZERO
ZERO
ZERO
ACTIVE VIDEO AREA
ZERO
ZERO
ZERO
ZERO
VSTART
Note that the vertical coordinates start with 1, whereas the
horizontal coordinates start with 0.
• The default cropping mode is set for the entire frame. Specifically, Field 2 starts at a VSTART value of 283 (for NTSC
regular).
When the quality box is enabled (Mode Control register, Bit 14
= 1), the area defined by the HSTART, HEND, VSTART and
VEND registers is the quality box area, and the rest of the video
area is attenuated according to the value in the background
Contrast Control register (Indirect Register Index 0x9). In this
mode, the range of values for VSTART and VEND is 1–243 for
NTSC and 1–288 for PAL. Also note that VSTART and VEND
do not need to be updated for each field in this mode.
VEND
X, Y
MAX FOR SELECTED VIDEO MODE
Figure 12. Video Area and Video Area Registers
HSTART Register
Indirect (Write Only) Register Index 0x02
This register holds the setting for the horizontal start of the ADV611/ADV612’s active video area or quality box. The value in this
register is usually set to zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST.
[9:0]
Horizontal Start, HST[9:0]. 10-bit value defining the start of the active video region. (0 at reset)
[15:10] Reserved (always write zero)
HEND Register
Indirect (Write Only) Register Index 0x03
This register holds the setting for the horizontal end of the ADV611/ADV612’s active video area or quality box. If the value is larger
than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for HEND.
[9:0]
Horizontal End, HEN[9:0]. 10-bit value defining the end of the active video region. (0x3FF at reset this value is larger
than the max size of the largest video mode)
[15:10] Reserved (always write zero)
VSTART Register
Indirect (Write Only) Register Index 0x04
This register holds the setting for the vertical start of the ADV611/ADV612’s active video area or quality box. The value in this
register is usually set to zero unless you want to crop the active video.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field unless the quality box is enabled. Perform this updating as
part of the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of
which field is being processed next.
[9:0]
Vertical Start, VST[9:0]. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0 at reset)
[15:10] Reserved (always write zero)
VEND Register
Indirect (Write Only) Register Index 0x05
This register holds the setting for the vertical end of the ADV611/ADV612’s active video area or quality box. If the value is larger
than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for VEND.
–14–
REV. 0
ADV611/ADV612
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for each
field. The VSTART and VEND contents must be updated on each field, unless the quality box is enabled. Perform this updating as part of
the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of which
field is being processed next.
[9:0]
Vertical End, VEN[9:0]. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0x3FF at reset—this value is larger than the max size of the largest video mode)
[15:10] Reserved (always write zero)
Compressed Field Size Limit
Indirect (Read/Write) Register Index 0x8
[15:0] The DWORD Max Count 16 MSBs register selects the maximum number of double (32-bit) words for an encoded field.
When the value in the DWORD count registers reaches the DWORD Max Count, the Quantizer zeroes out all remaining
samples in the field. To enable the DWORD Max Counts operation, you must set (= 1) Bit 4 in Indirect register 0x7; all
other bits in Indirect register 0x7 are reserved ( = 0). Note that the 4 LSBs of the max count are 0000, so the max count is
selectable in 16-word increments. Contains bits [19:4] of the DWORD max count, reset to 0xffff
Mode Control #2
Indirect (Read/Write) Register Index 0x9
[2:0]
These bits control the contrast/attenuation of the area outside the quality box when the quality box is enabled. The
following settings control background contrast.
Setting
Contrast/Attenuation
000
Illegal
001
6 dB
010
12 dB
011
18 dB
100
24 dB
101
30 dB
[3]
Field Polarity Bit. This bit reverses the polarity of the FIELD pin. This bit operates as follows:
0
Normal Field Polarity (ADV601 Mode), reset value
1
Reverse Field Polarity. Polarity is opposite to the polarity in the FIELD pin timing diagrams.
[8:4]
Field Rate Reduction. To reduce this compressed data rate, the ADV601 can discard some video fields. Set field rate
reduction to zero to capture all fields, one to discard every other field, two to discard two fields out of three and so on.
Maximum possible field rate reduction send only one field out of 32.
[9]
Reserved, must set to 1. This bit must be set to take advantage of MERR detection logic. Resets to 0.
[10]
Reserved, resets to 1.
[11]
Ignore Field bit in decode, setting this bit eliminates black fields if field bits repeat from field to field in decode mode,
resets to 0.
Sum of Squares [0–41] Registers
Indirect (Read Only) Register Index 0x080 through 0x0A9
The Sum of Squares [0–41] registers hold values that correspond to the summation of squared values in corresponding Mallat blocks
[0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV611/ADV612; using these values (with the
Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV611/ADV612
indicates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the
statistics at any time. The Host reads these values through the Host Interface.
[15:0] Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square
values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for
large blocks. The 16-bit codes have the following precision:
Blocks Precision Sum of Squares Precision Description
0–2
48.–32
48.-bits wide, left shift code by 32-bits, and zero fill
3–11
46.–30
46.-bits wide, left shift code by 30-bits, and zero fill
12–20 44.–28
44.-bits wide, left shift code by 28-bits, and zero fill
21–29 42.–26
42.-bits wide, left shift code by 26-bits, and zero fill
30–41 40.–24
40.-bits wide, left shift code by 24-bits, and zero fill
If the Sum of Squares code were 0x0025 for block 10, the actual value would be 0x000940000000; if using that same
code, 0x0025, for block 30, the actual value would be 0x0025000000.
[31:0] Reserved (always read zero)
REV. 0
–15–
ADV611/ADV612
Sum of Luma Value Register
Indirect (Read Only) Register Index 0x0AA
The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The
Host reads these values through the Host Interface.
[15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cb Value Register
Indirect (Read Only) Register Index 0x0AB
The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host
reads these values through the Host Interface.
[15:0] Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cr Value Register
Indirect (Read Only) Register Index 0x0AC
The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host
reads these values through the Host Interface.
[15:0] Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
MIN Luma Value Register
Indirect (Read Only) Register Index 0x0AD
The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface.
[15:0] Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
MAX Luma Value Register
Indirect (Read Only) Register Index 0x0AE
The MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface.
[15:0]
Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MIN Cb Value Register
Indirect (Read Only) Register Index 0x0AF
The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface.
[15:0]
Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MAX Cb Value Register
Indirect (Read Only) Register Index 0x0B0
The MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface.
[15:0]
Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
–16–
REV. 0
ADV611/ADV612
MIN Cr Value Register
Indirect (Read Only) Register Index 0x0B1
The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
MAX Cr Value Register
Indirect (Read Only) Register Index 0x0B2
The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)
[31:0]
Reserved (always read zero)
Compressed Field Size [HI]
Indirect (Read Only) Register Index 0x83
[15:0]
The DWORD Count registers hold the count of double (32-bit) words contained in the previously encoded field. This
count is useful for bit rate control algorithms that use a servo loop, which is locked to the expected number of double words
in the field. The registers are double buffered to ensure that the count remains constant while the next field's count accumulates. Contains bits [19:4] of the DWORD count, reset is 0.
Compressed Field Size [LO]
Indirect (Read Only) Register Index 0xB4
[3:0]
Contains bits [3:0] of the DWORD count, reset is 0. For more information, see the DWORD Count 16 MSB Register
description.
Bin Width and Reciprocal Bin Width Registers
Indirect (Read/Write) Register Index 0x0100-0x0153
The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and
MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes these
values through the Host Interface.
These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values as
indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined
at reset).
[15:0]
Bin Width Values, BW[15:0]
[15:0]
Reciprocal Bin Width Values, RBW[15:0]
REV. 0
–17–
ADV611/ADV612
PIN FUNCTION DESCRIPTIONS
Clock Pins
Name
Pins
I/O
Description
VCLK/XTAL
2
I
VCLKO
1
O
A single clock (VCLK) or crystal input (across VCLK and XTAL). An acceptable
50% duty cycle clock signal is 27 MHz (CCIR-601 NTSC/PAL).
If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If
using a clock input, use a TTL level input, 50% duty cycle clock with 1 ns (or less)
jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are
acceptable; up to 5% frequency variation in 0.5 sec.
VCLK Output or VCLK Output divided by two. Select function using Mode
Control register.
Name
Pins
I/O
Description
VSYNC
1
I or O
Vertical Sync or Vertical Blank. This pin can be either an output (Master Mode) or
an input (Slave Mode). The pin operates as follows:
Video Interface Pins
HSYNC
1
I or O
FIELD
1
I or O
ENC
1
O
VDATA[7:0]
8
I/O
STALL
1
I
• Output (Master) HI during inactive lines of video and LO otherwise
• Input (Slave) a HI on this input indicates inactive lines of video
Horizontal Sync or Horizontal Blank. This pin can be either an output (Master
Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI during inactive portion of video line and LO otherwise
• Input (Slave) a HI on this input indicates inactive portion of video line
Note that the polarity of this signal is modified using the Mode Control register. For
detailed timing information, see the Video Interface section.
Field # or Frame Sync. Polarity of FIELD Pin can be reversed by setting Bit 3 in
Mode Control Register 2. The pin operates as follows:
• Output (Master) HI during Field1 lines of video and LO otherwise
• Input (Slave) a HI on this input indicates Field1 lines of video
Encode or Decode. This output pin indicates the coding mode of the ADV611/
ADV612 and operates as follows:
• LO Decode Mode (Video Interface is output)
• HI Encode Mode (Video Interface is input)
Note that this pin can be used to control bus enable pins for devices connected to
the ADV611/ADV612 Video Interface.
4:2:2 Video Data (8-bit digital component video data). These pins are inputs during
encode mode and outputs during decode mode. When outputs (decode) these pins
are compatible with 50 pF loads (rather than 30 pF as all other busses) to meet the
high performance and large number of typical loads on this bus.
The performance of these pins varies with the Video Interface Mode set in the
Mode Control register, see the Video Interface section of this data sheet for pin
assignments in each mode.
Note that the Mode Control register also sets whether the color component is
treated as either signed or unsigned.
Stall Mode. This pin stalls incoming video data driving encode.
–18–
REV. 0
ADV611/ADV612
DRAM Interface Pins
Name
Pins
I/O
Description
DDAT[15:0]
16
I/O
DADR[8:0]
9
O
RAS
CAS
WE
1
1
1
O
O
O
DRAM Data Bus. The ADV611/ADV612 uses these pins for 16-bit data read/
write operations to the external 256K × 16-bit DRAM. (The operation of the
DRAM interface is fully automatic and controlled by internal functionality
of the ADV611/ADV612.) These pins are compatible with 30 pF loads.
DRAM Address Bus. The ADV611/ADV612 uses these pins to form the multiplexed row/column address lines to the external DRAM. (The operation of the
DRAM interface is fully automatic and controlled by internal functionality
of the ADV611/ADV612.) These pins are compatible with 30 pF loads.
DRAM Row Address Strobe. This pin is compatible with 30 pF loads.
DRAM Column Address Strobe. This pin is compatible with 30 pF loads.
DRAM Write Enable. This pin is compatible with 30 pF loads.
Note that the ADV611/ADV612 does not have a DRAM OE pin. Tie the
DRAM’s OE pin to ground.
Name
Pins
I/O
Description
DATA[31:0]
32
I/O
ADR[1:0]
2
I
BE0–BE1
BE2–BE3
2
I
CS
1
I
WR
RD
1
1
I
I
Host Data Bus. These pins make up a 32-bit wide host data bus. The host
controls this asynchronous bus with the WR, RD, BE and CS pins to communicate with the ADV611/ADV612. These pins are compatible with 30 pF loads.
Host DWord Address Bus. These two address pins let you address the
ADV611/ADV612’s four directly addressable host interface registers. For an
illustration of how this addressing works, see the Control and Write Register
Map figure and Status and Read Register Map figure. The ADR bits permit
register addressing as follows:
ADR1 ADR0
DWord
Address Byte Address
0
0
0
0x00
0
1
1
0x04
1
0
2
0x08
1
1
3
0x0C
Host Word Enable pins. These two input pins select the words that the ADV611/
ADV612’s direct and indirect registers access through the Host Interface;
BE0–BE1 access the least significant word, and BE2–BE3 access the most
significant word. For a 32-bit interface only, tie these pins to ground, making
all words available.
Some important notes for 16-bit interfaces are as follows:
• When using these byte enable pins, the byte order is always the lowest byte
• to the higher bytes.
• The ADV611/ADV612 advances to the next 32-bit compressed data FIFO
• location after the BE2–BE3 pin is asserted then de-asserted (when accessing the
• Compressed Data register); so the FIFO location only advances when and if
• the host reads or writes the MSW of a FIFO location.
• The ADV611/ADV612 advances to the next 16-bit indirect register after the
• BE0–BE1 pin is asserted then de-asserted; so the register selection only advances
• when and if the host reads or writes the MSW of a 16-bit indirect register.
Host Chip Select. This pin operates as follows:
• LO Qualifies Host Interface control signals
• HI Three-states DATA[31:0] pins
Host Write. Host register writes occur on the rising edge of this signal.
Host Read. Host register reads occur on the low true level of this signal.
Host Interface Pins
REV. 0
–19–
ADV611/ADV612
Host Interface Pins (Continued)
Name
Pins
I/O
Description
ACK
1
O
FIFO_SRQ
1
O
STATS_R
1
O
LCODE
1
O
HIRQ
1
O
RESET
1
I
Host Acknowledge. The ADV611/ADV612 acknowledges completion of a Host
Interface access by asserting this pin. Most Host Interface accesses (other than the
compressed data register access) result in ACK being held high for at least one wait
cycle, but some exceptions to that rule are as follows:
• A full FIFO during decode operations causes the ADV611/ADV612 to de-assert
• (drive HI) the ACK pin, holding off further writes of compressed data until
• the FIFO has one available location.
• An empty FIFO during encode operations causes the ADV611/ADV612 to de• assert (drive HI) the ACK pin, holding off further reads until one location is filled.
FIFO Service Request. This pin is an active high signal indicating that the FIFO
needs to be serviced by the host. (see FIFO Control register). The state of this pin
also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a
Host interrupt (HIRQ pin) based on the state of the FIFO_SRQ pin. This pin operates as follows:
• LO No FIFO Service Request condition (FIFOSRQ bit LO)
• HI FIFO needs service is nearly full (encode) or nearly empty (decode)
During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes HI
when the FIFO is nearly full (see FIFO Control register).
During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because FIFO
is empty, and goes LO when the FIFO is filled beyond the nearly empty condition
(see FIFO Control register).
Statistics Ready. This pin indicates the Wavelet Statistics (contents of Sum of
Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and
are ready for the Bin Width calculator to read them from the host interface. The
frequency of this interrupt will be equal to the field rate. The state of this pin also
appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a
Host interrupt (HIRQ pin) based on the state of the STATS_R pin. This pin operates as follows:
• LO No Statistics Ready condition (STATSR bit LO)
• HI Statistics Ready for BW calculator (STATSR bit HI)
Last Compressed Data (for field). This bit indicates the last compressed data word
for field will be retrieved from the FIFO on the next read from the host bus. The
frequency of this interrupt is similar to the field rate, but varies depending on
compression and host response. The state of this pin also appears in the Interrupt
Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin)
based on the state of the LCODE pin. This pin operates as follows:
• LO No Last Code condition (LCODE bit LO)
• HI Last data word for field has been read from FIFO (LCODE bit HI)
Host Interrupt Request. This pin indicates an interrupt request to the Host. The
Interrupt Mask/Status register can select conditions for this interrupt based on any
or all of the following: FIFOSTP, FIFOSRQ, FIFOERR, LCODE, STATR or
CCIR-656 unrecoverable error. Note that the polarity of the HIRQ pin can be
modified using the Mode Control register.
ADV611/ADV612 Chip Reset. Asserting this pin returns all registers to reset state.
Note that the ADV611/ADV612 must be reset at least once after power-up with this
active low signal input. For more information on reset, see the SWR bit description.
Name
Pins
I/O
Description
GND
VDD
16
13
I
I
Ground
+5 V dc Digital Power
Power Supply Pins
–20–
REV. 0
ADV611/ADV612
• Master-Slave Control
This control determines whether the ADV611/ADV612 generates or receives the VSYNC, HSYNC, and FIELD signals.
In master mode, the ADV611/ADV612 generates these signals for external hardware synchronization. In slave mode, the
ADV611/ADV612 receives these signals. Note that some video
formats require the ADV611/ADV612 to operate in slave mode
only. This control is maintained by the host processor.
Video Interface
The ADV611/ADV612 video interface supports two types of
component digital video (D1) interfaces in both compression
(input) and decompression (output) modes. These digital video
interfaces include support for the Multiplexed Philips 4:2:2 and
CCIR-656/SMPTE125M—international standard.
Video interface master and slave modes allow for the generation or
receiving of synchronization and blanking signals. Definitions for
the different formats can be found later in this section. For recommended connections to popular video decoders and encoders, see
the Connecting the ADV611/ADV612 to Popular Video Decoders
and Encoders section. A complete list of supported video interfaces
and sampling rates is included in Table VI.
• 525-625 (NTSC-PAL) Control
This control determines whether the ADV611/ADV612 is
operating on 525/NTSC video or 625/PAL video. This information is used when the ADV611/ADV612 is in master and
decode modes so that the ADV611/ADV612 knows where
and when to generate the HSYNC, VSYNC, and FIELD
Pulses as well as when to insert the SAV and EAV time codes
(for CCIR-656 only) in the data stream. This control is maintained by the host processor. Table VII shows how the 525625 Control in the Mode Control register works.
Table VI. Component Digital Video Interfaces
Name
CCIR-656
Multiplex
Philips
Bits/
Color
Component Space
Nominal
Date
Sampling Rate (MHz) I/F Width
8
YCrCb
4:2:2
27
8
8
YUV
4:2:2
27
8
Table VII. Square Pixel Control, 525-625 Control, and
Video Formats
Internally, the video interface translates all video formats to one
consistent format to be passed to the wavelet kernel. This consistent internal video standard is 4:2:2 at 16 bits accuracy.
525-625
Control
Max
Horizontal
Size
Max
Field
Size
NTSC-PAL
VITC and Closed Captioning Support
0
1
720
720
243
288
CCIR-601 NTSC
CCIR-601 PAL
The video interface also supports the direct loss-less extraction
of 90-bit VITC codes during encode and the insertion of VITC
codes during decode. Closed Captioning data (found on active
Video Line 21) is handled just as normal active video on an
active scan line. As a result, no special dedicated support is
necessary for Closed Captioning. The data rates for Closed
Captioning data are low enough to ensure robust operation of
this mechanism at compression ratios of 50:1 and higher. Note
that you must include Video Line 21 in the ADV611/ADV612’s
defined active video area for Closed Caption support.
• Bipolar/Unipolar Color Component
This mode determines whether offsets are used on color components. In Philips mode, this control is usually set to Bipolar, since the color components are normal twos-compliment
signed values. In CCIR-656 mode, this control is set to Unipolar, since the color components are offset by 128. Note that
it is likely the ADV611/ADV612 will function if this control is
in the wrong state, but compression performance will be
degraded. It is important to set this bit correctly.
27 MHz Nominal Sampling
There is one clock input (VCLK) to support all internal processing elements. This is a 50% duty cycle signal and must be synchronous to the video data. Internally this clock is doubled using
a phase locked loop to provide for a 54 MHz internal processing
clock. The clock interface is a two pin interface that allows a
crystal oscillator to be tied across the pins or a clock oscillator to
drive one pin. The nominal clock rate for the video interface is
27 MHz. Note that the ADV611/ADV612 also supports a pixel
rate of 13.5 MHz.
Video Interface and Modes
In all, there are seven programmable features that configure the
video interface. These are:
• Encode-Decode Control
In addition to determining what functions the internal processing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line drivers. This control is maintained by the host processor.
REV. 0
• Active Area Control
Four registers HSTART (horizontal start), HEND (horizontal end), VSTART (vertical start) and VEND (vertical end)
determine the active video area. The maximum active video
area is 720 by 288 pixels for a single field.
• Video Format
This control determines the video format that is supported. In
general, the goal of the various video formats is to support
glueless interfaces to the wide variety of video formats peripheral components expect. This control is maintained by the
host processor. Table VIII shows a synopsis of the supported
video formats. Definitions of each format can be found later
in this section. For Video Interface pins descriptions, see the
Pin Function Descriptions.
–21–
ADV611/ADV612
Table VIII. Component Digital Video Formats
Name
Bit/
Component
Color
Space
CCIR-656
Multiplex Philips
8
8
YCrCb
YUV
Sampling
Nominal
Data Rate
(MHz)
Master/
Slave
I/F Width
Format
Number
4:2:2
4:2:2
27
27
Master
Either
8
8
0x0
0x2
Clocks and Strobes
All video data is synchronous to the video clock (VCLK).
The rising edge of VCLK is used to clock all data into the
ADV611/ADV612.
Synchronization and Blanking Pins
Three signals, which can be configured as inputs or outputs, are
used for video frame and field horizontal synchronization and
blanking. These signals are VSYNC, HSYNC, and FIELD.
VDATA Pins Functions With Differing Video Interface Formats
The functionality of the Video Interface pins depends on the
current video format.
Video Formats—CCIR-656
The ADV611/ADV612 supports a glueless video interface to
CCIR-656 devices when the Video Format is programmed to
CCIR-656 mode. CCIR-656 requires that 4:2:2 data (8 bits per
component) be multiplexed and transmitted over a single 8-bit
physical interface. A 27 MHz clock is transmitted along with the
data. This clock is synchronous with the data. The color space of
CCIR-656 is YCrCb.
When in master mode, the CCIR-656 mode does not require
any external synchronization or blanking signals to accompany
digital video. Instead, CCIR-656 includes special time codes
in the stream syntax that define horizontal blanking periods,
vertical blanking periods, and field synchronization (horizontal
and vertical synchronization information can be derived). These
time codes are called End-of-Active-Video (EAV) and Start-ofActive-Video (SAV). Each line of video has one EAV and one
SAV time code. EAV and SAV have three bits of embedded
information to define HSYNC, VSYNC and Field information
as well as error detection and correction bits.
VCLK is driven with a 27 MHz, 50% duty cycle clock which is
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. When decoding, the VCLK
signal is typically transmitted along with video data in the
CCIR-656 physical interface.
Electrically, CCIR-656 specifies differential ECL levels to be
used for all interfaces. The ADV611/ADV612, however, only
supports unipolar, TTL logic thresholds. Systems designs that
interface to strictly conforming CCIR-656 devices (especially
when interfacing over long cable distances) must include ECL
level shifters and line drivers.
The functionality of HSYNC, VSYNC and FIELD Pins is
dependent on three programmable modes of the ADV611/
ADV612: Master-Slave Control, Encode-Decode Control and
525-625 Control. Table X summarizes the functionality of
these pins in various modes.
Table IX. CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
HSYNC, VSYNC and FIELD
Functionality for CCIR-656
Master Mode (HSYNC, VSYNC
and FIELD Are Outputs)
Slave Mode (HSYNC, VSYNC
and FIELD Are Inputs)
Encode Mode (video data is input
to the chip)
Pins are driven to reflect the states of the
received time codes: EAV and SAV. This
functionality is independent of the state of
the 525-625 mode control. An encoder is
most likely to be in master mode.
These pins are used to control the
blanking of video and sequencing (used
with video decoders that do not conform to the correct number of samples
per line [e.g., the Harris 8115]).
Decode Mode (video data is output
from the chip)
Pins are output to the precise timing definitions
Undefined—Use Master Mode
for CCIR-656 interfaces. The state of the pins
reflect the state of the EAV and SAV timing
codes that are generated in the output video data.
These definitions are different for 525 and 625 line
systems. The ADV611/ADV612 completely manages
the generation and timing of these pins.
–22–
REV. 0
ADV611/ADV612
Table X. Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
HSYNC, VSYNC and FIELD
Functionality for Multiplexed
Philips
Encode Mode (video data is input
to the chip)
Master Mode (HSYNC, VSYNC
and FIELD Are Outputs)
Slave Mode (HSYNC, VSYNC
and FIELD Are Inputs)
The ADV611/ADV612 completely manages the generation These pins are used to control the
and timingof these pins. The device driving the ADV611/ blanking of video and sequencing.
ADV612 video interface must use these outputs to remain
in sync with the ADV611/ADV612. It is expected that this
combination of modes would not be used frequently.
Decode Mode (video data is output The ADV611/ADV612 completely manages the generation These pins are used to control the
from the chip)
and timing of these pins.
blanking of video and sequencing.
Video Formats — Multiplexed Philips Video
DRAM Manager
The ADV611/ADV612 supports a hybrid mode of operation that
is a cross between standard dual lane Philips and single lane
CCIR-656. In this mode, video data is multiplexed in the same
fashion in CCIR-656, but the values 0 and 255 are not reserved as
signaling values. Instead, external HSYNC and VSYNC pins are
used for signaling and video synchronization. VCLK may range
up to 27 MHz.
The DRAM Manager provides a sorting and reordering function on the subband coded data between the Wavelet Kernel
and the Programmable Quantizer. The DRAM manager provides a pipeline delay stage to the ADV611/ADV612. This
pipeline lets the ADV611/ADV612 extract current field image
statistics (min/max pixel values, sum of pixel values, and sum of
squares) used in the calculation of bin widths and reorder
wavelet transform data. The use of current field statistics in the
bin width calculation results in precise control over the compressed bit rate. The DRAM manager manages the entire operation and refresh of the DRAM.
VCLK is driven with up to a 27 MHz 50% duty cycle clock
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. The functionality of HSYNC,
VSYNC, and FIELD pins is dependent on three programmable
modes of the ADV611/ADV612; Master-Slave Control, EncodeDecode Control, and 525-625 Control. Table IX summarizes
the functionality of these pins in various modes.
Video Formats—References
For more information on video interface standards, see the
following reference texts.
• For the definition of CCIR-601:
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 601-3 Encoding Parameters of digital television
for studios, page 35, September 15, 1992.
• For the definition of CCIR-656:
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 656-1 Interfaces for digital component video
signals in 525 and 626 line television systems operating at the
4:2:2 level of Rec. 601, page 46, September 15, 1992.
Host Interface
The ADV611/ADV612 host interface is a high performance
interface that passes all command and real-time compressed
video data between the host and codec. A 512 position by 32-bit
wide, bidirectional FIFO buffer passes compressed video data
to and from the host. The host interface is capable of burst
transfer rates of up to 132 million bytes per second (4 × 33 MHz).
For host interface pins descriptions, see the Pin Function Descriptions section. For host interface timing information, see the
Host Interface Timing section.
REV. 0
The interface between the ADV611/ADV612 DRAM manager and DRAM is designed to be transparent to the user. The
ADV611/ADV612 DRAM pins should be connected to the
DRAM as called out in the Pin Function Descriptions section.
The ADV611/ADV612 requires one 256K word by 16-bit,
60 ns DRAM. The following is a selected list of manufacturers
and part numbers. All parts can be used with the ADV611/
ADV612 at all VCLK. Any DRAM used with the ADV611/
ADV612 must meet the minimum specifications outlined for
the Hyper Mode DRAMs listed in Table XI. For DRAM Interface pins descriptions, see the Pin Function Descriptions.
Table XI. Compatible DRAMs
Manufacturer Part Number
Notes
Toshiba
NEC
NEC
TC514265DJ/DZ/DFT-60
µPD424210ALE-60
µPD42S4210ALE-60
Hitachi
HM514265CJ-60
None
None
CBR Self-Refresh
feature of this
product is not
needed by the
ADV611/ADV612.
None
–23–
ADV611/ADV612
pseudo code for a video data transfer that matches the transfer
order shown in Figure 13 and uses the code names shown in
Table XIV. The blocks of data listed in Figure 13 correspond to
wavelet compressed sections of each field illustrated in Figure 13
as a modified Mallat diagram.
Compressed Data-Stream Definition
Through its Host Interface the ADV611/ADV612 outputs (during encode) and receives (during decode) compressed digital
video data. This stream of data passing between the ADV611/
ADV612 and the host is hierarchically structured and broken up
into blocks of data as shown in Figure 13. Table V shows
TIME
FRAME (N)
FIELD 1 SEQUENCE
FRAME (N + 1)
FRAME (N + 2)
(CONTINUOUS STREAM OF FRAMES)
FRAME (N + M)
FIELD 2 SEQUENCE
FIELD SEQUENCE STRUCTURE
START OF FIELD 1 OR 2 CODE
FIRST BLOCK SEQUENCE
VERTICAL INTERFACE TIME CODE
COMPLETE BLOCK SEQUENCE
FIRST BLOCK SEQUENCE STRUCTURE
SUB-BAND TYPE CODE
BIN WIDTH QUANTIZER CODE
DATA FOR MALLAT BLOCK 6
COMPLETE BLOCK SEQUENCE ORDER
SEQUENCE FOR MALLAT BLOCK 9
SEQUENCE FOR MALLAT BLOCK 20
(STREAM OF MALLAT
BLOCK SEQUENCES)
SEQUENCE FOR MALLAT BLOCK 3
COMPLETE BLOCK (INDIVIDUAL) SEQUENCE STRUCTURE
START OF BLOCK CODE
BIN WIDTH QUANTIZER CODE
DATA FOR MALLAT BLOCK
Figure 13. Hierarchical Structure of Wavelet Compressed Frame Data (Data Block Order)
–24–
REV. 0
ADV611/ADV612
Table XII. Pseudo-Code Describing a Sequence of Video Fields
Complete Sequence:
<Field 1 Sequence>
<Field 2 Sequence>
<Field 1 Sequence>
<Field 2 Sequence>
(Field Sequences)
<Field 1 Sequence>
<Field 2 Sequence>
#EOS
“Frame N; Field 1”
“Frame N; Field 2”
“Frame N+1; Field 1”
“Frame N+1; Field 2”
“Frame N+M; Field 1”
“Frame N+M; Field 2”
“Required in decode to let the ADV611/ADV612 know the
sequence of fields is complete.”
Field 1 Sequence:
#SOF1
<VITC>
<First Block Sequence>
<Complete Block Sequence>
Field 2 Sequence:
#SOF2
<VITC>
<First Block Sequence>
<Complete Block Sequence>
First Block Sequence:
<TYPE4>
<BW>
<Huff_Data>
Complete Block Sequence:
<Block Sequence>
...
(Block Sequences)
...
<Block Sequence>
Block Sequence:
#SOB1, #SOB2, #SOB3, #SOB4 or #SOB5
<BW>
<Huff_Data>
REV. 0
–25–
ADV611/ADV612
In general, a Frame of data is made up of odd and even Fields
as shown in Figure 13. Each Field Sequence is made up of a
First Block Sequence and a Complete Block Sequence. The
First Block Sequence is separate from the Complete Block Sequence. The Complete Block Sequence contains the remaining
41 Block Sequences (see block numbering in Figure 14). Each
Block Sequence contains a start of block delimiter, Bin Width
for the block and actual encoder data for the block. A pseudo
code bitstream example for one complete field of video is shown in
Table XIII. A pseudo code bitstream example for one sequence
of fields is shown in Table XIV. An example listing of a field
of video in ADV611/ADV612 bitstream format appears in
Table XVII.
Y COMPONENT
39
36
33
30
24
15
27
21
6
18
12
0
3
9
40 34
37 31
Cb COMPONENT
25
16
28
22
7
19
13
1
10
4
41 35
38 32
Cr COMPONENT
26
17
29
23
8
20
14
2
11
5
Figure 14. Block Order of Wavelet Compressed Field Data (Modified Mallat Diagram)
–26–
REV. 0
ADV611/ADV612
Table XIII. Pseudo Code of Compressed Video Data Bitstream for One Field of Video
Block Sequence Data
For Mallat Block Number . . .
#SOFn<VITC><TYPE4><BW><Huff_Data>
n indicates field 1 or 2 Huff_Data indicates Mallat block 6 data
A typical Bin Width (BW) factor for this block is 0x1DDC
Mallat block 9 data—Typical BW = 0x1DDC
Mallat block 20 data—Typical BW = 0x0C2E
Mallat block 22 data—Typical BW = 0x03A1
Mallat block 19 data—Typical BW = 0x0C2E
Mallat block 23 data—Typical BW = 0x03A1
Mallat block 17 data—Typical BW = 0x0C2E
Mallat block 25 data—Typical BW = 0x0306
Mallat block 16 data—Typical BW = 0x0C2E
Mallat block 26 data—Typical BW = 0x0306
Mallat block 14 data—Typical BW = 0x0E9D
Mallat block 28 data—Typical BW = 0x0306
Mallat block 13 data—Typical BW = 0x0E9D
Mallat block 29 data—Typical BW = 0x0306
Mallat block 11 data—Typical BW = 0x2410
Mallat block 31 data—Typical BW = 0x0114
Mallat block 10 data—Typical BW = 0x2410
Mallat block 32 data—Typical BW = 0x0114
Mallat block 8 data—Typical BW = 0x2410
Mallat block 34 data—Typical BW = 0x00E5
Mallat block 7 data—Typical BW = 0x2410
Mallat block 35 data—Typical BW = 0x00E6
Mallat block 5 data—Typical BW = 0x2B46
Mallat block 37 data—Typical BW = 0x00E6
Mallat block 4 data—Typical BW = 0x2B46
Mallat block 38 data—Typical BW = 0x00E6
Mallat block 2 data—Typical BW = 0xC62B
Mallat block 40 data—Typical BW = 0x009A
Mallat block 1 data—Typical BW = 0xC62B
Mallat block 41 data—Typical BW = 0x009A
Mallat block 0 data—Typical BW = 0xA417
Mallat block 39 data—Typical BW = 0x007F
Mallat block 12 data—Typical BW = 0x0C1A
Mallat block 36 data—Typical BW = 0x00BE
Mallat block 15 data—Typical BW = 0x0A16
Mallat block 33 data—Typical BW = 0x00BE
Mallat block 18 data—Typical BW = 0x0A16
Mallat block 30 data—Typical BW = 0x00E4
Mallat block 21 data—Typical BW = 0x0301
Mallat block 27 data—Typical BW = 0x0281
Mallat block 24 data—Typical BW = 0x0281
Mallat block 3 data—Typical BW = 0x23D5
#SOB4<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB3<BW><Huff_Data>
#SOB1<BW><Huff_Data>
#SOB4<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB4<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB4<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB4<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB2<BW><Huff_Data>
#SOB4<BW><Huff_Data>
Table XIV specifies the Mallat block transfer order and associated Start of Block (SOB) codes. Any of these SOB codes can be
replaced with an SOB#5 code for a zero data block.
Table XIV. Pseudo Code of Compressed Video Data Bitstream for One Sequence of Video Fields
Block Sequence Data
For Mallat Block Number
#SOF1<VITC><TYPE4><BW><Huff_Data>
... (41 #SOBn blocks)
/* Mallat block 6 data */
#SOF2<VITC><TYPE4><BW><Huff_Data>
... (41 #SOBn blocks)
. (any number of Fields in sequence)
#EOS
/* Mallat block 6 data */
REV. 0
/* Required in decode to end field sequence*/
–27–
ADV611/ADV612
Table XV. ADV611/ADV612 Field and Block Delimiters (Codes)
Code Name
Code
Description (Align all #Delimiter Codes to 32-Bit Boundaries)
#SOF1
0xffffffff40000000
Start of Field delimiter identifies Field1 data. #SOF1 resets the Huffman decoder and is
sufficient on its own to reset the processing of the chip during decode. Please note that this
code or #SOF2 are the only delimiters necessary between adjacent fields. #SOF1 operates
identically to #SOF2 except that during decode it can be used to differentiate between
Field1 and Field2 in the generation of the Field signal (master mode) and/or SAV/EAV
codes for CCIR-656 modes.
#SOF2
0xffffffff41000000
Start of Field delimiter identifies Field2 data. #SOF resets the Huffman decoder and is
sufficient on its own to reset the processing of the chip during decode. Please note that this
code or #SOF1 are the only delimiters necessary between adjacent fields. #SOF2 operates
identically to #SOF1 except that during decode it can be used to differentiate between
Field2 and Field1 in the generation of the Field signal (master mode) and/or SAV/EAV
codes for CCIR-656 modes.
<VITC>
(96 bits)
This is a 12-byte string of data extracted by the video interface during encode operations
and inserted by the video interface into the video data during decode operations. The data
content is 90 bits in length. For a complete description of VITC format, see pages 175-178
of Video Demystified: A Handbook For The Digital Engineer (listed in References section).
<TYPE1>
0x81
This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model
1 Chroma)
<TYPE2>
0x82
This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model
1 Luma)
<TYPE3>
0x83
This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model
2 Chroma)
<TYPE4>
0x84
This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model
2 Luma)
#SOB1
#SOB2
#SOB3
#SOB4
#SOB5
0xffffffff81
0xffffffff82
0xffffffff83
0xffffffff84
0xffffffff8f
<BW>
(16 bits, 8.8)
Start of Block delimiter identifies the start of Huffman coded subband data. This
delimiter will reset the Huffman decoder if a system ever experiences bit errors or gets
out of sync. The order of blocks in the frame is fixed and therefore implied in the bit
stream and no unique #SOB delimiters are needed per block. There are 41 #SOB
delimiters and associated BW and Huffman data within a field. #SOB1 is differentiated
from #SOB2, #SOB3 and #SOB4 in that they indicate which model and Huffman table
was used in the Run Length Coder for the particular block:
#SOB1 Model 1 Chroma
#SOB2 Model 1 Luma
#SOB3 Model 2 Chroma
#SOB4 Model 2 Luma
#SOB5 Zero data block. All data after this delimiter and before the next start of block
delimiter is ignored (if present at all) and assumed zero including the BW value.
This data code is not entropy coded, is always 16 bits in length and defines the Bin Width
Quantizer control used on all data in the block subband. During decode, this value is used
by the Quantizer. If this value is set to zero during decode, all Huffman data is presumed to
be zero and is ignored, but must be included. During encode, this value is calculated by
the external Host and is inserted into the bitstream by the ADV611/ADV612 (this value
is not used by the quantizer). Another value calculated by the Host, 1/BW is actually used
by the Quantizer during encode.
<HUFF_DATA>
(Modulo 32)
This data is the quantized and entropy coded block subband data. The data’s length is
dependent on block size and entropy coding so it is therefore variable in length. This field is
filled with 1s making it Modulo 32 bits in length. Any Huffman decode process can be
interrupted and reset by any unexpectedly received # delimiter following a bit error or
synchronization problem.
#EOS
0xffffffffc0ffffff
The host sends the #EOS (End of Sequence) to the ADV611/ADV612 during decode after
the last field in a sequence to indicate that the field sequence is complete. The ADV611/
ADV612 does not append this code to the end of encoded field sequences; it must be added
by the host.
–28–
REV. 0
ADV611/ADV612
Table XVI. Video Data Bitstream for One Field In a Video Sequence 1
ffff
8400
ffff
609f
8300
ffff
6894
811d
ffff
6894
8116
5d75
f1f8
0f87
6b5a
fbfb
fdff
fe62
7431
57ed
eb17
dff5
ef97
f87e
ffff
e9e9
b76e
ef7b
df69
c8fa
ffff
c9a7
8213
ffff
ffff
00ff
ffff
ffff
00fe
ffff
3fff
40f0
ffff
3fff
80f0
d75a
fc7e
c3e1
d6b5
fbfb
7fdf
a2ff
e9f4
fd7f
eff3
7eef
58bf
ffaf
ffff
e9e9
ddb7
def7
a647
7b77
ffff
1fff
80ff
ffff
4000
df0c
8300
ffff
c70f
8300
ffff
90ff
8300
ffff
9fff
f8f9
3f1f
f0f8
a2b0
fbfb
f7fd
ffff
fbff
bbe3
fc3f
d9fb
7f9f
f77e
8400
e9e9
fbbe
bdef
d3db
da69
8400
ffff
7703
8200
0000
daff
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ffff
ffff
74eb
8fc7
fd9f
d249
fbfb
feff
ffff
77eb
d2d3
7fd5
be5d
e1fb
cfab
00ff
e9e9
df9f
75f4
bed3
647c
00ff
ffff
5fff
00ff
0000
ffff
609f
8300
ffff
609f
811d
ffff
68aa
8116
ffff
d7af
e5fa
1f1f
24a5
fcfd
3fbb
8103
fd3f
dfe7
fbbf
62fd
feaf
e5d6
dfb7
e9e9
af6d
f7f4
4c8f
fd7b
c9a7
820f
ffff
7745
0000
ffff
ffff
00fe
ffff
ffff
40f0
ffff
bfff
80f0
ffff
5ebd
ff6f
2f2f
ce36
bdfe
effb
e6fd
b3ec
f87e
67ee
fe7f
ddfb
2fe9
c5ff
e9e9
b6db
dee9
a7b7
6100
1fff
00ff
ffff
efff
0000
8300
ffff
c70f
8300
ffff
90ff
8300
ffff
9fff
8300
7af5
d5f6
2f2f
db6d
dfb7
feff
bfab
f2d5
5f57
f975
87ef
3f77
f3fc
df0d
e9e9
6db6
2492
7da6
0000
ffff
7704
8200
ffff
0000
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ebf0
7d9f
2f2f
b6db
edfb
bfef
f9bf
efeb
eefd
8bf7
fabf
cbac
7f7f
7fff
dbef
db6d
4924
991f
0045
ffff
bfff
00ff
ffff
0000
609f
8300
ffff
609f
8300
ffff
68aa
8116
ffff
fe62
f8f8
67d9
2f2f
6db7
7eef
fbfe
57d5
f6fe
9fbb
f9fe
77ec
5fbf
d9f5
ffff
fbbe
b6db
924c
4f7e
bdfd
820f
ffff
7743
8400
0000
ffff
00fe
ffff
ffff
00fe
ffff
bfff
80f0
ffff
a2ff
f979
f67d
2f1f
c6fd
bbee
ffbf
f2eb
1fbb
e5d6
1fbf
fddf
cff0
7edf
ffff
9efe
6db6
fa7b
fb4d
37bb
00ff
ffff
1fff
00ff
8400
ffff
c5af
8300
ffff
c78f
8300
ffff
9bff
8300
ffff
7979
9f67
2ebd
fd3d
fbbe
efff
18f4
f67e
2fdf
eafd
2eb1
fdff
abc7
8202
9dbb
db6d
77da
323e
8888
7704
8400
ffff
df0c
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ffff
7979
d9f6
7af5
3d3d
dfbb
ffff
f9fd
afdb
e7f8
dfb3
7eff
57ee
431e
9afc
76ed
aff6
6991
9edd
8888
4fff
00ff
ffff
daff
df0d
8300
ffff
609f
8300
ffff
6894
8116
ffff
6894
8103
7979
7edf
ebd7
3d3d
dbe7
ffff
ffb7
f0f3
7eff
f77c
3fc3
fd9f
9f4f
3eff
dbb7
fd3d
f4f7
f69a
8888
ffff
c9a7
8200
8eff
00fe
ffff
ffff
00fe
ffff
3fff
80f0
ffff
3fff
e6e9
79fd
abec
ae9d
3d3d
f6fd
ffff
f5ff
aaed
abf7
bac5
f7fd
bbe5
c7f8
b7e9
6edd
bbed
efb4
647d
8888
ffff
1fff
00ff
ffff
c5af
8300
ffff
c78f
8300
ffff
9bff
8300
ffff
d74d
5f5f
f87c
74e9
3d3b
ff7f
8300
3feb
edf7
7ecf
fbfc
5fbb
d62f
7fff
ede9
bb76
7bde
d323
3dbb
8aff
8400
ffff
7743
ffff
ffff
00ff
ffff
ffff
00ff
ffff
ffff
00ff
ffff
75d7
c7e3
3e1f
a56d
7a7b
dff7
00ff
fafc
fe3f
ddf2
ff0f
f67e
dfe7
ffff
e9e9
eddb
f7bd
e9ed
ed34
ffff
00ff
ffff
1fff
NOTE
1
This table shows ADV611/ADV612 compressed data for one field in a color ramp video sequence. The SOF# and SOB# codes in the data are in bold text.
Bit Error Tolerance
Bit error tolerance is ensured because a bit error within a
Huffman coded stream does not cause #delimiter symbols to be
misread by the ADV611/ADV612 in decode mode. The worst
REV. 0
error that can occur is loss of a complete block of Huffman data.
With the ADV611/ADV612, this type of error results only in
some blurring of the decoded image, not complete loss of the
image.
–29–
ADV611/ADV612
APPLYING THE ADV611/ADV612
Using the ADV611/ADV612 in Computer Applications
This section includes the following topics:
Many key features of the ADV611/ADV612 were driven by the
demanding cost and performance requirements of computer
applications. The following ADV611/ADV612 features provide
key advantages in computer applications, such as the one in
Figure 15.
Using the ADV611/ADV612 in computer applications
Using the ADV611/ADV612 in stand-alone applications
Configuring the host interface for 16- or 32-bit data paths
Connecting the video interface to popular video encoders and
decoders
• Getting the most out of the ADV611/ADV612
•
•
•
•
The following Analog Devices products should be considered in
ADV611/ADV612 designs:
• ADV7175/ADV7176—Digital YUV to analog composite
video encoder
• AD722—Analog RGB to analog composite video encoder
• AD1843—Audio codec with embedded video synchronization
• ADSP-21xx—Family of fixed-point digital signal processors
• AD8xxx—Family of video operational amplifiers
A2
A3
• Host Interface
The 512 double word FIFO provides necessary buffering of
compressed digital video to deal with PCI bus latency.
• Low Cost External DRAM
Unlike many other real-time compression solutions, the
ADV611/ADV612 does not require expensive external
SRAM transform buffers or VRAM frame stores.
A0–A8
D0–D15
ADR0
ADR1
D0–D7
D8–D15
DQ0–DQ7
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
D16–D23
D24–D31
A0–A8
DQ1–DQ16
RAS
RAS
CAS
CAS
OE
WEL
WEH
WE
BE0–BE1
HOST BUS
BE2–BE3
DECODE1
ADV611/ADV612
A28
A29
A30
A31
CS
RD
RD
WR
WR
DRAM
(256K 3 16-BIT)
TOSHIBA
NEC
NEC
HITACHI
TC514265DJ/DZ/DFT-60
mPD424210ALE-60
mPD42S4210ALE-60
HM514265CJ-60
ANY DRAM USED WITH THE ADV611/ADV612
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
24.576MHz
XTAL
VCLKO
DECODE2
XTAL
STATS R
NOTE:
DECODE1 ASSERTS CS~ ON THE
ADV611/ADV612 FOR HOST ADDRESSES
0X4000,0000 THROUGH 0X4000,0013
DECODE2 IS HOST-SPECIFIC
HIRQ
LCODE
ACK
FIFO SRQ
FIFO ERR
FIFO STP
27MHz PAL OR NTSC
VCLK
LLC
SAA7111
VDATA [0–7]
Y[0–7]
COMPOSITE VIDEO INPUT
Figure 15. A Suggested PC Application Design
–30–
REV. 0
ADV611/ADV612
A0–A8
FL0
FL1
ADR0
D0–D15
ADR1
RAS
A0–A8
DQ1–DQ16
RAS
CAS
CAS
D8–D23
D16–D31
(256K 3 16-BIT)
WEL
WE
WEH
ADV611/ADV612
ADSP-2185
PF4
BE0–BE1
PF5
BE2–BE3
FL2
CS
RD
RD
WR
WR
IRQ2
DRAM
OE
D0–D15
TOSHIBA
NEC
NEC
HITACHI
TC514265DJ/DZ/DFT-60
mPD424210ALE-60
mPD42S4210ALE-60
HM514265CJ-60
ANY DRAM USED WITH THE ADV611/ADV612
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
24.576MHz
XTAL
LCODE
HIRQ
IRQL1
THE ADSP-2185 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
XTAL
27MHz PAL OR NTSC
VCLK
LLC
SAA7111
Y[0–7]
VDATA [0–7]
COMPOSITE VIDEO INPUT
Figure 16. Alternate Stand-Alone Application Design
Using the ADV611/ADV612 In Stand-Alone Applications
XTAL
Figure 16 shows the ADV611/ADV612 in a noncomputer
based applications. Here, an ADSP-2185 digital signal processor provides Host control and BW calculation services. Note
that all control and BW operations occur over the host interface
in this design.
10kV
ADV7175
XTAL
XTAL
LLC
SAA7111
VCLK
ADV611/ADV612
Y(0:7)
VDATA (0:7)
(CCIR-656 MODE)
ADV611/ADV612
(CCIR-656 MODE)
(MODE 0 & SLAVE MODE)
Figure 18. ADV611/ADV612 and ADV7175 Example
Interfacing Block Diagram
Using the Raytheon TMC22153 Video Decoder
Raytheon has a whole family of video parts. Any member of the
family can be used. The user must select the part needed based
on the requirements of the application. Because the Raytheon
part does not include the A/Ds, an external A/D is necessary in
this design (or a pair of A/Ds for S video).
The part can be used in CCIR-656 (D1) mode for a zero control signal interface. Special attention must be paid to the video
output modes in order to get the right data to the right pins (see
the following diagram).
Note that the circuit in Figure 19 has not been built or tested.
Figure 17. ADV611/ADV612 and SAA7111 Example
Interfacing Block Diagram
VCLK
XTAL
Using the Analog Devices ADV7175 Video Encoder
CLOCK
TMC22153
Because the ADV7175 has a CCIR-656 interface, it connects
directly with the ADV611/ADV612 without “glue” logic. Note
that the ADV7175 can only be used at CCIR-601 sampling
rates.
Y(2:9)
MODE SET TO:
CDEC = 1
YUVT = 1
F422 = X
The ADV7175 example circuit, which appears in Figure 18, is
used in this configuration on the ADV611 CCTVPIPE demonstration board.
REV. 0
VDATA (7:0)
P7–P0
150V
The following circuits are recommendations only. Analog
Devices has not actually built or tested these circuits.
The SAA7111 example circuit, which appears in Figure 17, is
used in this configuration on the ADV611 CCTVPIPE demonstration board.
VCLKO
ALSB
Connecting the ADV611/ADV612 to Popular Video Decoders
and Encoders
Using the Philips SAA7111 Video Decoder
XTAL VCLK
BLANK
CLOCK
VCLK
ADV611/ADV612
VDATA (0:7)
(CCIR-656 & SLAVE MODE)
Figure 19. ADV611/ADV612 and TMC22153 Example
CCIR-656 Mode Interface
–31–
ADV611/ADV612
P8–P15
HARRIS
8115
8
CLK2
CLK2
The exact part number is ADV611-CCTVPIPE and it can be
purchased through any Analog Devices authorized sales channel.
VDATA (0–7)
VCLK
A PCI card is available for the ADV601 called the “VideoLab,”
which is bitstream compatible with the ADV611/ADV612. See
the Analog Devices Web site for further details.
ADV611/ADV612
27MHz
PIXEL CLOCK GSC
Software Codec
Analog Devices has created two types of software products for
cases where encoding or decoding in software are desirable.
Figure 20. Using the Harris 8115 Decoder
• Bit Exact Codec – Nonreal-time bit exact encoder for
Windows® ’95 or ’98.
GETTING THE MOST OUT OF ADV611/ADV612
How Much Compression Can Be Expected
• MMX/DirectShow Player – Real-time playback for
Windows ’98 (PC monitor can be used to view the video
directly–no need for a dedicated TV monitor).
The ADV611/ADV612 can be used in applications where up
to 7500:1 compression is required. To express this in more
meaningful terms, a digitized NTSC video signal at 167 MBit/s
per second can be reduced to less than 25 kbits per second. To
achieve this performance, the following approach could be used:
Field Rate Reduction
As demonstrated by the CCTVPIPE evaluation board, field
rates can be reduced to increase compression. The ADV611/
ADV612 allow this to be done in hardware (see register
descriptions).
1. Image Compressed to 250:1
2. Frame Rate Reduced to 1 frame per second (not uncommon
in CCTV applications)
Edge Enhancement and Detection
3. Quality box size less than 1% of the total image size
Since the ADV611/ADV612 filters the image into wavelet
subbands, edge information is isolated in the high pass blocks of
image data (see the Mallat diagram of the Analog Devices building in the ADV601LC data sheet for an illustration). By zeroing
the low pass blocks, the ADV611/ADV612 will preserve only
the high pass content of the image and thus enhance the edges
in the image. The CCTVPIPE has a mode that demonstrates
this feature. Furthermore, these blocks can be Huffman decoded and analyzed for edge detection purposes.
4. Background contrast attenuated by 18 dB
The scenario described above used by Analog Devices on the
CCTVPIPE evaluation board as the splash-screen after powerup. Video quality is subjective, and therefore, it is highly recommended to perform a direct evaluation of the CCTVPIPE or the
ADV601 software codec to confirm that the compression performance is appropriate for a given application.
While the ADV611/ADV612 can be used in very high compression applications as outlined above, it is equally suitable for full
resolution, 60 field per second visually loss-less applications.
Motion Detection
There are two known means of implementing motion detection
with the ADV611/ADV612.
Evaluation Board
1. Compare the image statistics between fields of video. This is
the technique used on the CCTVPIPE for the motion detection demo.
There is a low cost stand-alone evaluation board for the ADV611
called the CCTVPIPE (see block diagram). The CCTVPIPE
provides a fast, simple, and low cost means of evaluating the
performance of the ADV611/ADV612 and it is very similar to
the evaluation board for the ADV601LC, the VideoPipe. The
CCTVPIPE is shipped with a small mouse to allow real-time
quality box control. The board is also shipped with a small
speaker to provide an audio alert signal when motion is detected
in the video image. All of the source code and schematics for the
CCTVPIPE are available from the Analog Devices Web site free
of charge (www.analog.com/wavelet).
2. Decode the smallest Mallat block (Block 39) and compare
one field to the next. Since these block are small (approximately
2400 pixels) the computational burden is much less than it
would be for the entire image. For comparative purposes, the
data samples in Block 39 contain only 1/1024th of the total
samples, or 1/512th the luminance samples. Please Contact
Analog Device, Inc. for information on how to implement
this technique with quality box placement.
SERIAL PORT
(SPORT) EZ-ICE
JP16
JP17
RS-232
P1
ADV611
Y/C
J2
CVBS
J11
SAA7111
DRAM
ADV611
DRAM
ADSP-2185
H/W RESET
CCIR-656
J12
+5VDC
J10
H/W RESET
SRAM
ROM
SRAM
PALS
ADV611
ADV7175
Y/C
J8
CVBS
J7
H/W RESET
RESET
FREEZE
UP
DOWN
SELECT
CCTVPIPE
CCIR-656
J13
PUSH
BUTTONS
Figure 21. ADV611 CCTVPIPE Block Diagram
Windows is a registered trademark of Microsoft Corporation.
–32–
REV. 0
SPECIFICATIONS
ADV611/ADV612
The ADV611/ADV612 Video Codec uses a Bi-Orthogonal (7, 9) Wavelet Transform.
RECOMMENDED OPERATING CONDITIONS
Parameter
Description
Min
Max
Unit
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
4.50
0
5.50
+70
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Max
Unit
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Hi-Level Input Voltage
Lo-Level Input Voltage
Hi-Level Output Voltage
Lo-Level Output Voltage
Hi-Level Input Current
Lo-Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Input Pin Capacitance
Output Pin Capacitance
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C
2.0
N/A
2.4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
N/A
0.4
10
10
10
10
8*
8*
V
V
V
V
µA
µA
µA
µA
pF
pF
*Guaranteed but not tested.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Description
Min
Max
Unit
VDD
VIN
VOUT
TAMB (ADV611)
TAMB (ADV612)
TS
TL
Supply Voltage
Input Voltage
Output Voltage
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Lead Temperature (5 sec) PQFP
–0.3
N/A
N/A
0
–25
–65
N/A
+7
VDD ± 0.3
VDD ± 0.3
+70
+85
+150
+280
V
V
V
°C
°C
°C
°C
*Stresses greater than those listed above under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the Pin Definitions section of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
SUPPLY CURRENT AND POWER
Parameter
Description
Test Conditions
Min
Max
Unit
IDD
IDD
IDD
Supply Current (Dynamic)
Supply Current (Soft Reset)
Supply Current (Idle)
@ VDD = max, tVCLK_CYC = 37 ns (at 27 MHz VCLK)
@ VDD = max, tVCLK_CYC = 37 ns (at 27 MHz VCLK)
@ VDD = max, tVCLK_CYC = None
0.11
0.08
0.01
0.27
0.17
0.02
A
A
A
ENVIRONMENTAL CONDITIONS
Parameter
Description
ADV611/ADV612 Max
Unit
θCA
θJA
θJC
Case-to-Ambient Thermal Resistance
Junction-to-Ambient Thermal Resistance
Junction-to-Case Thermal Resistance
30
35
5
°C/W
°C/W
°C/W
CAUTION
The ADV611/ADV612 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges. Proper ESD
precautions are strongly recommended to avoid functional damage or performance degradation.
The ADV611/ADV612 latchup immunity has been demonstrated at ≥200 mA/–200 mA on all pins
when tested to industry standard/JEDEC methods.
REV. 0
–33–
WARNING!
ESD SENSITIVE DEVICE
ADV611/ADV612
TEST CONDITIONS
output reaches the high impedance state (also +1.5 V). Similarly, these tests conditions consider an output as enabled when
the output leaves the high impedance state and begins driving a
measured high or low voltage. Tests measure output enable time
(tENABLE) as the time between the reference input signal crossing
+1.5 V and the time that the output reaches the measured high
or low voltage.
Figure 22 shows test condition voltage reference and device
loading information. These test conditions consider an output
as disabled when the output stops driving and goes from the
measured high or low voltage to a high impedance state. Tests
measure output disable time (tDISABLE) as the time between the
reference input signal crossing +1.5 V and the time that the
INPUT & OUTPUT VOLTAGE/TIMING REFERENCES
VIH
INPUT
REFERENCE
SIGNAL
DEVICE LOADING FOR AC MEASUREMENTS
1.5V
VIL
IOL
tDISABLED
VOH
tENABLED
TO
OUTPUT
PIN
1.5V
OUTPUT
SIGNAL
+1.5V
2pF
VOL
IOH
Figure 22. Test Condition Voltage Reference and Device Loading
TIMING PARAMETERS
This section contains signal timing information for the ADV611/ADV612. Timing descriptions for the following items appear in this
section:
• Clock signal timing
• Video data transfer timing (CCIR-656, and Multiplexed Philips formats)
• Host data transfer timing (direct register read/write access)
Clock Signal Timing
The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin
loading of 50 pF.
Table XVII. Video Clock Period, Frequency, Drift and Jitter
Video Format
Min VCLK_CYC
Period
Nominal VCLK_CYC
Period (Frequency)
Max VCLK_CYC
Period1, 2
CCIR-601 PAL
CCIR-601 NTSC
35.2 ns
35.2 ns
37 ns (27 MHz)
37 ns (27 MHz)
38.9 ns
38.9 ns
NOTES
1
VCLK Period Drift = ± 0.1 (VCLK_CYC/field.
2
VCLK edge-to-edge jitter = 1 ns.
Table XVIII. Video Clock Duty Cycle
1
VCLK Duty Cycle
Min
Nominal
Max
(40%)
(50%)
(60%)
NOTE
1
VCLK Duty Cycle = t VCLK_HI/(tVCLK_LO) × 100.
Table XIX. Video Clock Timing Parameters
Parameter
Description
Min
tVCLK_CYC
tVCLKO_D0
tVCLKO_D1
VCLK Signal, Cycle Time (1/Frequency) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz
(See Video Clock Period Table)
10
29
10
29
–34–
Max
Unit
ns
ns
REV. 0
ADV611/ADV612
tVCLK
CYC
(I) VCLK
(O) VCLKO
(VCLK2 = 0)
tVCLKO
D0
tVCLKO
D1
(I) VCLKO
(VCLK2 = 1)
NOTE:
USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS.
DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE.
Figure 23. Video Clock Timing
CCIR-656 Video Format Timing
The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video
mode. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for CCIR-656 video, the label CTRL
indicates the VSYNC, HSYNC, and FIELD pins.
Table XX. CCIR-656 Video—Decode Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Units
tVDATA_DC_D
tVDATA_DC_OH
tCTRL_DC_D
tCTRL_DC_OH
VDATA Signals, Decode CCIR-656 Mode, Delay
VDATA Signals, Decode CCIR-656 Mode, Output Hold
CTRL Signals, Decode CCIR-656 Mode, Delay
CTRL Signals, Decode CCIR-656 Mode, Output Hold
N/A
4
N/A
5
14
N/A
11
N/A
ns
ns
ns
ns
(O) VCLKO
(O) VDATA
VALID
t VDATA
t VDATA
(O) CTRL
VALID
VALID
VALID
DC D
VALID
t CTRL
VALID
DC OH
DC OH
t CTRL
DC D
Figure 24. CCIR-656 Video—Decode Pixel (YCrCb) Transfer Timing
Table XXI. CCIR-656 Video—Encode Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Units
tVDATA_EC_S
tVDATA_EC_H
tCTRL_EC_D
tCTRL_EC_OH
VDATA Bus, Encode CCIR-656 Mode, Setup
VDATA Bus, Encode CCIR-656 Mode, Hold
CTRL Signals, Encode CCIR-656 Mode, Delay
CTRL Signals, Encode CCIR-656 Mode, Output Hold
2
5
N/A
20
N/A
N/A
33
N/A
ns
ns
ns
ns
(I) VCLK
(I) VDATA
VALID
VALID
tVDATA
(O) CTRL
t VDATA
EC H
ASSERTED
ASSERTED
tCTRL
EC S
EC OH
tCTRL
EC D
Figure 25. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing
REV. 0
–35–
Y
N-2
Cr
N-2
Y
N-1
–36–
623
624
EAV
XX
FF
SAV
XX
EC S
Cb
0
Y
0
t VDATA
625
1
2
3
4
5
6
21
22
23
24
309
310
311
312
313
314
315
316
317
318
319
ENCODE / DECODE & MASTER CCIR-656 -- 625 (PAL) FRAME (VERTICAL) TRANSFER TIMING
FF
t VDATA
Cr
0
EC H
334
Y
1
335
Cb
2
336
337
Y
2
524
525
1
2
3
4
5
6
7
8
9
20
21
22
23
262
263
264
265
266
267
268
282
ENCODE / DECODE CCIR-656 -- 525 (NTSC) FRAME (VERTICAL) TRANSFER TIMING
283
284
335
336
337
338
(NOTE: STATS R IS ALWAYS LO FOR 45 CYCLES BEFORE GOING HI AGAIN. STATS R IS LO COMING OUT OF SOFT RESET AND GOES HIGH RIGHT AFTER THE ADV611/ADV612 FINISHES TAKING IN THE VERY FIRST FIELD.)
(O) STATS R
(ENCODE)
(O) FIELD
(O) VSYNC
(O) HSYNC
525 (NTSC)
LINE #
(NOTE: STATS R IS ALWAYS LO FOR 45 CYCLES BEFORE GOING HI AGAIN. STATS R IS LO COMING OUT OF SOFT RESET AND GOES HIGH RIGHT AFTER THE ADV611/ADV612 FINISHES TAKING IN THE VERY FIRST FIELD.)
(O) STATS_R
(ENCODE)
(O) FIELD
(O) VSYNC
(O) HSYNC
622
NTSC CCIR-601 PIXEL, N = 720
Cb
N-2
PAL CCIR-601 PIXEL, N = 720
625 (PAL)
LINE # 621
(O) VCLKO
(VCLK2 = 1)
(O) VCLKO
(VCLK2 = 0)
(O) HSYNC
(I) VDATA
(I) VCLK
SAMPLE 0
ENCODE CCIR-656 -- LINE (HORIZONTAL) TRANSFER TIMING (FOR DECODE VDATA IS SYNCHRONOUS TO VCLKO)
ADV611/ADV612
Figure 26. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing
Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO.
REV. 0
ADV611/ADV612
Multiplexed Philips Video Timing
The diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal)
and frame (vertical) data transfer timing, see Figure 29. All output values assume a maximum pin loading of 50 pF. Note that in
timing diagrams for Multiplexed Philips video, the label CTRL indicates the VSYNC, HSYNC and FIELD pins.
Table XXII. Multiplexed Philips Video—Decode and Master Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_DMM_D
tVDATA_DMM_OH
tCTRL_DMM_D
tCTRL_DMM_OH
VDATA Bus, Decode Master Multiplexed Philips, Delay
VDATA Bus, Decode Master Multiplexed Philips, Output Hold
CTRL Signals, Decode Master Multiplexed Philips, Delay
CTRL Signals, Decode Master Multiplexed Philips, Output Hold
N/A
4
N/A
5
14
N/A
11
N/A
ns
ns
ns
ns
(O) VCLKO
(O) VDATA
VALID
tVDATA
tVDATA
tCTRL
VALID
VALID
VALID
DMM D
VALID
(O) CTRL
VALID
DMM OH
DMM OH
tCTRL
DMM D
Figure 27. Multiplexed Philips Video—Decode and Master Pixel (YCrCb) Transfer Timing
Table XXIII. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_DSM_D
tVDATA_DSM_OH
tCTRL_DSM_S
tCTRL_DSM_H
VDATA Bus, Decode Slave Multiplexed Philips, Delay
VDATA Bus, Decode Slave Multiplexed Philips, Output Hold
CTRL Signals, Decode Slave Multiplexed Philips, Setup
CTRL Signals, Decode Slave Multiplexed Philips, Hold
N/A
4
16
42
14
N/A
N/A
N/A
ns
ns
ns
ns
(O) VCLKO
(O) VDATA
VALID
tVDATA
VALID
DSM OH
tVDATA
(I) CTRL
DSM D
VALID
VALID
tCTRL
tCTRL
DSM H
DSM S
Figure 28. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Timing
REV. 0
–37–
Y
N-2
Cr
N-2
Y
N-1
–38–
623
624
625
1
2
3
4
5
(NOTE: ADV611/ADV612 GETS HSYNCH FROM PHILIPS HREF)
622
Cb
0
Y
0
Cr
0
t VDATA_EC_H
6
7
8
23
24
309
310
311
312
313
314
315
316
317
318
319
320
321
Y
1
335
Cb
2
336
Y
2
525
1
2
3
4
5
6
7
8
9
21
22
23
24
262
263
264
265
266
267
268
282
283
284
335
ENCODE / DECODE & MASTER MULTIPLEXED PHILIPS -- 525 (NTSC) FRAME (VERTICAL) TRANSFER TIMING
(NOTE: ADV611/ADV612 IN SLAVE MODE GETS HSYNCH FROM PHILIPS HREF)
524
336
337
338
(NOTE: STATS_R IS ALWAYS LO FOR 45 CYCLES BEFORE GOING HI AGAIN. STATS R IS LO COMING OUT OF SOFT RESET AND GOES HIGH RIGHT AFTER THE ADV611/ADV612 FINISHES TAKING IN THE VERY FIRST FIELD.)
STATS_R
(ENCODE)
(O) FIELD
VSYNC
HSYNC
525 (NTSC)
LINE #
(NOTE: STATS_R IS ALWAYS LO FOR 45 CYCLES BEFORE GOING HI AGAIN. STATS R IS LO COMING OUT OF SOFT RESET AND GOES HIGH RIGHT AFTER THE ADV611/ADV612 FINISHES TAKING IN THE VERY FIRST FIELD.)
STATS_R
(ENCODE)
(O) FIELD
VSYNC
HSYNC
t VDATA_EC_S
ENCODE / DECODE & MASTER MULTIPLEXED PHILIPS -- 625 (PAL) FRAME (VERTICAL) TRANSFER TIMING
NTSC CCIR-601 PIXEL, N = 720
Cb
N-2
PAL CCIR-601 PIXEL, N = 720
625 (PAL)
LINE # 621
(O) VCLKO
(VCLK2 = 1)
(O) VCLKO
(VCLK2 = 0)
(O) HSYNC
(I) VDATA
(I) VCLK
SAMPLE 0
ENCODE MASTER MULTIPLEXED PHILIPS -- LINE (HORIZONTAL) TRANSFER TIMING (FOR DECODE VDATA IS SYNCHRONOUS TO VCLKO)
ADV611/ADV612
Figure 29. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing
REV. 0
ADV611/ADV612
Table XXIV. Multiplexed Philips Video—Encode and Master Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_EMM_S
tVDATA_EMM_H
tCTRL_EMM_D
tCTRL_EMM_OH
VDATA Bus, Encode Master Multiplexed Philips, Setup
VDATA Bus, Encode Master Multiplexed Philips, Hold
CTRL Signals, Encode Master Multiplexed Philips, Delay
CTRL Signals, Encode Master Multiplexed Philips, Output Hold
2
5
N/A
20
N/A
N/A
33
N/A
ns
ns
ns
ns
(I) VCLK
VALID
(I) VDATA
VALID
tVDATA
(O) CTRL
tVDATA
EMM H
ASSERTED
ASSERTED
tCTRL
EMM S
EMM OH
tCTRL
EMM D
Figure 30. Multiplexed Philips Video—Encode and Master Pixel (YCrCb) Transfer Timing
Table XXV. Multiplexed Philips Video—Encode and Slave Pixel (YCrCb) Timing Parameters
Parameter
Description
Min
Max
Unit
tVDATA_ESM_S
tVDATA_ESM_H
tCTRL_ESM_S
tCTRL_ESM_H
VDATA Bus, Encode Slave Multiplexed Philips Mode, Setup
VDATA Bus, Encode Slave Multiplexed Philips Mode, Hold
CTRL Signals, Encode Slave Multiplexed Philips Mode, Setup
CTRL Signals, Encode Slave Multiplexed Philips Mode, Hold
2
5
5
5
N/A
N/A
N/A
N/A
ns
ns
ns
ns
(I) VCLK
(I) VDATA
VALID
VALID
tVDATA
(I) CTRL
ESM S
tVDATA
ESM H
ASSERTED
ASSERTED
tCTRL
ESM S
tCTRL
ESM H
Figure 31. Multiplexed Philips Video—Encode and Slave Pixel (YCrCb) Transfer Timing
REV. 0
–39–
ADV611/ADV612
Host Interface (Indirect Address, Indirect Register Data and Interrupt Mask/Status) Register Timing
The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers,
except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers
are slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct
register, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect
Register Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.
Table XXVI. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters
Parameter
Description
Min
tRD_D_RDC
tRD_D_PWA
tRD_D_PWD
tADR_D_RDS
tADR_D_RDH
tDATA_D_RDD
tDATA_D_RDOH
tRD_D_WRT
tACK_D_RDD
tACK_D_RDOH
RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Read Setup
ADR Bus, Direct Register, Read Hold
DATA Bus, Direct Register, Read Delay
DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)
WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)
1
N/A
N/A1
5
2
2
N/A
26
48.74
8.6
11
Max
Unit
N/A
N/A
N/A
N/A
N/A
171.62, 3
N/A
N/A
287.15, 6
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
RD input must be asserted (low) until ACK is asserted (low).
2
Maximum tDATA_D_RDD varies with VCLK according to the formula: t DATA_D_RDD (MAX) = 4 (VCLK Period) +16.
3
During STATS_R deasserted (low) conditions, t DATA_D_RDD may be as long as 52 VCLK periods.
4
Minimum tRD_D_WRT varies with VCLK according to the formula: t RD_D_WRT (MIN) = 1.5 (VCLK Period) –4.1.
5
Maximum tACK_D_RDD varies with VCLK according to formula: t ACK_D_RDD (MAX) = 7 (VCLK Period) +14.8.
6
During STATS_R deasserted (low) conditions, t ACK_D_RDD may be as long as 52 VCLK periods.
tRD
D RDC
(I) RD
tRD
(I) ADR, BE, CS
tRD
D PWA
D PWD
VALID
tADR
D RDS
tDATA
D RDD
VALID
tADR
D RDH
VALID
(O) DATA
tDATA
VALID
D RDOH
(I) WR
tRD
D WRT
(O) ACK
tACK
D RDD
tACK
D RDOH
Figure 32. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing
–40–
REV. 0
ADV611/ADV612
Table XXVII. Host (Indirect Address, Indirect Data and Interrupt Mask/Status) Write Timing Parameters
Parameter
Description
Min
tWR_D_WRC
tWR_D_PWA
tWR_D_PWD
tADR_D_WRS
tADR_D_WRH
tDATA_D_WRS
tDATA_D_WRH
tWR_D_RDT
tACK_D_WRD
tACK_D_WROH
WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
WR Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Write Setup
ADR Bus, Direct Register, Write Hold
DATA Bus, Direct Register, Write Setup
DATA Bus, Direct Register, Write Hold
WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK)
ACK Signal, Direct Register, Write Output Hold
1
N/A
N/A1
5
2
2
–10
0
35.62
8.6
11
Max
Unit
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
182.13, 4
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
WR input must be asserted (low) until ACK is asserted (low).
2
Minimum tWR_D_RDT varies with VCLK according to the formula: t WR_D_RDT (MIN) = 0.8 (VCLK Period) +7.4.
3
Maximum tWR_D_WRD varies with VCLK according to the formula: t ACK_D_WRD (MAX) = 4.3 (VCLK Period) +14.8.
4
During STATS_R deasserted (low) conditions, t ACK_D_WRD may be as long as 52 VCLK periods.
tWR
D WRC
(I) WR
tWR
(I) ADR, BE, CS
tWR
D PWA
VALID
tADR
D WRS
VALID
tADR
D WRH
VALID
(I) DATA
tDATA
D WRS
D PWD
tDATA
VALID
D WRH
(I) RD
tWR
D RDT
(O) ACK
tACK
D WRD
tACK
D WROH
Figure 33. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing
REV. 0
–41–
ADV611/ADV612
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV611/ADV612’s Compressed Data
register. Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and
Interrupt Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address,
Indirect Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the RD
or WR signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.
Table XXVIII. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
tRD_CD_RDC
tRD_CD_PWA
tRD_CD_PWD
tADR_CD_RDS
tADR_CD_RDH
tDATA_CD_RDD
tDATA_CD_RDOH
tACK_CD_RDD
tACK_CD_RDOH
RD Signal, Compressed Data Direct Register, Read Cycle Time
RD Signal, Compressed Data Direct Register, Pulsewidth Asserted
RD Signal, Compressed Data Direct Register, Pulsewidth Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK Signal, Compressed Data Direct Register, Read Delay
ACK Signal, Compressed Data Direct Register, Read Output Hold
28
10
10
2
2
N/A
18
N/A
9
N/A
N/A
N/A
N/A
N/A
10
N/A
18
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRD
CD RDC
(I) RD
tRD
(I) ADR, BE, CS
tRD
CD PWD
VALID
tADR
(O) DATA
CD PWA
VALID
tADR
CD RDS
CD RDH
VALID
VALID
tDATA
CD RDOH
tDATA
CD RDD
(O) ACK
tACK
CD RDOH
tACK
CD RDD
Figure 34. Host (Compressed Data) Read Transfer Timing
–42–
REV. 0
ADV611/ADV612
Table XXIX. Host (Compressed Data) Write Timing Parameters
Parameter
Description
Min
Max
Unit
tWR_CD_WRC
tWR_CD_PWA
tWR_CD_PWD
tADR_CD_WRS
tADR_CD_WRH
tDATA_CD_WRS
tDATA_CD_WRH
tACK_CD_WRD
tACK_CD_WROH
WR Signal, Compressed Data Direct Register, Write Cycle Time
WR Signal, Compressed Data Direct Register, Pulsewidth Asserted
WR Signal, Compressed Data Direct Register, Pulsewidth Deasserted
ADR Bus, Compressed Data Direct Register, Write Setup
ADR Bus, Compressed Data Direct Register, Write Hold
DATA Bus, Compressed Data Direct Register, Write Setup
DATA Bus, Compressed Data Direct Register, Write Hold
ACK Signal, Compressed Data Direct Register, Write Delay
ACK Signal, Compressed Data Direct Register, Write Output Hold
28
10
10
2
2
2
2
N/A
9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
19
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWR
CD WRC
(I) WR
tWR
(I) ADR, BE, CS
tWR
CD PWA
CD PWD
VALID
tADR
VALID
tADR
CD WRS
(I) DATA
CD WRH
VALID
VALID
tDATA
CD WRS
tDATA
CD WRH
(O) ACK
tACK
CD WRD
tACK
CD WROH
Figure 35. Host (Compressed Data) Write Transfer Timing
REV. 0
–43–
ADV611/ADV612
ADV611/ADV612 LQFP PINOUTS
Pin
Pin
Name
Pin
Type
Pin
Pin
Name
Pin
Type
Pin
Pin
Name
Pin
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DATA4
DATA3
DATA2
DATA1
DATA0
VDD
GND
RD
WR
CS
ADR1
ADR0
GND
BE2–BE3
BE0–BE1
GND
RESET
VDD
ACK
VDD
GND
HIRQ
LCODE
FIFO_SRQ
STATS_R
VDD
GND
GND
VDD
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
GND
RAS
I/O
I/O
I/O
I/O
I/O
POWER
GROUND
I
I
I
I
I
GROUND
I
I
GROUND
I
POWER
O
POWER
GROUND
O
O
O
O
POWER
GROUND
GROUND
POWER
O
O
O
O
O
O
O
O
O
GROUND
O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CAS
WE
VDD
VDD
DDAT15
DDAT14
DDAT13
DDAT12
DDAT11
DDAT10
DDAT9
DDAT8
DDAT7
DDAT6
DDAT5
DDAT4
DDAT3
DDAT2
DDAT1
DDAT0
GND
VDD
GND
VDD
STALL
GND
ENC
VCLKO
VDD
XTAL
VCLK
GND
FIELD
HSYNC
VSYNC
GND
VDD
VDATA7
VDATA6
VDATA5
O
O
POWER
POWER
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GROUND
POWER
GROUND
POWER
I
GROUND
O
O
POWER
I
I
GROUND
I OR O
I OR O
I OR O
GROUND
POWER
I/O
I/O
I/O
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VDATA4
GND
VDD
VDATA3
VDATA2
VDATA1
VDATA0
NC*
NC*
GND
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
VDD
DATA19
DATA18
DATA17
DATA16
GND
GND
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
I/O
GROUND
POWER
I/O
I/O
I/O
I/O
NC
NC
GROUND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
GROUND
GROUND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
*Apply a 10 kΩ pull-down resistor to this pin.
–44–
REV. 0
ADV611/ADV612
91 DATA31
92 DATA30
93 DATA29
95 DATA27
94 DATA28
97 DATA25
96 DATA26
98 DATA24
99 DATA23
101 DATA21
100 DATA22
102 DATA20
103 VDD
105 DATA18
104 DATA19
106 DATA17
107 DATA16
109 GND
108 GND
111 DATA14
110 DATA15
113 DATA12
112 DATA13
115 DATA10
114 DATA11
117 DATA8
116 DATA9
119 DATA6
118 DATA7
120 DATA5
ADV611/ADV612 PIN CONFIGURATION
DATA4
1
DATA3
2
DATA2
3
88 NC*
DATA1
4
87 VDATA0
DATA0
5
86 VDATA1
VDD
6
85 VDATA2
GND
7
84 VDATA3
RD
8
83 VDD
WR
9
82 GND
90 GND
PIN 1
IDENTIFIER
89 NC*
CS 10
81 VDATA4
ADR1 11
80 VDATA5
ADR0 12
79 VDATA6
GND 13
78 VDATA7
BE2–BE3 14
ADV611/ADV612
77 VDD
BE0–BE1 15
LQFP
76 GND
TOP VIEW
(Not to Scale)
GND 16
RESET 17
74 HSYNC
VDD 18
73 FIELD
ACK 19
VDD 20
72 GND
GND 21
70 XTAL
71 VCLK
HIRQ 22
LCODE 23
69 VDD
FIFO SRQ 24
67 ENC
STATS R 25
VDD 26
66 GND
GND 27
GND 28
64 VDD
VDD 29
DADR8 30
62 VDD
68 VCLKO
65 STALL
63 GND
–45–
DDAT0 60
DDAT1 59
DDAT2 58
DDAT3 57
DDAT4 56
DDAT5 55
DDAT6 54
DDAT8 52
DDAT7 53
DDAT10 50
DDAT9 51
DDAT11 49
DDAT12 48
DDAT13 47
DDAT14 46
VDD 44
DDAT15 45
WE 42
VDD 43
RAS 40
CAS 41
GND 39
DADR0 38
DADR1 37
DADR2 36
DADR3 35
DADR5 33
DADR4 34
DADR6 32
DADR7 31
61 GND
*APPLY A 10kV PULL DOWN RESISTOR TO THIS PIN
REV. 0
75 VSYNC
ADV611/ADV612
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
120-Lead LQFP
(ST-120)
C3399–3–1/99
0.638 (16.20)
0.630 (16.00) SQ
0.622 (15.80)
0.559 (14.20)
0.551 (14.00) SQ
0.543 (13.80)
0.063 (1.60)
MAX
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
120
91
1
90
SEATING
PLANE
0.457
(11.6)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
MAX
30
61
60
31
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.006 (0.15)
0.002 (0.05)
0.008 (0.20)
0.004 (0.09)
0.016 (0.40)
BSC*
0.009 (0.23)
0.007 (0.18)
0.005 (0.13)
78
3.58
08
* THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.07 mm
LATERAL TO THE PINS TRUE POSITION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
ORDERING GUIDE
Part Number
Ambient Temperature Range1
Package Description
Package Options2
ADV611JST
ADV612BST3
0°C to +70°C
–25°C to +85°C
120-Lead LQFP
120-Lead LQFP
ST-120
ST-120
PRINTED IN U.S.A.
NOTES
1
J = Commercial temperature range (0°C to +70°C).
2
ST = Plastic Thin Quad Flatpack.
3
B = Standard Industrial Temperature Range (–25°C to +85°C).
–46–
REV. 0