ETC GF9101

MultiGEN ™ GF9101 High
Performance Multirate Digital Filter
DATA SHEET
DESCRIPTION
• highly optimized & flexible architecture for multirate
FIR filtering applications
The GF9101 is a high performance multirate digital filter
which can be programmed to implement a wide range of
signal processing functions using both symmetrical and
asymmetrical filter structures. It is composed of a 12-tap
FIR filter with internal RAM to hold up to 108 individual
filters. An externally controlled address bus selects one of
the 108 filters in each clock cycle. Pipelined architecture
allows cascading of up to three devices with no additional
hardware.
• implements dual 12 tap filters operating at 40 MHz or
single 23 or 24 tap filter operating at 20 MHz maximum
data rate
• stores up to 108 fully-programmable 12 tap filters with
12 bit coefficients at each tap, dynamically
addressable in each clock cycle
• 3 flexible memory loading modes
• supports both symmetrical and asymmetrical FIR
filters
Two 10-bit input shift registers are provided for multiplexed
filtering applications. The 12-bit coefficients can be
programmed in serial, high speed parallel or
microprocessor modes. In the high speed parallel mode,
any one of the 108 filters can be reprogrammed in 18 clock
cycles.
• 40 MHz maximum computation and input/output data
rates
ORDERING INFORMATION
• 20 bit pipeline for cascading up to 3 devices
• 20 bit output accumulator
• filter output negate and zero controls
APPLICATIONS
PART NUMBER
PACKAGE
TEMPERATURE
Video rate conversion; High performance FIR filters;
Adaptive digital filters; Video encoding; Digital modulation
GF9101 - CMQ
160 pin Metal Quad
0° to 70°C
1
0
+10
DATA–A–IN
ENA
+10
DATA–B–OUT
R
TAP TAP
ENB
+10
DATA–A–OUT
+10
R
SEL–A/B
R
ENC
R
COEF–ADDR
R
TAP
TAP
CELL
CELL CELL
1
2
DATA–B–IN
CELL
12
11
7
7
Σ
±14.11
ZERO
R
NEGATE
R
4R
±13.6 TRUNCATED
DELAY
1,3,4,5
R
2
DELAY SEL
±13.6
CONFIGURATION
REGISTER
DATA B SEL
±13.6
CARRY
IN
±13.6
PIPELINE–IN
R
±13.6
0
1
FB–SEL
±13.6
+
R
±13.6
PIPELINE–OUT
R
BLOCK DIAGRAM
Revision Date: July 1999
Document No. 520 - 64 - 7
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GF9101
FEATURES
I/O DESCRIPTION
GF9101
SYMBOL
PIN NO.
TYPE
DESCRIPTION
VDD
1, 10, 20, 29, 40, 41,
59, 69, 80, 81, 90, 99,
109, 120, 121, 129,
140, 150, 160
+5 V power supply pins. 0.1µF capacitors between the VCC and GND pins
are recommended.
GND
3, 6, 8, 19, 33, 36, 39,
46, 49, 60, 73, 76, 79,
83, 86, 88, 100, 113,
116, 119, 122, 125,
139, 153, 155, 159
Device ground.
CLK_IN
138
I
System clock. All inputs except for CONFIGURE, and all internal registers are
clocked on the rising edge of CLK_IN.
DATA_A_IN (9-0)
127, 128, 130-137
I
Input data to registers A0 - A11. 9 bit signed or 10 bit unsigned data.
DATA_B_IN (9-0)
141-149, 151
I
Input data to registers B11 - B0. 9 bit signed or 10 bit unsigned data.
ENA
23
I
Shift enable for A0 - A11. Enables shifting of A registers when high.
ENB
24
I
Shift enable for B0 - B11. Enables shifting of B registers when high.
ENC
25
I
Enable for C0-C11. Enables C registers when high. The C registers transfer
data from either the A or B registers depending on the state of SEL_A/B.
SEL_A/B
22
I
Selects A or B registers. Selects registers A when high or registers B when
low to be transferred to the C registers.
96-98, 101-105
I
Data bus for coefficients and configuration register:
COEF_DATA (7-0)
a) Parallel and microprocessor loading modes : COEF_DATA (7-0) is used to
load 8 bit data into internal RAM.
b) Serial Loading mode: COEF_DATA (7) is used to serially load the internal
RAM.
c) Configuration mode: COEF_DATA (6-0) are inputs to the CONFIGURATION
register.
COEF_ADDR (9-0)
78, 77, 75, 74, 72, 47,
45-42
I
Address bus for internal RAM (address 0 —> 107):
a) Run mode: COEF_ADDR (6-0) selects one of the 108 sets of 12 coefficients
in the internal RAM.
b) Parallel and micro-processor loading modes: Selects the internal RAM
address for the 8-bit data loading COEF_DATA (7-0).
COEF_WR
17
I
Enable for COEF_DATA (7-0). LOAD_EN must be enabled for COEF_WR to
work:
a) Parallel and micro-processor loading modes : Enables COEF_DATA (7-0)
registers or loading 8 bit data in internal RAM.
b) Serial Loading mode: On a high to low transition, a one bit data gets
clocked in to the internal RAM through COEF_DATA bit 7.
LOAD_EN
18
I
Used during loading mode. This signal selects a particular GF9101 device
when 2 or more share the same bus for loading. The particular GF9101
device is selected when set low. LOAD_EN must be enabled for COEF_WR.
For a single GF9101 using the serial loading, this pin can be set low.
NEGATE
126
I
This signal negates the filter sum before it enters the pipelined output section
when high.
ZERO
123
I
Zeros filter sum before it enters the pipelined output section when low.
FB_SEL
124
I
Feedback select. Selects data in PIPELINE_IN when low or filter sum in
PIPELINE_OUT when high to the input of the output accumulator.
2
520 - 64 - 7
I/O DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
21
I
GF9101 reset/configure. Resets the GF9101 when high for at least one clock
period. Loads COEF_DATA (6-0) into the CONFIGURATION register on a high
to low transition. This bit is set low in run mode. When CONFIGURE is high,
the GF9101 is reset but the values in the internal RAM and registers in the run
mode sections are not altered. This means that the GF9101 may be
reconfigured after the internal RAM has been loaded.
PIPELINE_IN (19-0)
38,37, 35, 34, 32-30,
28-26, 15-11, 9, 7, 5,
4, 2
I
Pipeline input. Input to the output accumulator when FB_SEL is low.
DATA_A_OUT (9-0)
71, 70, 68-61
O
Output data from register A11.
DATA_B_OUT (9-0)
58-50, 48
O
Output data from register B0.
PIPELINE_OUT (190)
82, 84, 85, 87, 89, 9195, 106-108, 110112, 114, 115, 117,
118
O
Pipeline output. Output of the accumulator or PIPELINE_IN depending on
FB_SEL.
16
O
CONFIGURE
S_LOAD_CMP
Serial loading complete.
a) Serial loading mode: When high, indicates that all the internal RAM has
been loaded.
SCAN_IN, SCAN_EN
TEST
POUT, SCANOUT
157, 156
Set low.
158
Set high.
152, 154
No Connect.
Note: All unused inputs of the GF9101 should be connected to GND
GF9101 OPERATION
When CONFIGURE is high, the GF9101 is reset but the
values in the internal RAM and registers in the run mode
sections are not altered. This means that the GF9101 may
be reconfigured after the internal RAM has been loaded.
The GF9101 has two operating modes: the load mode and
the run mode. In the load mode, the coefficients for the
filters are written to the internal RAM. In the run mode, the
GF9101 is used to filter signals.
MEMORY LOADING
Before the GF9101 can filter signals, two steps must be
performed:
The GF9101 contains 12 tap cells with 108 12-bit memory
locations for each tap. When loading the memory, the tap
cells must be viewed as 6 memory banks with 108 24-bit
memory locations in each bank. Each memory bank is
assigned to a pair of tap cells as shown in Table 2.
1. CONFIGURATION - is accomplished by writing one 7 bit
word into the CONFIGURATION REGISTER. This register
holds static operating parameters that affect both the
load mode and the run mode.
During configuration, either the parallel, microprocessor, or
serial loading is selected. When in the load mode, the
memory outputs are undefined. Please refer to the GF9101
block diagram and notice that, even though the memory
outputs are undefined, several valid outputs may be in the
processing section below the multipliers and can exit the
GF9101 correctly. This would be useful for adaptive filtering
where the tap memories can be changed while the GF9101
outputs are still valid. During power up, the internal RAM of
the GF9101 is in a random state, and is not intialized to
zero.
2. MEMORY LOADING - is done after configuration. The
internal RAM must be loaded with at least one of the 108
filter coefficient sets before signals can be processed.
CONFIGURATION
The GF9101 is reset by holding CONFIGURE high for at
least one clock cycle. Configuration occurs upon a high to
low transition on the CONFIGURE pin. This transition
registers COEF_DATA (6-0) into the CONFIGURATION
REGISTER. Table 1 shows the meaning of each bit in the
CONFIGURATION REGISTER.
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520 - 64 - 7
GF9101
PIN NO.
PARALLEL LOADING
GF9101
TABLE 1: Configuration Register Format
CONFIGURATION
REGISTER BIT
COEF_DATA(6-0)
MEANING
0
MODE A (1 if A input signed, 0 if unsigned)
1
MODE B (1 if B input signed, 0 if unsigned)
3, 2
If parallel loading is selected, both the COEF_WR pin and
the LOAD_EN pin determine whether the GF9101 is in the
load mode. When COEF_WR and LOAD_EN are both low,
the load mode is selected, the run mode is disabled, and
writes to memory can occur. Parallel loading is random
access and synchronous.
DELAY_SEL selects delay for pipelining:
4
Bits 3, 2
Delay in CLK_IN cycles
0, 0
1
0, 1
3
1, 0
4
1, 1
5
Data is written through COEF_DATA (7-0) and its destination
is determined by COEF_ADDR (9-0). Coefficient memory is
loaded by writing 8 bits at a time, first to two temporary
registers (bits 15 -0) and finally to the desired memory bank
(bits 23-0). Each memory bank word is loaded in three
clock cycles. COEF_ADDR (9-7) defines the address
location for temporary registers (TEMP_REG_A and
TEMP_REG_B) and memory banks. COEF_ADDR (6-0)
determines the filter coefficient address (0 -107) in the
internal RAM. COEF_ADDR (6-0) must be less than 108. In
Table 3, COEF_ADDR (9-7) determines the following:
DATA_B_SEL 0 selects B12 for two 12 tap
filters or one 24 tap filter by externally
connecting DATA_A_OUT to DATA_B_IN.
DATA_B_SEL 1 selects A12 for a 23 tap
filter.
6,5
TABLE 3: Temporary Loading Registers and Memory Banks
COEF_ADDR(9-7)
(binary)
LOAD MODE SELECT (see below)
Bits 6, 5
Loading mode
0, 0
Serial
0, 1
Parallel
1, 0
Microprocessor
1, 1
Reserved
TABLE 2: Memory Locations for Internal RAM
DESTINATION
NUMBER OF BITS
111
TEMP_REG_B
8 (15-8)
110
TEMP_REG_A
8 (7-0)
101
MB5
100
MB4
24 (23-0)
011
MB3
24 (23-0)
010
MB2
24 (23-0)
1
24 (23-0)
MEMORY BANKS (BITS)
TAPS (BITS)
001
MB1
24 (23-0)
0 (23-12)
0 (11-0)
000
MB0
24 (23-0)
0 (11-0)
2 (11-0)
1 (23-12)
3 (11-0)
1 (11-0)
4 (11-0)
2 (23-12)
5 (11-0
TEMP_REG_A and TEMP_REG_B temporarily hold memory
bits, (7-0) and (15-8) respectively. Three 8 bit writes are
necessary to write one 24-bit memory as follows:
2 (11-0)
6 (11-0)
1. Load COEF_DATA (7-0) into TEMP_REG_A
3 (23-12)
7 (11-0)
2. Load COEF_DATA (7-0) into TEMP_REG_B
3 (11-0)
8 (11-0)
4 (23-12)
9 (11-0)
3. Load COEF_DATA (7-0), TEMP_REG_B (7-0), and
TEMP_REG_A (7-0) into the selected memory bank, MB0MB5 (23-0).
4 (11-0)
10 (11-0)
5 (23-12)
11 (11-0)
5 (11-0)
12 (11-0)
NOTE 1: Memory Bank No. 5
While COEF_ADDR (9-7) selects MB0-MB5 for writing,
COEF_ADDR (6-0) selects the memory bank location that
the 24-bit word is written into. Parallel loading is
synchronous with CLK_IN. When COEF_WR and LOAD_EN
are both low, 8-bit words will be written on the rising edge of
CLK_IN. Consecutive writes may be done indefinitely by
keeping COEF_WR and LOAD_EN low. A parallel loading
timing diagram is shown in Figure 1.
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520 - 64 - 7
The timing diagram shown in Figure 1 loads the memories shown in Table 4:
TABLE 4: Memory Loaded into Internal RAM in Parallel Load Mode
12-bit WORD IN HEX.
MEMORY BANK
1 (0)
FB2
MB0
2 (0)
EF4
MB0
11 (107)
CCC
MB5
12 (107)
DDD
MB5
GF9101
TAP (location)
CONFIGURE
LOAD_EN
COEF_WR
COEF_DATA
(7-0)
COEF_ADDR
(9-0)
F4
2E
FB
DD
CD
CC
XX
300
380
000
36B
3EB
2EB
XX
XX
XX
CLK_IN
Fig. 1 Parallel Loading Timing Diagram
The address generated is shown in Table 5.
Timing for the parallel loading signals is the same as that
for other synchronous inputs.
TABLE 5: Address Generation for Parallel Loading Example
COEF_ADDR
(9-7) IN BINARY
COEF_ADDR
(6-0) IN HEX
COEF_ADDR
(9-0) IN HEX
TEMP_REG_A
110
X
300
TEMP_REG_B
111
X
380
MB0
000
0
000
TEMP_REG_A
110
X
36B or 300
TEMP_REG_B
111
X
3EB or 380
MB5
101
6B
2EB
DESTINATION
MICROPROCESSOR LOADING
If microprocessor loading is selected, the LOAD_EN pin
alone determines the run mode or the load mode. When
LOAD_EN is low, the load mode is selected, the run mode
is disabled, but a write will not occur until COEF_WR is low.
Microprocessor loading is random access and
asynchronous. Like parallel loading, microprocessor
loading uses COEF_DATA (7-0) and COEF_ADDR (9-0) to
write three 8-bit words for each 24-bit memory written.
Addressing is the same as for parallel loading. In
microprocessor mode, at least one set of filter coefficients
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520 - 64 - 7
SERIAL LOADING
need to be loaded into the internal RAM. If location 0 is
used for filtering, MB0 > MB5 must be loaded for this
location. The example shown in Figure 2 loads the value
BBH into TEMP_REG_A.
Serial loading is sequential and synchronous. If serial
loading is selected the GF9101 will not enter the run mode
until the entire serial load sequence is completed at which
time the S_LOAD_CMP signal will go high. A bit will be
written each time LOAD_EN is low and COEF_WR makes a
high to low transition. Once the GF9101 is configured for
serial loading, 24 x 108 x 6 =15552 bits must be written
before the run mode is entered automatically. The 15552
bits must be entered in the order defined in Table 6. MB0 is
loaded first from RAM location 0 starting to fill the first 12
bits of tap 2. MB5 RAM location 107, tap 11 is loaded last.
COEF-WR
COEF_DATA
(7-0)
BBH
COEF_ADDR
(9-0)
300H
When the serial load sequence is completed,
S_LOAD_CMP will go high and the run mode will be active.
Below is a serial loading timing diagram. This example
shows the serial loading start-up sequence. Notice that the
falling edge of COEF_WR is used to register the serial data.
The frequency of COEF_WR should be ≤1/4 CLK_IN
frequency.
Fig. 2 Microprocessor Loading Timing Diagram
TABLE 6: Serial Mode Loading Order
Memory Bank 1
Memory Bank 5
TAP 2
TAP 1
TAP4
TAP 3
TAP12
1,2,3 .... 12
13 ........ 24
2593 ............................. 2617
5185 ............................. 5208
0,1,2 .... 11
0 .......... 11
0 .......... 11
0 .......... 11
0 .......... 11
TAP 11
0 .......... 11
2618 ............................. 2642
5209 ............................. 5233
0 .......... 11
0 .......... 11
0 .......... 11
0 .......... 11
..........
..........
..........
..........
..........
0 .......... 11
...............
..........
25 .................................. 48
0 .......... 11
2568 ............................. 2592
5160 ............................. 5184
15528 ...........................15552
0,1,2 .... 11
0 .......... 11
0 .......... 11
0 .......... 11
...............
0 .......... 11
CONFIGURE
LOAD_EN
COEF_WR
COEF_DATA (7)
BIT 1
BIT 2
BIT 15551
BIT 3
CLK_IN
S_LOAD_CMP
Fig. 3 Serial Mode Timing Diagram
6
520 - 64 - 7
Ram
Location
BIT 15552
0 .......... 11
0
1
..........
Memory Bank 0
...............
GF9101
LOAD_EN
107
FILTER ARCHITECTURE
For the following discussion on filter architecture, refer to the GF9101 Block Diagram and Figure 4.
+10.0
DATA _A_IN
+10.0
TO NEXT TAP
A REG
R
B REG
+10.0
DATA_B_IN
+10.0
TO NEXT
TAP
ENB
GF9101
ENA
R
1
R
SEL–A/B
0
+10.0
C REG
R
ENC
+10.0
MODE A
CONFIGURATION
REGISTER
MODE B
0
MULT
MODE
REG
1
SIGNED /
UNSIGNED
+10.0 / ±9.0
7
COEF–ADDR
R
108 x12 ±0.11
COEF
REG
COEF
REG
±0.11
±10.11
MULT
REG
±10.11
TO ADDER
Fig. 4 Tap Cell (1-12)
COEFFICIENT MULTIPLICATION AND ADDITION STAGE
mismatch will occur. One needs to be cautious while using
the GF9101 as two separate filters with MODE A and MODE
B not in the same state (data entering REG_A is signed/
unsigned while in REG_B it is the opposite of REG_A) . If
ENC is low and SEL_A/B, changes state, a signed/unsigned
mismatch will occur. To avoid an error under these
circumstances, always make ENC high after a SEL_A/B,
state change.
Two shift registers, A and B, are used to shift input data
through the GF9101. Notice that if DATA_B_SEL was set low
during configuration, data applied at DATA_A_IN enters at
tap 1 and exits from tap 12, while data applied at
DATA_B_IN enters at tap 12 and exits from tap 1. This gives
two 12 tap filters. If DATA_B_SEL was set high during
configuration, data applied at DATA_A_IN enters at tap 1,
reverses direction at tap 12 (bypasses REG_12B) and exits
from tap 1 on DATA_B_OUT, while DATA_B_IN is disabled.
This gives a 23 tap filter. ENA and ENB control the shifting
of the input data. The C register holds the next set of 12
input values to be applied to the multipliers.
The input values in the C register are multiplied by the
coefficient values in the COEF register and the result enters
an adder tree . The coefficients that enter the COEF register
are stored in the internal RAM and are selected by the
externally controlled COEF_ADDR (6-0) bus, which is
common to all taps. At the output of the adder tree is the
untruncated sum of taps 1 through 12.
If ENC is high, SEL_A/B, determines whether the A or B shift
register data enters the C register. SEL_A/B, also
determines whether the MODE A or MODE B control signal
enters the MULT_MODE register. The value in the
MULT_MODE register determineswhether theinputdatato
themultiplierisrecognized as signed or unsigned. MODE A
and MODE B are separate, static control signals which
determine signed/unsigned for A or B input data
respectively. They are common to all taps. When using the
GF9101 as a 23 or 24 tap filter (combiningREG_A and
REG_B to get a single filter output), MODE A and MODE B
should be in the same state. If not, a signed/unsigned
This sum is then truncated as shown in the GF9101 Block
diagram. The sum then passes through a variable delay
along with the ZERO and NEGATE signals. The variable
delay is provided so that complementary sums from
cascaded GF9101’s may be added together in the
pipelined output stage. The ZERO signal zeros the sum and
the NEGATE signal negates the sum.
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520 - 64 - 7
GF9101
PIPELINE_IN, PIPELINE_OUT STAGE
and BURST signals (i.e. for 4:2:2 to 4ƒSC rate conversion).
This can be achieved by clocking in the SYNC and BURST
signals from an external PROM connected to the
PIPELINE_IN.
The calculated filter sum from the adder tree and delay
enters into the pipelined output stage. Figure 5 shows the
block diagram for the pipelined structure. FB_SEL
determines whether the sum is added to the current
PIPELINE_OUT or the registered PIPELINE_IN. The result is
then registered at PIPELINE_OUT. When using one GF9101,
this configuration can be used to add two partial filter sums
from the A and B registers. Another application would be to
use the PIPELINE_IN port for adding DC offset or SYNC
By connecting PIPELINE_OUT of one GF9101 device to
PIPELINE_IN of another, up to three GF9101’s may be
cascaded to form larger filters.
FILTER–SUM
20
PIPELINE–IN
20
20
R
PROM
0
+
1
PIPELINE–OUT
R
20
FB–SEL
CLK–IN
R
GF9101
Fig. 5 Block Diagram for Pipelined Output Stage
CLK_IN
FILTER_SUM
XXX
SUM 1
XXX
SUM 2
XXX
SUM 3
003H
PIPELINE_IN
FB_SEL
XXX
SUM 1
PIPELINE_OUT
SUM 1
+
SUM 2
XXX
003H
+
SUM 3
XXX
Fig. 6 Timing Diagram for the Pipelined Output Stage
APPLICATION NOTES
Video applications for the GF9101 include video rate
conversion and high performance FIR filters. The following
section presents a number of examples which show odd
and even symmetric and asymmetric filters.
ODD-TAP SYMMETRIC FILTER
multiplied by the data in reg. A_12 and reg.B_12 is
bypassed. The data is shifted into the register by clocking
ENA and ENB at the same time at half the CLK_IN
frequency. The filter timing is shown in Figure 8.
The GF9101 can be configured as an Odd-tap symmetric
filter. A 23-tap odd-symmetric filter using one GF9101 will
be discussed. For an odd-tap symmetric filter, the
configuration word is shown in Table 7.
The maximum data rate using this filter configuration is 20
MHz, where the filter is clocked at twice the data rate of 40
MHz, the frequency of CLK_IN. The filter has input data An
and filter data coefficients Cn (C0 —> C11) as shown in
Figure 7. The input enters the filter at DATA_A_IN and exits
the filter from DATA_B_OUT. The coefficient C11 is only
8
520 - 64 - 7
TABLE 7: Configuration Word for an Odd-Tap Symmetric Filter
BIT
NO.
CONFIGURATION
WORD
0
1
1
1
2
0
3
0
4
1
23-tap filter, bypass reg.
B_12
5
X
Depending on loading mode.
6
X
(See Table 1)
DESCRIPTION
Data A and B are both
signed data2
One register delay
GF9101
NOTE:
2: Bits 0 and 1 should have the same value for a 23 or 24 tap
filter.
TABLE 8: Internal RAM Addresses and Contents
COEF_ADDR (6-0)
MEMORY CONTENTS
00H
12 coefficients, for tap 1—> tap 12
C11
C10
C9
C3
C2
C0
C10
C9
C3
C4
C1
C8
C5
C4
C8
C7
A23
A25
A24
A16
A17
A21
A18
A20
A19
C0
C6
A10
A22
(a) Filter Coefficients Cn
C1
C5
C7
C6
C2
A12
A14
A4
A9
A11
A15
A5
A8
A13
A6
A7
A3
(b) Input Data An
A0
A2
A1
Fig. 7 Input Data An and Coefficients Cn
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DATA_A_IN
0
1
2
3
4
5
6
7
8
9
10
11
CLK_IN
GF9101
ENA
ENB
SEL_A/B
B
A
B
A
COEF_ADDR
(6 - 0)
B
A
B
A
B
A
B
A
00H
ENC
LOAD_EN
ZERO
CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 8 Timing Diagram for a 23-Tap Odd-Symmetric Filter
Assuming that the data A0 —> A21 has already been
shifted into the filter registers, by clocking ENA and ENB the
data A22 enters DATA_A_IN (Figure 9a). During the first
CLK_IN rising edge, the data in the A registers (A22 —>
A11) are selected by SEL_A/B , to be multiplied by the
coefficients, C0 —> C11 in memory location 0,
COEF_ADDR 00H . During the second CLK_IN rising edge
the data in B registers (A0 —> A10) are selected by SEL_A/
B, to be multiplied by the coefficients, C0 —>C10 (Figure
DATA–A–IN
A22
A20
A21
A1
A0
DATA–B–OUT
A12
9b). After passing through the adder tree and the delay (4
CLK_IN cycles in total), the two sums are added in the
pipeline section of the filter. FB_SEL selects PIPELINE_IN
during CLK_IN period 5, at which time a DC offset could be
introduced at PIPELINE_IN to be added to the sum. During
CLK_IN period 6, FB_SEL selects PIPELINE_OUT and the
final filter sum is calculated and passed through to
PIPELINE_OUT.
A11
DATA–A–IN A22
A21
A20
DATA–B–OUT
A0
A1
x
C1
x
C2
x
A11
A10
A2
A10
A2
C0
C0
A12
C10
x
C11
x
C1
x
C2
x
C10
x
C11
x
x
Σ
Σ
PIPELINED
ADDER
PIPELINED
ADDER
(A22 x C0) + (A21 x C1) + (A20 x C2) +...+(A12 x C10) + (A11 x C11)
+
(A22 x C0) + (A21 x C1) + (A20 x C2) +...+(A12 x C10) + (A11 x C11)
(A0 x C0) + (A1 x C1) + (A2 x C2) +...+(A10 x C10)
Fig. 9a Data Flow Diagram for a 23 Tap Odd-Symmetric Filter
Fig. 9b Data Flow Diagram for a 23 Tap Odd-Symmetric Filter
EVEN-TAP SYMMETRIC FILTER
PIPELINE_OUT. For a 24-tap symmetric
configuration word is shown in Table 9.
The GF9101 can be configured as an even-tap symmetric
filter. A 24-tap symmetric filter can be configured using one
GF9101 by connecting the outputs of DATA_A_OUT to the
inputs of DATA_B_IN and taking the output at
10
520 - 64 - 7
filter,
the
TABLE 9: Configuration Word for a 24-tap Symmetric Filter
BIT
NO.
CONFIG.
WORD
0
1
1
1
2
0
3
0
4
0
24-tap filter, connect the outputs of
DATA_A_OUT to the inputs of DATA_B_IN.
5
X
Depending on the loading mode
6
X
See Table 1
DESCRIPTION
3
Data A and B are both signed data
GF9101
One register delay
NOTE
3. Bits 0 and 1 should have the same value for a 23 or 24 tap filter
The filter coefficients are shown in Figure 10. The timing is verysimilar to that of the even-symmetric case.
C11 C
11
C10
C10
C9
C4
C3
C0
C1
C9
C5
C5
C4
C3
C0
C2
C2
C6
C8
C8
A17
A18
C1
C7
C7
A19
C6
(a) Filter Coefficients Cn
A7
A16
A8
A15
A9
A6
A5
(b) Input Data An
A20
A24
A21
A23
A22
A4
A10
A14
A13
A11
A0
A3
A12
A1
A2
Fig. 10 Input Data An and Coefficients Cn
ASYMMETRIC FILTER
The GF9101 can be used as a 24-tap asymmetric filter by
configuring it the same way as the even-symmetric case.
The difference is in the memory locations since the
asymmetric case uses 24 different coefficients, i.e. two sets
of filter coefficients. The filter coefficients and the memory
locations are shown in Table 10.
TABLE 10:Internal RAM Address & Contents for a 24-tap
Asymmetric Filter
COEF_ADDR (6-0)
MEMORY CONTENTS
00H
First set of 12 coefficients, C0 —> C11
01H
Second set of 12 coefficients, C23 —> C12
The timing diagram is shown in Figure 11. The data flow
diagrams are shown in Figures 11a and 11b.
11
520 - 64 - 7
DATA_A_IN
0
1
2
3
4
5
6
7
8
9
10
GF9101
CLK_IN
ENA
ENB
SEL_A/B
B
COEF_ADDR
(6-0)
01H
A
B
A
B
A
B
A
B
00H
01H
00H
01H
00H
01H
00H
A
01H
B
01H
00H
ENC
LOAD_EN
ZERO
CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 11 Timing Diagram for a 24 Tap Asymmetric Filter
DATA–A–IN
DATA–A–IN
A23
A22
A21
A0
A1
A13
A23
C0
x
C1
x
A10
A2
C2
x
C10
A21
A0
A1
A13
A12
A12
DATA–B–OUT
DATA–B–OUT
A22
x
C11
A11
A10
A2
A11
C23
x
x
C22
x
C21
x
C13
x
C12
x
Σ
Σ
PIPELINED
ADDER
PIPELINED
ADDER
(A0 x C23) + (A1 x C22) + (A2 x C21) +...+(A10 x C13) + (A11 x C12)
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
+
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11a Data Flow Diagram for a 24 Tap Asymmetric Filter
Fig. 11b Data Flow Diagram for a 24 Tap Asymmetric Filter
CASCADING
register of the same device. The contents of the
configuration register will be different for the two devices to
compensate for a three register delay introduced when two
GF9101's are cascaded to get a 48 tap filter. The
configuration register contents are shown in Table 11.
In the previous section, configuration for a 24 tap filter using
only one GF9101 was shown. To realize higher order (>24)
filters, up to three GF9101's would allow a 72 tap FIR filter to
be configured without any additional hardware. In Figure
13, two GF9101's are cascaded together to obtain a 48 tap
filter. The data enters DATA_A_IN (device number 1) and
exits from DATA_B_OUT (device number 1). In device
number 2, the DATA_A_OUT bus is connected to
DATA_B_IN in order to feed the data back in to the B12
12
520 - 64 - 7
For the 48 tap filter, input data A n and coefficients C n are
shown in Figure 12. The pipelined output section of the 48
tap filter is shown in Figure 14. Note that two register delays
are introduced due to R2 and R3 between the accumulators
of device number 1 and number 2. An additional delay is
introduced when the filter-sum is fed back to be added to
the next sum by selecting FB_SEL_1. The timing diagram
for the 48 tap asymmetric filter is shown in Figure 15. The
processing clock runs at twice the data rate since the A and
B registers of the GF9101 are multiplexed internally..
TABLE 11 Configuration Word for the Cascaded GF9101’s
DEVICE NO. 2
BIT NO.
CONFIG.
WORD
CONFIG.
WORD
0
1
1
1
1
1
2
0
0
3
0
1
4
0
0
Using each device as 2 x 12 tap filters. Note that in device no. 2
DATA_A_OUT is externally connected to DATA_B_IN.
5
0
0
Assuming serial load mode selected for both devices.
6
0
0
GF9101
DEVICE NO. 1
DESCRIPTION
Data A and B are both signed data.
1 clock cycle delay in device no. 1 and 4 clock delay in device no. 2
C39
C6
C0
C7
C36
C37
C38
C40 C
41
C42
C47
C43 C44 C45 C46
C5
C1 C
2
C4
C3
A44
A45
A47
A46
A10
A43
A11
A42
A41
A9
A8
A7
A6
A0
A5
A40
A1
A4
A3
Fig. 12 Input Data An and Coefficients Cn
13
520 - 64 - 7
CONFIG
COEFWR
CLK_IN
ADDRESS [6..0]
OFFSET [7..0]
+5V
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0
22
ENB
SEL A/B
138
25
78
77
75
74
72
47
45
44
43
42
96
97
98
101
102
103
104
105
38
37
35
34
32
31
30
28
27
26
15
14
13
12
11
9
7
5
4
2
58
57
56
55
54
53
52
51
50
48
24
ENA
+5V
21
C
O
CLK N
F
I
G
ENC
COEF_AD9
COEF_AD8
COEF_AD7
COEF_AD6
COEF_AD5
COEF_AD4
COEF_AD3
COEF_AD2
COEF_AD1
COEF_AD0
COEFD7
COEFD6
COEFD5
COEFD4
COEFD3
COEFD2
COEFD1
COEFD0
PL_IN19
PL_IN18
PL_IN17
PL_IN16
PL_IN15
PL_IN14
PL_IN13
PL_IN12
PL_IN11
PL_IN10
PL_IN9
PL_IN8
PL_IN7
PL_IN6
PL_IN5
PL_IN4
PL_IN3
PL_IN2
PL_IN1
PL_IN0
SEL_A/B
DB_OUT9
DB_OUT8
DB_OUT7
DB_OUT6
DB_OUT5
DB_OUT4
DB_OUT3
DB_OUT2
DB_OUT1
DB_OUT0
ENB
DA_IN9
DA_IN8
DA_IN7
DA_IN6
DA_IN5
DA_IN4
DA_IN3
DA_IN2
DA_IN1
DA_IN0
ENA
17
W
R
E
N
18
C
O
E
F
L
O
A
D
158
T
E
S
T
N
157
I
N
S
C
A
N
126
N
E
G
A
T
E
124
S
E
L
F
B
82
84
85
87
89
91
92
93
94
95
106
107
108
110
111
112
114
115
117
118
141
142
143
144
145
146
147
149
151
151
71
70
68
67
66
65
64
63
62
61
CE
OE
XC1736
CLK
DATA
SERIAL PROM
123
N
Z
E
R
O
SLOADCMP
156
E
N
S
C
A
N
1
GF9101
PL_OUT19
PL_OUT18
PL_OUT17
PL_OUT16
PL_OUT15
PL_OUT14
PL_OUT13
PL_OUT12
PL_OUT11
PL_OUT10
PL_OUT9
PL_OUT8
PL_OUT7
PL_OUT6
PL_OUT5
PL_OUT4
PL_OUT3
PL_OUT2
PL_OUT1
PL_OUT0
DB_IN9
DB_IN8
DB_IN7
DB_IN6
DB_IN5
DB_IN4
DB_IN3
DB_IN2
DB_IN1
DB_IN0
DA_OUT9
DA_OUT8
DA_OUT7
DA_OUT6
DA_OUT5
DA_OUT4
DA_OUT3
DA_OUT2
DA_OUT1
DA_OUT0
NEGATE
127
128
130
131
132
133
134
135
136
137
23
ZERO
DATA_IN [9..0]
FB_SEL-1
6
7
+5V
CONFIG
COEFWR
CLK_IN
ADDRESS [6..0]
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0
+5V
22
ENB
SEL A/B
138
25
78
77
75
74
72
47
45
44
43
42
96
97
98
101
102
103
104
105
38
37
35
34
32
31
30
28
27
26
15
14
13
12
11
9
7
5
4
2
58
57
56
55
54
53
52
51
50
48
24
ENA
127
128
130
131
132
133
134
135
136
137
23
+5V
C
O
CLK N
F
I
G
ENC
21
COEF_AD9
COEF_AD8
COEF_AD7
COEF_AD6
COEF_AD5
COEF_AD4
COEF_AD3
COEF_AD2
COEF_AD1
COEF_AD0
COEFD7
COEFD6
COEFD5
COEFD4
COEFD3
COEFD2
COEFD1
COEFD0
PL_IN19
PL_IN18
PL_IN17
PL_IN16
PL_IN15
PL_IN14
PL_IN13
PL_IN12
PL_IN11
PL_IN10
PL_IN9
PL_IN8
PL_IN7
PL_IN6
PL_IN5
PL_IN4
PL_IN3
PL_IN2
PL_IN1
PL_IN0
SEL_A/B
DB_OUT9
DB_OUT8
DB_OUT7
DB_OUT6
DB_OUT5
DB_OUT4
DB_OUT3
DB_OUT2
DB_OUT1
DB_OUT0
ENB
DA_IN9
DA_IN8
DA_IN7
DA_IN6
DA_IN5
DA_IN4
DA_IN3
DA_IN2
DA_IN1
DA_IN0
ENA
18
E
N
L
O
A
D
W
R
C
O
E
F
17
T
E
S
T
N
158
I
N
S
C
A
N
157
E
N
S
C
A
N
2
GF9101
4
3
2
1
123
82
84
85
87
89
91
92
93
94
95
106
107
108
110
111
112
114
115
117
118
141
142
143
144
145
146
147
149
151
151
71
70
68
67
66
65
64
63
62
61
CE
OE
XC1736
CLK
DATA
SERIAL PROM
124
N
Z
E
R
O
126
S
E
L
F
B
156
N
E
G
A
T
E
SLOADCMP
PL_OUT19
PL_OUT18
PL_OUT17
PL_OUT16
PL_OUT15
PL_OUT14
PL_OUT13
PL_OUT12
PL_OUT11
PL_OUT10
PL_OUT9
PL_OUT8
PL_OUT7
PL_OUT6
PL_OUT5
PL_OUT4
PL_OUT3
PL_OUT2
PL_OUT1
PL_OUT0
DB_IN9
DB_IN8
DB_IN7
DB_IN6
DB_IN5
DB_IN4
DB_IN3
DB_IN2
DB_IN1
DB_IN0
DA_OUT9
DA_OUT8
DA_OUT7
DA_OUT6
DA_OUT5
DA_OUT4
DA_OUT3
DA_OUT2
DA_OUT1
DA_OUT0
GF9101
NEGATE
14
ZERO
520 - 64 - 7
FB_SEL-2
Fig. 13
6
7
+5V
OUTPUT [11..0]
FILTER–SUM 1
FILTER–SUM 2
20
20
OFFSET [7..0]
R1
20
0
8
Σ
1
R2
R3
20
20
0
20
1
20
Σ
20
12
R4
OUTPUT [11..0]
20
FB–SEL-1
R
FB–SEL-2
R
GF9101
DEVICE No.1
GF9101
GF9101
DEVICE No.2
Fig. 14 Pipelined Output Stages for Two Cascaded GF9101’s
TABLE 12: Internal RAM Address and Contents for a 48-tap Asymmetric Filter using Two Cascaded GF9101’s
COEF_ADDR
INTERNAL RAM CONTENTS
Device No. 1
Device No. 2
00H
C0 —> C11 (registers A1 —> A12)
C12 —> C23 (registers A1 —> A12)
01H
C47 —> C36 (registers B1 —> B12)
C35 —> C24 (registers B1 —> B12)
coefficients should be arranged as shown in Table 12. If a
single source is used for coefficient loading, the LOAD_EN
signal is used to select the appropriate device. Also, the
S_LOAD_CMP signal can be used as an indicator for a
successful load.
Dedicated serial PROM's can be used to load the
coefficients into the internal RAM of each GF9101. Note that
when data is fed back into DATA_B_IN, it enters register
B12 of device number 2. Therefore, while loading the
coefficients into the internal RAM for the B registers the
1
2
3
4
5
6
00H
01H
00H
01H
00H
01H
7
8
00H
01H
9
10
11
12
00H
01H
00H
01H
13
14
CLK_IN
DATA_A_IN
ENA
ENB
SEL_A/B
COEF_ADDR
(6-0)
00H
01H
LOAD_EN
ZERO
CONFIGURE
FB_SEL-1
FB_SEL-2
NEGATE
Fig. 15 Timing Diagram for a 48 Tap Asymmetric Filter
15
520 - 64 - 7
DA-IN9
DA-IN8
DA-IN7
DA-IN6
DA-IN5
DA-IN4
DA-IN3
DA-IN2
DA-IN1
DA-IN0
ENA
DB-IN9
DB-IN8
DB-IN7
DB-IN6
DB-IN5
DB-IN4
DB-IN3
DB-IN2
DB-IN1
DB-IN0
ENB
SELAB
PL-IN19
PL-IN18
PL-IN17
PL-IN16
PL-IN15
PL-IN14
PL-IN13
PL-IN12
PL-IN11
PL-IN10
PL-IN9
PL-IN8
PL-IN7
PL-IN6
PL-IN5
PL-IN4
PL-IN3
PL-IN2
PL-IN1
PL-IN0
COEF-D7
COEF-D6
COEF-D5
COEF-D4
COEF-D3
COEF-D2
COEF-D1
COEF-D0
COEF-AD9
COEF-AD8
COEF-AD7
COEF-AD6
COEF-AD5
COEF-AD4
COEF-AD3
COEF-AD2
COEF-AD1
COEF-AD0
ENC
CLK_IN
21
18
GF9101
160 PIN Metal Quad
+/- 5V
1, 10, 20, 29,
40, 41, 59, 69,
80, 81, 90, 99, 109,
120, 121, 129,
140, 150, 160
GND
3, 6, 8, 19, 33,
36, 39, 46, 49,
60, 73, 76, 79, 83,
86, 88, 100,
113, 116, 119,
122, 125, 139,
153, 155, 159
ABSOLUTE MAXIMUM RATINGS
DA-OUT9
DA-OUT8
DA-OUT7
DA-OUT6
DA-OUT5
DA-OUT4
DA-OUT3
DA-OUT2
DA-OUT1
DA-OUT0
71
70
68
67
66
65
64
63
62
61
DB-OUT9
DB-OUT8
DB-OUT7
DB-OUT6
DB-OUT5
DB-OUT4
DB-OUT3
DB-OUT2
DB-OUT1
DB-OUT0
58
57
56
55
54
53
52
51
50
48
PL-OUT19
PL-OUT18
PL-OUT17
PL-OUT16
PL-OUT15
PL-OUT14
PL-OUT13
PL-OUT12
PL-OUT11
PL-OUT10
PL-OUT9
PL-OUT8
PL-OUT7
PL-OUT6
PL-OUT5
PL-OUT4
PL-OUT3
PL-OUT2
PL-OUT1
PL-OUT0
82
84
85
87
89
81
82
83
84
85
106
106
108
110
111
112
114
115
117
118
SLOADCMP
PARAMETER
VALUE
Supply Voltage
-0.3 to +7.0 V
Input Voltage
-0.3 to (VDD +0.3) V
Short Circuit Duration
1 second
(single output)
Storage Temp
- 40 to +125 C
RECOMMENDED OPERATING CONDITIONS
16
PARAMETER
SYMBOL
LIMIT
UNIT
VDD
+ 3.0 to + 5.5
V
Ambient
TA
0 to +70
C
Junction
TJ
+150
C
DC Supply Voltage
5
VCC= 5 V
TA = 25 C
4
P (W)
GF9101
127
128
130
131
132
133
134
135
136
137
23
141
142
143
144
145
146
147
148
149
151
24
22
38
37
35
34
32
31
30
28
27
26
15
14
13
12
11
9
7
5
4
2
96
97
98
101
102
103
104
105
78
77
75
74
72
47
45
44
43
42
25
138
3
2
1
10
20
30
40
50
60
80
GF9101 Power Consumption vs Clock Rate
17
158
157
156
126
124
123
GF9101 Pin Designations
VDD
VDD
n SUBSTRATE
n SUBSTRATE
p
D1
D1
p
p+
p+
CONTROL
INPUT
n+
n+
D2
n
n
D2
p WELL
p WELL
GND
GND
Fig. 16 Equivalent Input/Output Circuit
16
520 - 64 - 7
70
Frequency (MHz)
DC ELECTRICAL CHARACTERISTICS
VCC = 5V ±5%, TA = 0°C to 70°C unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIL
-
-
1.5
V
Voltage Input HIGH
VIH
3.5
-
-
V
Voltage Output HIGH
VOH
2.4
4.5
-
V
Switching Threshold
VT
-
2.5
-
V
Input Current
IIN
VIN = VDD or VSS
-10
+/-1
10
µA
Output Current HIGH
IOH
PIPELINE_OUT
-
-
2
mA
IOH
DATA_A_OUT, DATA_B_OUT
-
-
1
mA
IOL
PIPELINE_OUT
-
-
2
mA
IOL
DATA_A_OUT, DATA_B_OUT
-
-
1
mA
Quiescent Supply Current
IDD
VIN = VDD or VSS
-
12
-
mA
Output Short Circuit Current
IOS
VDD = Max, VO = VDD
30
75
140
mA
VDD = Max, VO = 0V
25
70
140
mA
CIN
-
4.0
-
pF
COUT
-
3.5
-
pF
-
8
-
ns
Output Current LOW
Input Capacitance
Output Capacitance
GF9101
Voltage Input LOW
SWITCHING CHARACTERISTICS
VCC = 5V ±5%, TA = 0°C to 70°C unless otherwise shown
Output Delay
tD
Setup Time
tS
All Inputs
2
-
-
ns
Hold Time
tH
All Inputs
6
-
-
ns
Clock Rate
ƒMAX
-
-
40
MHz
17
520 - 64 - 7
GF9101 TIMING
T
GF9101
CLK-IN
t1
t2
t3
CONFIGURE
t4
COEF-DATA
(6-0)
t5
Configuration Mode
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
1
CLK_IN duration time (HIGH)
t1
12
ns
2
CLK_IN duration time (LOW)
t2
12
ns
3
CLK_IN period time
T
25
ns
4
CONFIGURE pulse width
t3
T+10
ns
5
COEF_DATA to configure setup time
t4
10
ns
6
COEF_DATA to configure hold time
t5
5
ns
18
520 - 64 - 7
LOAD_EN
COEF_WR
t5
COEF_DATA
(7-0)
t6
GF9101
t7
COEF_ADDR
(9-0)
t8
t3
t2
t1
CLK_IN
t4
Memory Loading - Parallel Interface
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
1
LOAD_EN to CLK_IN set up time*
t1
4
ns
2
LOAD_EN to CLK_IN hold time**
t2
6
ns
3
COEF_WR to CLK_IN set up time*
t3
4
ns
4
COEF_WR to CLK_IN hold time**
t4
6
ns
5
COEF_DATA to CLK_IN set up time
t5
2
ns
6
COEF_DATA to CLK_IN hold time
t6
6
ns
7
COEF_ADDR to CLK_IN set up time
t7
2
ns
8
COEF_ADDR to CLK_IN hold time
t8
6
ns
* to enable loading
** to disable loading
19
520 - 64 - 7
LOAD_EN
t1
t2
t3
COEF_WR
t4
GF9101
t5
COEF_DATA
(7-0)
t6
COEF_ADDR
(9-0)
t7
t8
Memory Loading - Microprocessor Interface
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
1
LOAD_EN to COEF_WR set up time
t1
2
na
2
COEF_WR puls width low
t2
80
ns
3
LOAD_EN to COEF_WR hold time
t3
6
ns
4
COEF_WR pulse width, high
t4
20
ns
5
COEF_DATA to COEF_WR set up time
t5
10
ns
6
COEF_DATA to COEF_WR hold time
t6
10
ns
7
COEF_ADDR to COEF_WR set up time
t7
2
ns
8
COEF_ADDR to COEF_WR hold time
t8
6
ns
20
520 - 64 - 7
t2
t1
LOAD_EN
t3
COEF_WR
t4
BIT 1
BIT 2
BIT 3
BIT 15551
BIT 15552
GF9101
COEF_DATA
(7)
t5
X
CLK_IN
S_LOAD_CMP
Memory Loading - Serial
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
1
LOAD_EN to COEF_WR set up time
t1
4
ns
2
LOAD_EN to COEF_WR hold time
t2
6
ns
3
COEF_WR period
t3
4xT
ns
4
COEF_DATA(7) to COEF_WR set up time
t4
2
ns
5
COEF_DATA(7) to COEF_WR hold time
t5
6
ns
SYMBOL
MIN
CLK_IN
t2
t1
EN A
t3
t4
DATA_A_IN
(9-0)
DATA_A_OUT
(9-0)
Run Mode
DESCRIPTION
MAX
UNIT
1
ENA to CLK_IN set up time
t1
2
ns
2
ENA to CLK_IN hold time
t2
6
ns
3
DATA_A_IN to CLK_IN set up time
t3
2
ns
4
DATA_A_IN to CLK_IN hold time
t4
6
ns
21
520 - 64 - 7
CLK_IN
t1
GF9101
SEL_A/B
t3
t2
ENC
t5
t4
FB_SEL
Run Mode
DESCRIPTION
SYMBOL
MIN
MAX
UNIT
1
SEL_A/B to CLK_IN set up time
t1
2
ns
2
ENC to CLK_IN set up time
t2
2
ns
3
ENC to CLK_IN hold time
t3
6
ns
4
FB_SEL to CLK_IN set up time
t4
2
ns
5
FB_SEL to CLK_IN hold time
t5
6
ns
22
520 - 64 - 7
120
81
121
80
0..................7
COEF–DATA
10......................19
PIPELINE–OUT 9
COEF–ADDR
5
........
0.........................9
PIPELINE–OUT
ZERO
FB–SEL
NEGATE
9
DATA–A–IN
DATA–A–OUT
0
...................
...................
GF9101
9
0
CLK–IN
9
...................
DATA–B–OUT
DATA–B–IN
0
...................
9
........
0
C
O
S
C
N S
L
4
O
F E
O
L
COEF–ADDR
E
I
A
D C G – E E E F
PIPELINE–IN 0
U A N N N C
W 10......................19
M E R /
P N E B A B C R
PIPELINE–IN
0.........................9
160
41
40
1
160 pin Metal Quad Pinout
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Remove ‘Not Recommended for New Designs’ Watermark.
Correct package name to 160 pin Metal Quad.
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ
Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright October 1998 Gennum Corporation. All rights reserved. Printed in Canada.
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