General Purpose Controller / Memory Chip for Hearing Instruments GP521 - DATA SHEET FEATURES An information transfer dialogue consists of the address and data for a register sent to the GP521 and the register contents returned by the GP521. The function controlled by an output of the GP521 is defined by the signal path circuit allowing current controlled parameters. The relationship between the GP521 register addresses and the function on the signal path circuit is defined by a data file in the programming unit. With this format, any software developed for the GP521 can be used for future generations of Gennum’s controller/memory circuits and audio signal path circuits. • general purpose • EEPROM non-volatile memory • 8 programmable current sink (PCS) control outputs • can be configured with 6 PCS outputs for hearing instruments (two switchable, four non-switchable) • status register • data transmission error detection • synchronization of GP521 internal clocks with program unit clock The GP521 uses EEPROM cells as the long term memory element. These cells will retain the stored data when the power supply is disconnected. Each EEPROM cell is combined with a temporary (RAM) memory cell which makes it possible to evaluate various control settings prior to saving them in the long term EEPROM memory. STANDARD PACKAGING • Chip (129 x 112 mils) Au Bump DESCRIPTION The GP521 is a general purpose controller/memory chip intended for use with audio signal path circuits in programmable hearing instruments. The GP521 uses a flexible communication standard which allows room for future growth in programmable functions for hearing instruments. The communication with the program unit is over a bi-directional serial data link. Error detection circuitry is used to avoid undesired changes in programmed settings. The GP521 controls the audio signal path circuit using eight Programmable Current Sinks (PCS). Each PCS has 16 programmable settings. The circuit can be configured for either 6 or 8 PCS outputs. When used with a single pole single throw switch (SPST) under the 6 PCS configuration , it is possible to design a hearing instrument with two programmed settings (i.e. adjusting a low cut filter for either noisy or quiet background environments). The 8 output configuration may be used for circuits that require more programmable but nonswitchable settings. An external reference current is used for the PCS’s so that the PCS outputs can track with the currents in the audio signal path circuit. BLOCK DIAGRAM CONTROL OUTPUTS CONTROL OUTPUTS IO1 IO2 10 4 BIT EEPROM DAC IO3 9 4 BIT EEPROM DAC 8 4 BIT EEPROM DAC IO4 IO5 15 7 4 BIT EEPROM DAC 4 BIT EEPROM DAC IO6 IO7 13 4 BIT EEPROM DAC 12 4 BIT EEPROM DAC IO8 11 4 BIT EEPROM DAC REFERENCE CURRENT V CC GND 3 17 2 DATA SERIAL TO PARELLEL CONVERSION DATA ERROR CHECKING EEPROM VOLTAGE MULTIPLIER CONTROLLER TIMING 1 OSCILLATOR CLOCK I RR STATUS & OPERATION REGISTER 16 14 4 SW OFF Revision Date: May 1998 I 5 N/C N/C 6 OS1 Document No. 510 - 79 - 06 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 Web Site: www.gennum.com E-mail: [email protected] ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE / UNITS Supply Voltage 3 V DC 1 CLOCK IR 17 2 DATA NC 16 IO5 15 3 V CC Min. voltage any pin GND - 200 mV Max. voltage any pin VCC + 200 mV 5 GND 0 to 50 oC 6 OS1 Operating temperature NC 14 4 SWOFF CAUTION GP521 IO6 13 IO7 12 7 IO4 IO8 11 IO1 10 IO3 IO2 9 8 CLASS 1 ESD SENSITIVITY Fig. 1 Chip Pad Diagram ELECTRICAL CHARACTERISTICS Current into IC considered positive. o Conditions: Temperature = 25 C, IR = 4 µA, Vcc = 1.3 V PARAMETER SYMBOL Supply Voltage VCC Supply Current: I cc CONDITIONS MIN. TYP. - 1.3 3 Normal operation mode - - 25 µA Program mode - - 1 mA 1000 - - cycles - - 200 mV - - V - 6 50 kHz - - 14 µA 400 500 - N/A 16 N/A 6.81 7.5 8.25 ± 10% N/A EEPROM read / write cycles Low Input Voltage "low" VL High Input Voltage "high" VH Clock Rate ƒCL VCC - 0.2 MAX UNITS V PROGRAMMABLE CURRENT SINKS Reference current IR PCS Bias Voltage VPCS Number of Settings mV µA Output Current for set "15" Io15 DAC set to 15 Linearity Error η DAC set for 1,2,4,8 (note 1, 2) N/A Output Current offset "0" IOFFS DAC set to 0 (note 1, 2) - 0 - nA Output Leakage Current IL DAC set to 0 - 0 - nA Early Voltage = Va DAC set to 15 (note 1, 2) - 37 - V 1 VPCS = 0.5 V (note 2) VPCS = 0.5 V (note 1, 2) Set VPCS = 0.5V and Channel length modulation VPCS = 0.7V (S9 = b) All switches remain as shown in Test Circuit unless otherwise stated in condition columns. NOTES: 1. Refer to the definition section 2. Measurements performed for all DAC's separately (SWS 1 to 8 closed sequentially). 510 - 79 - 06 2 - 1.3 V CLOCK + 1.3 V DATA CLOCK OSI SWOFF VCC 18 K - I 01 I 02 + V REF =0.65V SWS 1 2 I 03 I 04 3 4 I 06 I 05 5 IR GND 6 I 07 7 I R = 4 uA I 08 A 8 + - S9 IO - DATA RET VB = 1.3 V 18 K - DATA + - b a + 1.3 V 22 K 27 K 0.5 V + - + - 0.7 V 22 K All resistors in ohms, all capacitors in µF unless otherwise stated Fig. 2 Digital Test Circuit GP521 DIGITAL TESTING The GP521 is tested for digital functionality via a series of reads and writes to the GP521. For a summary of the actual testing refer to Document No. 520-35 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PCS CURRENT (µA) 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 10 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 9 8 PCS CURRENT (µA) 8 7 6 5 4 3 2 1 0 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 PCS VOLTAGE(V) PCS VOLTAGE (V) Fig. 4 PCS Current (Sink) vs PCS Voltage IR = 0 to 7.5µA (step 0.5µA) DAC set at 10 Fig. 3 PCS Current (Sink) vs PCS Voltage at DAC Setting 0 to 15, IR = 4µA 3 510 - 79 - 06 TYPICAL DISTRIBUTION of PCS CURRENT Number of IC Number of IC 240 240 200 200 160 160 120 120 80 80 40 40 0 0 -6 -3 0 3 6 -6 -4 Fig. 5 Linearity Error (Digital Input set to 2) [%] -2 0 2 4 Fig. 6 Linearity Error (Digital Input set to 4) [%] Number of IC 280 240 200 160 120 80 40 0 -3 -2 -1 0 1 2 3 Fig. 7 Linearity Error (Digital Input set to 8) [%] Number of IC 280 Number of IC 240 240 200 200 160 160 120 120 80 80 40 40 0 0 -0.06 -0.03 0 0.0 3 0.06 Fig. 8 Output Current Off set [µA] 7.2 7.4 7.6 7.8 8 8.2 Fig. 9 Output Current for Digital Input set to 15 [µA] * The data was collected on limited numbers of the chips. 510 - 79 - 06 7 4 PIN DESCRIPTION CLOCK - The clock pulses for synchronization of the data transfer. The clock pulses are provided by the programming unit. Similarly if OS1 is high, IO2 and IO4 are set as high impedance points. This allows PCS IO1 and IO3 to sink current. TABLE 1 EFFECTS OF SWOFF AND OS1 INPUTS DATA - The input / output pin allow for serial data transfer between the GP521 and the programming unit. VCC SWOFF OS1 - Recommended supply voltage for GP521 is 1.3V SWOFF - The logic state of SWOFF determines whether the GP521 operates at 6 or 8 PCS configuration. When SWOFF is IO8) PCS are available (8 PCS high, all eight (IO1 to configuration) Figure 10. OUTPUT PCS Register Address 0 1 ( IO1 and IO3)* (0001000 and 0001010) 0 0 ( IO2 and IO4)* (0001001 and 0001011) 1 x IO1 0001000 1 x IO2 0001001 1 x IO3 0001010 1 x IO4 0001011 x x IO5 0001100 CLOCK 1 17 IR x x IO6 0001101 DATA 2 16 x x IO7 0001110 V CC 3 NC Io5 SWOFF x x IO8 0001110 4 GND 5 OS1 Io4 6 Io3 15 GP521 14 NC 13 Io6 12 Io7 11 7 10 8 9 Note* Io8 Io1 IO1 - IO8 - Each pin is the output of the specific Programmable Current Sink (PCS). Each PCS consists of four bit EEPROM memory, Digital to Analog Converter (DAC) and current sink. The EEPROM stores the four bit information written during initialization of the system. Four bit memory allows for 16 settings of the current sink. For simplicity, consider the current sink as a variable resistor. The value of this resistor is dependent on the DAC setting; DAC is controlled by the binary value of the RAM memory. To define output current of the current sink, it is necessary to set the voltage applied to the PCS output. This voltage is recommended to be 0.5 V. If the binary value of the EEPROM increases by one, the value of the output current increases by 0.125 x IR. Io2 Fig.10 EIGHT OUTPUT CONFIGURATION When SWOFF is low, four PCS (IO5 to IO8) are available; availablility of other two PCS is dependent on the voltage on pin OS1. For this configuration (6 PCS configuration) the necessary hardware connections are presented in Figure 11. CLOCK 1 17 DATA 2 16 VCC 3 SWOFF 4 GND 5 OSI 6 GP521 15 IR NC Io5 14 NC 13 Io6 12 Io7 Io4 7 10 Io8 Io1 Io3 8 9 Io2 11 The complementary outputs are set as high impedance points. IR - The reference current delivered from the outside source (eg. GP520A). This current determines the incremental value of the programmable current sink for each increase of the EEPROM address value. The valid addresses run from 0 through to 15. Each step is defined as ∆I = IR x 0.125, therefore maximum current at setting 15 is equal to I15 = IR x 0.125 x 15. Fig. 11 SIX OUTPUT CONFIGURATION OS1 - The voltage level on this pin determines the selection of four PCS (IO1 to IO4) for 6 PCS configuration. As indicated on Figure 11, pin IO1, IO2 and IO3, I O4 are connected together. If OS1 is low, IO1 and IO3 are set to high impedance. Therefore the PCS, IO2 and IO4 are permitted to sink current. 5 510 - 79 - 06 GP521 REGISTERS TABLE 2 There are four types of registers used in the GP521. Their functions are described as follows: ADDRESS FUNCTION TYPE 0000000 ID read only 0000001 STATUS/OP read/write RAM / ROM ID - Hearing instruments identification register. The contents are set to 0000000 indicating a visual identification is required. REGISTER ADDRESS DEFINITIONS MEMORY CELL * ROM 0000010 * to STATUS - Monitors the present state of the GP521 and records whether an error has occurred in the previous dialogue with the program unit. The STATUS is read only register. unused 0000111 0001000 PCS IO1 read/write RAM +EEPROM 0001001 PCS IO2 read/write RAM +EEPROM OPERATION - Performs EEPROM read to (write from) RAM operations. The desired operation is specified by the data sent to the register. This is write-only register. 0001010 PCS IO3 read/write RAM +EEPROM 0001011 PCS IO4 read/write RAM +EEPROM 0001100 PCS IO5 read/write RAM +EEPROM PCS - Stores the programmable current sink settings. 0001101 PCS IO6 read/write RAM +EEPROM 0001110 PCS IO7 read/write RAM +EEPROM 0001111 PCS IO8 read/write RAM +EEPROM The register address definitions and the data bit definitions are given in Tables 2 and 3. The STATUS and OPERATION registers are two different registers sharing a common address. 0010000 * to unused 1111111 * The GP521 will indicate an error if an unused register is accessed or a write to is attempted to a read-only register. TABLE 3 DATA BIT DEFINITIONS DATA BIT STATUS REGISTER OPERATION REGISTER PCS REGISTER* No operation set IO= 0 EEPROM values Load EEPROM values into PCS set IO= 0.125 IR XXXXX1X Circuit busy with EEPROM write Save PCS values in EEPROM memory set IO= 0.25 IR XXXX1XX Transmission error on previous dialogue unused set IO= 0.5 IR XXX1XXX Bad Address and/or Operation Error on previous dialogue unused set IO= 1.0 IR XX1XXXX unused unused unused X1XXXXX unused unused unused 1XXXXXX unused unused unused 0000000 XXXXXX1 PCS outputs may be different than *Note: 1. Combining data bits in a word is equivalent to combining the corresponding definitions. (i.e. 0001101 in the PCS register would set the output to IO =1.625 IR ). 2. The upper 3 data bits are ignored except for parity checking. 510 - 79 - 06 6 ERROR DETECTION The errors detected and recorded in the STATUS register are defined as follows: The alternating 1’s and 0’s between information bits are used to check whether the GP521 is synchronized with the prgramming unit. The information bits are defined as: f (function bit) f = 0 Write data to specified memory address f = 1 Read data from specified memory address TRANSMISSION ERROR This error occurs whenever an incoming parity error is detected and/or the GP521 detects that it is not synchronized with the programming unit. This type of error sets a STATUS bit and puts the circuit in unsynchronized mode. The STATUS bit clears after a successful read/write operation. BAD ADDRESS and / or OPERATION ERROR: Status register is set when: - any write operation is attempted while an EEPROM write is in progress a6a5a4a3a2 a1a0 d6d5d4d3d2 d1d0 7 bit address to read/write to 7 bit data to write to memory pO parity bit for information from program unit (odd parity) r6r5r4r3r2 r1r0 7 bit data. If f=0, the data will echo the 7 bit data sent by the programming unit. If f=1, the data is read from the memory address. p1 Parity bit for data sent by GP521 (odd parity) - a write operation is attempted on the ID register - any operation is attempted on an unused address. This type of error sets a STATUS bit and sets the parity bit of the returned data stream to the incorrect value. This bit is reset at the conclusion of a ␣ acceptable read or write operation. SYNCHRONIZATION OF THE GP521 WITH PROGRAMMER The synchronization of the program with the GP521 is done using a code in the data stream which cannot occur during a correct dialogue. The GP521 looks for the following data sequence in the data stream: COMMUNICATION FORMAT The dialogue between the programming unit and the GP521 consists of 32 bits being sent to the GP521 which responds by returning 16 bits to the programming unit. A complete dialogue DATA = 1010 consisting of 48 bits as seen on the DATA line is as follows: where the final synchronization bit is a low. The next bit following the 4 bit synch code is assumed to be part of a valid dialogue. Once the GP521 is synchronized with the program unit, it is possible to perform a continuous sequence of dialogues without having to re-synchronize unless transmission errors occur. It is also possible to pause and continue the transmission provided the proper relationship between CLOCK and DATA is maintained. From Program Unit: f 1 a0 0 a1 1 a2 0 a3 1 a4 0 a5 1 a6 0 d0 1 d 1 0 d2 1 d 3 0 d4 1 d 5 0 d6 1 p0 0 From GP521: r 0 1 r 1 0 r 2 1 r 3 0 r 4 1 r 5 0 r 6 1 p1 0 To guarantee that the circuit synchronizes properly, the internal shift registers should be cleared by preceding the synch code with a string of bits containing a synch error. The dialogue begins with the bit f and ends with the two bits p1 , 0. The data and synchronization bits must be correct on the falling edge of CLOCK. This relationship is shown in Figure 12. An example of the data sequence that guarantees a correctly synchronized circuit is: DATA = 11111010 CLOCK DATA f aO a1 Synch bit alternates 1 0 1 0 1 ... Fig. 12 7 510 - 79 - 06 DEFINITIONS LINEARITY ERROR OUTPUT LEAKAGE CURRENT Linearity error is defined as the difference between the actual current value for a given digital input setting and the current value indicated by the straight line through point P1 and P15. Maximum sink current of the control output at setting 0 of the digital input is defined as output leakage current. EARLY VOLTAGE The point P1 is the current at the setting 1 (0001) of the digital input. (Figure 13) The early voltage is defined by the following equation: 1 V = Early Voltage = a The point P15 is the current at the setting 15 (1111) of the digital input (Figure 13) The current at set 0(0000) of the digital input is left out of the linearity error definition. This point on the characteristic is not correlated to other points (there is no current commutation through the current sink at set 0000). = 0.5 - I0.5 (0.5 - 0.7) (I0.5 - I 0.7) where V a - Early Voltage I0.5 - sink output current at bias voltage VPCS = 0.5 V P15 CURRENT VALUE = channel length modulation I0.7 - sink output current at bias voltage VPCS = 0.7 V MEASURED VALUES LINEARITY ERROR OUTPUT CURRENT OFFSET P1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DIGITAL SETTINGS Fig. 13 PCS Current vs Digital Setting OUTPUT CURRENT OFFSET FOR SETTING 0 The current value determined by the extrapolation of the straight line (defined by the linearity error definition) at setting 0 (0000) of the digital input ( Figure 13) is defined as the ouput current offset. DOCUMENT IDENTIFICATION: DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. REVISION NOTES: Updated to Data sheet Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright April 1991Gennum Corporation. All rights reserved. 510 - 79 - 06 8 Printed in Canada.