ANALOG PRODUCT DIVISION PA1418 Technical Note Introduction This is a reference note for Protek Analog’s PA1418. The document includes data for the IC, recommended external components, and other pertinent information. Please read all instructions and recommendations before beginning to design any product that is to include this device. This document contains a checklist to reference before powering up completed circuit and troubleshooting procedures outlining causes and countermeasures for issues arising in the application of the IC. Contact information is included if this document is insufficient to answer any problems or questions that may arise. Contents Overview. 1.1. Features 1.2. Block Diagrams 24TSSOP Pin out 32 QFN Pin out 1.3. Absolute Maximum Ratings 1.4. Operating Range 2. Operation. 3. Navigator. 4. Explanation of External Parts. 4.1. Pre-Emphasis 4.2. Limiter 4.3. Low-Pass Filter 4.4. Half VDD Filter 4.5. Composite Signal Adjust 4.6. RF Oscillator 4.7. RF Output 4.8. X’TAL Oscillator 4.9. Serial Data Input 4.10. Phase Lock Loop 4.11. Audio Mute 4.12. Pilot Signal Adjust 5. PCB Sample and Recommendations. 1. 1. Overview: The PA1418 is a Radio Transmitter that can send audio signals from personal computers, game consoles or independent devices to any type of audio equipment with a built in FM receiver. The IC consists of a Pre-Emphasis circuit that improves Signal to Noise Ratio (S/N), a Limiter circuit that prevents over-modulation and a low Pass filter (LPF) circuit that limits the maximum modulation frequency. The Stereo modulation circuit generates stereo composite signals through a FM transmitter circuit with PhaseLocked Loop (PLL) frequency synthesizers. 1. 1. Features 1. 2. 3. 4. 5. Improved Audio Quality due to integrated Pre-emphasis, limiter and Low-pass filter circuits. Pilot tone FM stereo modulation circuit is integrated. An incorporated PLL frequency synthesizer ensures a stable FM transmission frequency. Device utilizes a serial data control method to set the frequency via a microcontroller. Integrated mute option. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 1. 2. Block Diagram: - XTAL IN XTAL OUT PLL Vcc 20 NC 21 Chip Enable Pilot Sig Adj 22 CLOCK LPF TC 23 DATA Pre-Emp TC 24 Audio Mute L-CH Input 24 TSSOP Package 19 18 17 16 15 14 13 LPF + 16 Bit Shift Register 2 1 304kHz 1/25 Audio MPX LPF 3 4 5 6 7 8 9 10 11 12 PLL Phase Detector Out VCC NC RF Oscillator RF Ground RF Output RF + GND Pre-Emp TC OSC VCC 2 Composite Signal Out R-CH Input Dual Modulus Driver Phase Detector Filter 2 152kHz LPF TC 1 1/76 M/S Pilot MPX - 100kHz 1/2 Mute + 11 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 1.2. Block Diagram: NC 20 19 18 NC CE Audio Mute 21 22 CLOCK 23 DATA 24 Pilot Sig Adj. NC NC 32 QFN Package 17 25 16 XTAL IN 15 XTAL OUT 14 PLL VCC 13 RF Output 16 Bit Shift Register LPF TC 26 Pre-Emp TC 27 1 - 1/25 1/2 304kHz 28 + + Phase Detector OSC 1 2 3 4 5 6 7 8 NC PLL Phase Detector Out VCC VCC 2 GND 32 RF NC NC Dual Modulus Driver Composite Signal Out 31 - Pilot MPX Filter LPF TC Mute LPF NC Pre-Emp TC 1/76 152kHz 29 30 100kHz M/S Audio MPX R-CH Input 11 LPF + L-CH Input 2 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com 12 RF Ground 11 NC 10 RF Oscillator 9 NC ANALOG PRODUCT DIVISION PA1418 Technical Note 1. 3. Maximum Operating Range (Ta = 25oC, In test circuit)(Pin numbers reference the 24 TSOP package) Symbol Limits Unit Conditions Supply Voltage VCC +7.0 V Pin 8, 13. Data Input voltage V IN-D - 0.3 to Vcc + 0.3 V Pin 17,18,19,20. Phase comparator output voltage VOUT-P - 0.3 to Vcc + 0.3 V Pin 7. Power dissipation PD 630 mW (Note 1) Storage Temperature Tstg -55 to +125 ºC Parameter (Note 1) when operation temperature exceeds Ta= to 25ºC power is derated at 6.3mW per 1ºC 1.4. Recommended Operating Range o (Ta = 25 C,) Parameter Symbol Limits Unit Operating Supply Voltage VCC 3.6 to 5.0 V Operating Temperature TOPR -40 to +85 ºC Audio Input level VIN-A Up to 10 Audio Input Frequency Band fIN-A Pre-emphasis time constant set up range Conditions Pin 8, 13. dBV Pin 1, 24 20 to 15k Hz Pin 1, 24 tPRE to 155 µS Pin 2, 23 Transmission Frequency fTX 70 to 120 MHz Pin 10, 12 Control Terminal “H” level input voltage VIH 0.8Vcc to Vcc V Pin 17, 18, 19, 20. Control Terminal “H” level input voltage VIL GND to 0.2Vcc V Pin 17, 18, 19, 20. Notes i. Operating conditions. a. Do not exceed the maximum rating for this device even momentarily; reliability and functionality of the device could be compromised. If special design considerations permit the circuit to exceed the listed tolerance, please utilize a fuse or other methods to protect component from damage. b. The electrical characteristics described at Ta = 25°C cannot be guaranteed if this operating temperature is not maintained. Please contact the engineers at Protek Analog if you have any questions or concerns. ii. Storage and Transportation. a. Store the product in a dry place at room temperature to prevent oxidation of the device terminals. (Humidity = 75% or less, Temperature = 0-30°C) b. Please use static protection containers when storing or transporting devices. c. Be careful not to expose ICs to water or electrically conducting fluids at any time and avoid toxic gasses or dust. d. During transportation, please insulate the device from any discharge capacitors on boards. e. Avoid mechanical vibration and physical shock to devices during transportation or storage. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note iii. Cautions during Installation. a. Some device packages contain NC terminals, please do not use these free pads for relays, or allow the other pins to make contact with these NC terminals. Problems such as unwanted oscillations may occur. b. Caution: If a heat sink is cut or damaged and the device is deformed the induced thermal stress can cause a failure or limit the life of the device. c. When mounting device on a board please be careful to align the device in the correct direction, both the 32 QFN and 24 TSSOP packages have dots placed in the same corner of the package corresponding to pin 1. Powering on the device with the pins misaligned can ruin the device. 32 QFN 24 TSSOP 24 13 PA1418 XXXX PA1418 1 12 d. Install the device gently on its PCB level with the plane of the board to reduce stress on pins and contacts. e. Before soldering device, be sure that the soldering iron properly grounded and that it is not leaking power into the tip. Discharge from the iron can cause failure of the device when placed in contact with the pins. f. Verify that all assembly stations and their perspective assembly techs are properly grounded as released static charge can have an adverse effect on the device. Likewise, pay close attention to the humidity and production methods to reduce static buildup. iv. Cautions during testing and inspection. a. Be sure to inspect soldering for accuracy before applying power to the device, bridged pins can cause serious damage. b. Please use a current limiter circuit on the power supply, high currents can go into the device and ruin it. c. Be careful that the device or board is in the designated position before starting measurement inspection or possible high currents can damage product. d. Ensure that the ground will not generate a surge current. v. Heat Design a. The operational characteristics of this device are affected by temperature. Excessive heat can cause the performance and life expectancy of the product to reduce dramatically, in Extreme cases destroying the device outright. b. The IC is designed for balanced temperature at normal operation; if however, external components or lack of proper ventilation cause excessive heat than additional heat sinks can be utilized to cool the device. c. If additional heat sinks are implemented, please ensure that they are properly bonded to device. If you have any questions about thermal design or any other topics in an application please contact the applications team at Protek Analog. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 2. Operation: (Pin numbers reference 24 TSSOP package) The PA1418, FM stereo transmitter IC made by ProTek Analog includes all the processing circuitry required for stereo FM transmission and also the crystal control section, which provides precise frequency locking As shown, the PA1418 includes two separate audio processing sections, for the left and right channels. The left-channel audio signal is applied to pin 24 of the chip, while the right channel signal is applied to pin 1. These audio signals are then applied to a pre-emphasis circuit, which boosts those frequencies above a 50ms time constant (i.e., those frequencies above 3.183 kHz) prior to transmission In addition, the 1.9MHz signal is divided by 76 to give a 100 kHz signal. This signal is then applied to the phase detector, which also monitors the program counter output. This program counter is actually a programmable dual modulus divider, which outputs a divided down value of the RF signal. Pre-emphasis is used to improve the signal-to-noise ratio of the received FM signal. It works by using a complementary de-emphasis circuit in the receiver to attenuate the boosted treble frequencies after demodulation, restoring the frequency response is restored to normal. At the same time, this also significantly reduces the ‘hiss” sound that would otherwise be evident in the signal The phase detector output produces an error signal to control the voltage applied to a varicap diode and forms part of the RF oscillator at pin 10. Its frequency of oscillation is determined by the value of the inductance and the total parallel capacitance. The amount of pre-emphasis is set by the value of the capacitors connected to pins 2 & 23, (Signal limiting is also provided within the pre-emphasis section). This involves attenuating signals above a certain threshold to prevent overloading succeeding stages also preventing over-modulation and reduces distortion. The pre-emphasized signals for the left and right channels are then processed through two low-pass filter (LPF) stages, designed at15kHz. This roll-off is necessary to restrict the bandwidth of the FM signal and is the same frequency limit used by commercial broadcast FM transmitters. The outputs from the left and right LPF channels are in turn applied to a multiplex (MPX) block. This is used to effectively produce sum (left + right) and difference (left - right) signals which are then modulated onto a 38 kHz carrier. The carrier is then suppressed (or removed) to provide a double-sideband suppressed carrier (DSBSC) signal. It is then mixed in a summing (+) block with a 19 kHz pilot tone to give a composite signal output (with full stereo encoding) at pin 5. The phase and level of the 19 kHz pilot tone are set using a resistor and a capacitor at pin 21.The 38 kHz multiplex signal and 19 kHz pilot tone are derived by dividing down the 7.6MHz crystal oscillator located at pins 14 & 15. The 7.6MHz crystal frequency is divided by 25 to provide a 304 kHz signal. This 304 kHz signal is used by the audio multiplexer and an 8-bit DAC to generate the composite signal with the subcarriers (38 kHz). The 76MHz frequency is also divided by 50 to generate a 152 kHz frequency. This signal is used by the pilot signal into the composite audio. The division ratio is set by programming the counter with a 6 and 5 bit number. More information on the working of the dual modulus divider is given in section I of “Explanation of External Parts” Since the varicap diode forms part of this capacitance, we can alter the RF oscillator frequency by varying its value. In operation, the varicap diode's capacitance varies in proportion to the DC voltage applied to it by the output of the PLL phase detector. The phase detector adjusts the varicap voltage so that the divided RF oscillator frequency is 100 kHz at the program counter output. If the RF frequency drifts high, the frequency output from the programmable divider rises and the phase detector will "see" an error between this and the 100 kHz signal. As a result, the phase detector reduces the DC voltage applied to the varicap diode, thereby increasing its capacitance. And this in turn decreases the oscillator frequency to bring it back into "lock". Conversely, if the RF frequency drifts low, the programmable divider output will be lower than 100 kHz. This means that the phase detector now increases the applied DC voltage to the varicap to decrease its capacitance and raise the RF frequency. As a result, this PLL feedback arrangement ensures that the programmable divider output remains fixed at 100 kHz and thus ensures stability of the RF oscillator. By changing the programmable divider we can change the RF frequency. So, for example, if we set the divider to 1079, the RF oscillator must operate at 107.9MHz for the programmable divider output to remain at 100 kHz. The RF frequency is modulated by the voltage applied to the varicap diode using the composite signal output at pin 5.The average frequency of the RF oscillator remains fixed, as set by the programmable divider. As a result, the transmitted FM signal varies either side of the carrier frequency according to the composite signal level - i.e., it is frequency modulated. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 10uF .22uH .1uF .22uH PLL Vcc 22pF 22pF 56K 11 3.3K 56K 12 22pF 10 XTAL OUT XTAL IN Chip Enable NC 9 22pF 100nF 1uF 10uF 150pF 2.2nF + 8 10uF + 13 RF Output 7 14 RF Ground 6 15 RF Oscillator PLL Phase Detect 5 16 NC GND 4 Vcc Signal Out Comp CLOCK 17 ½ Vcc Filter DATA 18 LPF TC Audio Mute 19 3 + + 7.6MHz 20 2 + 27pF 27pF 2.2nF 1.8K 21 Pilot Sig Adj 22 Pre-Emp TC L-CH Input + 1uF 23 1 10µF Right Channel In 24 R-CH Input Left Channel In + 1uF Pre-Emp TC 50K LPF TC 2.2nF 10uF + 150pF 3. Navigator: Basic design reference 10 50K 470pF 150pF VCD MPX 330pF 10uF 10K CMP 50K 3.3K 2.2K .047uF 10K VT 2.2nF 32QFN 29 30 31 2 3 5 7 8 10 12 13 14 15 16 18 19 20 21 22 26 27 28 10K PIN OUT Reference Pin Name R- CH Input Pre-Emp TC LPF TC ½ Vcc Signal Out Comp GND PLL Phase Detect Vcc RF Oscillator RF Ground RF Output PLL Vcc XTAL OUT XTAL IN Chip Enable CLOCK DATA Audio Mute Pilot Signal Adjust LPF TC Pre-Emp TC L- CH Input 2pF (OPT) 3.3K 24TSSOP 1 2 3 4 5 6 7 8 10 11 12 13 14 15 17 18 19 20 21 22 23 24 .1u 1uF C B E 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 4. Explanation of External Parts: (Use TSSOP Package for referencing pin locations) 4.1. Pre-Emphasis (Pins 2, 23) The IC’s internal bias is set to ½ Vcc at pins 1 and 24 therefore coupling capacitors (C1) must be used between these pins and the audio signal. The positive polarity of the coupling capacitors must be set to the higher DC potential whether that is the input signal from the Audio source or the Left and Right channel inputs. The low range frequency cut-off is determined by the input impedance values of pins 1 and 24 and the value of the external coupling capacitors. If the value is too low the lower frequency ranges can be cut, but if the value becomes too large a pronounced pop-up noise and a longer start up time will result. 1 2 43k C1 The Input cut-off frequency can be calculated by: ƒCL = The Pre-Emphasis Time constant is determined by the value of the external capacitors (C2) at pins 2 and 23 and the IC’s internal resistance of 22.7kΩ. 22.7 k C The Time Constant can be calculated by: 2 < 155 sec L & R Channel Inputs C1 ½ Vcc + C1 + 43K 43K 24 1 2 C2 1K 1K - + 22.7K + - 22.7K 23 C2 Limiter Circuit 4.2. Limiter (Internal) The Limiter Circuit: Pre-Emphasis 100K ½ Vcc + - 100K - + 100K 100K Low pass filters 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 4.3. Low Pass Filter (Pins 3 and 22) Both pin 3 and pin 22 require 150pF capacitors (C3) connected to ground to complete the LPF circuit. Limiter Circuit 100K 100K ½ Vcc 22 3 - + 100K C3 100K 100K + - 100K C3 50pF 50pF MPX 4.4. Half Vcc Filter (pin 4) A 10μF capacitor (C4) is required for proper filtering. A lower value will add distortion while a higher value will slow the start up time. 4 ½ Vcc + C4 4.5. Composite Signal Adjust (pin 5) The modulation rate is adjusted using the composite signal output (pin 5) and the external FM modulator. To make an adjustment, alter the load resistance at pin 5 by changing the value of R1. The total load on pin 5 should not exceed 50kΩ; lesser values will add unnecessary distortion. ƒCL = 1 2R1C5 C5 To the FM modulator + + R1 5 + Pilot MPX Audio MPX Mute 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note By design, the IC is set so that the composite output L + R = 85% and Pilot = 15% when 400Hz and -20dBV of sine wave is input to pins 1 and 24. The pilot modulation rate is set to 15% to prevent the amplitude from lowering and the modulation rate from dropping far below 10% when the phase of the pilot signal is adjusted. If it is necessary to adjust the pilot modulation precisely, insert a resistor first in between pin 19 and capacitor to lower the modulation rate. Then adjust R1 while measuring the FM modulation rate at pin 11 until it reaches 100% with a modulation analyzer. 4.6. RF Oscillator (pin 10) The RF Oscillator is a modified Clapp oscillator, which consists of bipolar transistors. The features of this circuit are such that the oscillating condition is not affected even if the impedance of the parallel resonant (LC) circuit is changed. The oscillation is stabilized against internal transistor changes because the feedback capacitor inside the IC is much larger than the capacitance of the transistor. The RF Oscillator is an important part of the PLL circuit and should be verified in the application. Undesirable noise may result from running oscillations at the limits of the range or from external factors. The scale of the distortions are directly proportional the frequency so extra care is needed when using the upper ranges of the oscillator. It is also important to be sure the Oscillator’s components are properly secured; vibrations can cause undesired modulation if not mechanically sound. L1 R1 C1 C2 VCD 10 11 C3 OSC RF 12 DUAL MODULUS DIVIDER VT R2 R3 CMP C4 The padding Capacitor C3 in series with the Variable Capacitance Diode VCD is used to adjust the oscillating frequency range. The choice of C3 depends on the characteristics of the VCD. C3 can vary from 10pF to 150pF depending on surrounding components. If C3 is set closer to 100pF then the VCD has a large impact on the LC resonant circuit. When C3 is set with a low capacitance, the variable range of the control voltage to the VCD becomes wider, thereby making the oscillator excessively sensitive. This can cause the modulation rate to fluctuate in an exaggerated fashion in relation to the transmission frequency. The Inductance of the coil L1 is set so that the reactance XL may be around 50-100 If ƒTX = 77.5 MHz then, L1 = XL 2 ƒTX The capacitor C2 is connected in parallel with L1 and is used to set the range of the oscillator frequency. The larger the CMIN capacitor value, the smaller the variable range will become. 1 = 42.6pF 2 L1 1 If ƒMAX = 79 MHz then, CTOTmax = = 39.4pF 2 L1 If ƒMIN = 76 MHz then, CTOTmin = 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note CTOT is the combination of the inline capacitance of VCD and C3 with C2. Choose a VCD that had a linear c-v relationship of 0 ≤ VIN ≤ 5.0. In this schematic the part number used was Zetex ZMV832ACT that has a capacitance range of 30pF @ VIN = 0V to 11pF @ VIN = 5.0V. (please refer to manufacturer’s datasheet for detailed information on this part) The type of capacitor used for C2 is also of importance because of the need to cancel the temperature characteristics of L1. A temperature compensating ceramic capacitor is utilized for this purpose. For air-core coil inductors RH (-220±60 ppm/Cº) or SH (-330±60 ppm/Cº) can be used, for ferrite-core inductors TH (-470±60 ppm/Cº) or UJ (-750±60 ppm/Cº) are recommended. The damping resistor R1 and the coupling capacitor C1 are used to correct the harmonics of the oscillating circuit. C2 should be set between 470pF and 47nF. If larger values are utilized, the internal oscillator is greatly affected by the external circuits and may not stabilize. If the value is set low the Q of the oscillating circuit is decreased and the oscillating may stop. The harmonics are observed by monitoring the antenna terminal with a spectrum analyzer. Please be sure to match the impedance (50Ω or 75Ω) or the results will be misleading. The damping resistor is used to reduce the harmonics level. Set R1 between 0Ω and 10Ω. R1 must be set so that the harmonics comply with the radio laws of the marketed countries. To confirm the oscillation range of operation, 1. Manually discharge the inductor to stop the oscillation and upon removing the source of the interruption, check to see if the oscillating resumes. 2. Confirm that oscillation can continue when the power supply drops below 3.0V 3. Given that step 1 and 2 passed. Increase the value of R1 by at least 33% and check to see if the circuit can still oscillate. 4. If the circuit is incapable of passing the first 3 tests, increase the value of C1 or alter L1 or the VCD to increase the Q of the circuit. R2 is used to increase the impedance after the VCD; to achieve this at least 10KΩ should be employed. R3 and C4 act as a low pass filter for the DC voltage at VCD, choose R3 as 3.3kΩ and C4 as 2.2nF. 4.7. RF Output (Pin 12) A BPF must be inserted in-between the RF output and the antenna to suppress undesired RF output harmonics. The output impedance of pin 12 is set to 75Ω. OSC ANTENNA 11 RF 12 DUAL MODULUS DIVIDER C1 R2 R1 L1 R3 C2 L2 C3 C4 BPF 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 4.8. X’TAL Oscillator (Pin 14, 15) A 7.60 MHz crystal oscillator is needed between pins 14 and 15 coupled with its 27pF load capacitors (C1 and C2) as shown the the folowing drawing. 15 Rf C1 7.60MHz 14 C2 13 The crystal needs to be placed as near as possible to the device output pins to minimize stray capacitance. Please no not run any wires or traces near or under the oscillator as it is very suseptable to interference. If possible, place a ground plane directly under the crystal to further insulate it from any nearby signals. 4.9. Serial Data Input (Pin 17, 18, 19) The VIH level for the inpt voltage at the serial data input is 0.8Vcc to Vcc and the VIL level is GND to 0.2Vcc. Please note that the operating voltage of the microcontroller can be different from the operating voltage of the IC. It is also important to keep in mind that there needs to be a small delay betweeen powering on the IC and inputing the serial data. The initial logic is set as “unfixed” upon startup and some circuits such as the PLL will not function correctly instantaniously. Mono/Stereo Phase Detector 1 Dual Modulus Divider 18 17 Micro-Controller 11 Shift Register 19 2 6 PA1418 – Serial Programming Interface: The PA1418 has a 3-pin serial programming port. This port consists of pins CE (Chip Enable), CK (Clock) and DA (Data). The timing sequence of these signals is as shown in figure 1. Using these ports a 16-bit word can be fed into the chip to form various division ratios as well as other control bits. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note t1 t4 t2 t3 CE CK D0 DA D1 D2 D3 D4 D5 T1 T0 t1, t2, t3, t4 ≤ 1.5μsec Figure 1: Timing sequence of signals Setup and Hold Requirements: The setup and hold requirements of these signals are shown in figure 2: TDB TDE 90% 50% C E THW TLW 50% C K 50% 50% TR TF 90% 50% 50% D A 10% TSE THL TDB ≥ 1.5µsec TDE ≥ 0sec THW ≥ 1.5µsec TLW ≥ 1.5µsec TR TF TSE THL ≤ 300nsec ≤ 300nsec ≥ 100nsec ≥ 100nsec Figure 2: Setup and Hold requirements of signal 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note Bit Structure of the 16-bit word: The bit structure of the 16-bit word is shown in figure 3. Serial Data Input Configuration DA T1 T0 Test PD1 PD0 M/S Phase Detector Output Control S0 S1 S2 S3 S4 P0 P1 P2 P3 P4 P5 Program Counter Mono/ Stereo Figure 3: Serial data input configuration Setting up the Program Counter: Figure 4 shows the contents of the Program Counter. Program Counter Configuration S0 S1 S2 S3 S4 P0 P1 P2 P3 P4 P5 P (6 bits) S (5 bits) Figure 4: Program Counter Configuration The Dual Modulus divider works as follows: M= S P * 32 = f RF f IN = f RF 100kHz Where: M is the desired division ratio. S and P are integers such that S < P. Example: To program for 101.1MHz frequency, perform the following calculations. f RF 101.1MHz Calculate P as: P= M= 101.1MHz 100kHz = 1011 1011 = 31 = 111110b 32 Calculate S as: S= 1011 - 32 31 = 19 = 11001b To program the chip for normal stereo operation, feed the following bits: (0000 1100 1101 1111)b 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note Dual Mod Divider f IN (Input frequency) fI N PFD f RF M f RF Filter VCO RF Frequency ( f RF ) f REF (Ref frequency 100kHz) Figure 5: Block Diagram of PLL. The PFD and Divider are internal to the chip Please note that due to the limitations of the Dual Modulus Divider, there are frequencies where S P, such as 95.9 MHz (where S = 31 and P = 28). If programmed for this frequency or any other frequency where S P, the PLL will not lock to the desired frequency and it may produce undesired results like audio noise or jitter. The following frequencies in the US FM Band may not be programmable by the PA1418: 89.1, 89.3, 89.5, 92.5, 92.7, 95.7, 95.9, 99.1, and 102.3. Explanation of the remaining controller bits: In addition to the 11 bit word for the divider, the PA1418 provides an additional 5 bits for controlling the phase detector output and the multiplexer stereo/mono transmission. They are as follows: Mono/Stereo: Mono 0 1 Status Monaural Operation, L + R, Pilot Off Stereo Operation, L + R + (L-R)sinωt + Psin(ωt/2) Phase Detector: PD0 0 0 1 1 PD1 0 1 0 1 Charge Pump Output Normal Operation Forced Low Forced High High Z 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 4.10. PLL Loop Filter The PA1418 employs a Charge Pump PLL. This means that the PFD output (pin 7) is a current output. An active loop filter is recommended because it has a very small input leakage current. The PA1418 employs a Darlington pair (MPSA13) as the amplifier. The active filter is a low-pass type filter. The block diagram of the PLL is as shown in figure 6. ÷N C2 R1 C1 fin gm PFD VC fr VCO Figure 6: Block Diagram of the Charge Pump PLL The active filter that is used in the PLL, as shown in Figure 7. VDD R1 C2 0.047µF 2.2k 3.3k VOUT 1µ 10k C1 R2 R3 f1 VIN f2 2200pF C3 Figure 7: Active Loop Filter for PA1418 and its response 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note Frequencies f1 and f2 are obtained as follows: 1 15.9 Hz 2R2 C1 1 f2 21.9kHz 2R3 C 3 f1 The PLL directly conducts audio modulation to the VCO. Hence the interrupting frequency f1 should be set low. The time to lock to the set frequency is dependent on the time constant τ1 which is calculated as follows: 1 C1 R2 1 Gm where Gm gm R1 This time constant has a trade-off relation with the amplitude and distortion characteristics when the modulation is conducted at a low range frequency (100Hz). In other words, if the frequency lock time is shorter, the distortion ratio in the lower range becomes worse, and if the amplitude characteristics and the distortion ratio are improved, the frequency lock time becomes longer. If R2 value is chosen to be smaller, the gain ( Gm gm R1 ) of the amplifier will affect the time constant τ1 and the loop operation will be unstable. If R1 is set to a higher value to improve the gain of the amplifier, the current through the transistor decreases and the gm results are smaller. This in turn affects the stability of the loop filter. The capacitor C2 improves the dynamic range of the LPF. C2 is calculated taking into account the stability factor of the LPF circuit. C2 should be calculated from the time constant c condition n 1 C 2 R2 , with the c (5 ~ 10) n where ωn is the natural angular frequency given by the relation V 1 Kφ is the Phase Detector constant and is given by the expression Ip 2 20A 3.18 x10 6 2 KV is the VCO sensitivity and is calculated as V 2 f max f min 120 MHz 75MHz 2 83.15 x10 6 Vmax Vmin 4.0 0.6 V/rad/s In this example, ωn = 1626 rad/s. So ωc = 16260 rad/s. Choose C2 = 0.047µF. C3 and R3 form a low-pass filter to eliminate the sideband. The ωc of this filter is much higher than 10ωn so the loop can be stable. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 4.11. Audio Mute (Pin 20) For the input control of the Mute terminal, the VIH level is 0.8Vcc to Vcc and VIL level is GND to 0.2Vcc. This can be controlled using a microcontroller (Fig 8) or controlled with the IC’s Vcc and an alternate switching control. (Fig 9) 5 Σ 20 Mute Dual Modulus Divider 18 Micro-Controller MPX Shift Register 19 17 6 Figure 8: Controlling mute with microcontroller Vcc 5 Σ 20 Mute 19 MPX Figure 9: controlling mute with external switch 5. Pilot Signal Adjust (Pin 21) The Phase of the pilot signal can be adjusted by changing the RC constant of R1 and C1 in-between pin 21 and ground. Recommended settings are 1.8KΩ for R1 and 2.2nF for C1. 21 R1 C1 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com ANALOG PRODUCT DIVISION PA1418 Technical Note 5. PCB Samples and recommendations: 24 TSSOP Sample demo board: Recommendations: It is important to note that the ground plane has been segragated into 3 semi-isolated sections to help isolate the RF Output, the Input and PLL LPF, and the digital sections. It is detrimental to signal integrity to allow these sections to share ground impedence where it can be otherwise avoided. Ideally, the bypass capacitors should be placed as close to the IC as possible and have the needed characteristics to handle the high frequencys of the circuit. When possible, using an independent power supply for the digital system is useful to prevent noise from interfering with the other circuit blocks. The crystal Oscillator should be placed as close as possible to the IC to minimize stray capacitance. It is also important to keep it clear of other signal traces or power lines that could interfere with it’s operation. The traces for the RF Oscillator and the RF output should be of suffecient width to reduce stray capacitance. (0.5mm wide minimum) It is important that the RF Output should be isolated and not be allowed to cross any other signal paths, nor should it cross through vias or reflective trace corners that can reduce signal strength and intergrity. 561 E Elliot Road. Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715. www.protekanalog.com