HOLTEK HT82K95EE

HT82K95EE/HT82K95AE
USB Multimedia Keyboard Encoder 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
· 160´8 data memory RAM
fSYS=6M/12MHz: 4.2V~5.5V
· 128´8 data EEPROM
· Low voltage reset function
· All I/O ports support wake-up options
· 32 bidirectional I/O lines (max.)
· HALT function and wake-up feature reduce power
· 8-bit programmable timer/event counter with over-
consumption
flow interrupt
· 8-level subroutine nesting
· 16-bit programmable timer/event counter and over-
· Up to 0.33ms instruction cycle with 12MHz system
flow interrupts
· Crystal oscillator (6MHz or 12MHz)
clock at VDD=5V
· Bit manipulation instruction
· Watchdog Timer
· 15-bit table read instruction
· PS2 and USB modes supported
· 63 powerful instructions
· USB1.1 low speed function
· All instructions in one or two machine cycles
· 3 endpoints supported (endpoint 0 included)
· 28-pin SOP package
· 4096´15 program memory ROM
General Description
This device is an 8-bit high performance RISC architecture microcontroller designed for USB product applications. It is particularly suitable for use in products such
as keyboards. A HALT feature is included to reduce
power consumption. The mask version HT82K95AE is
fully pin and functionally compatible with the OTP version HT82K95EE device.
Rev. 1.20
There are two dice in the HT82K95EE/HT82K95AE
package: one is the HT82K95E/HT82K95A MCU, the
other is a 128´8 bits EEPROM used for data memory
purpose. The two dice are wire-bonded to form
HT82K95EE/HT82K95AE.
1
August 28, 2006
HT82K95EE/HT82K95AE
Block Diagram
U S B D + /C L K
U S B D -/D A T A
V 3 3 O
T M R 1 C
U S B 1 .1
P S 2
M
T M R 1
U
fS
Y S
X
/4
P A 7 /T M R 1
B P
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R 0
U
fS
/4
Y S
P A 6 /T M R 0
X
T M R 0 C
IN T C
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
X
W D T P r e s c a le r
D a ta
M e m o ry
P B C
T im in g
G e n e ra to r
S T A T U S
O S
R
V
V
C 1
E S
D D
S S
P O R T B
P B
U
S Y S C L K /4
X
W D T O S C
P A 0 ~ P A 5
P A 6 /T M R 0
P A 7 /T M R 1
P B 0 ~ P B 5
P B 6 /S C L
P B 7 /S D A
S h ifte r
P C C
O S C 2
P O R T A
P A
M U X
A L U
M
P A 6
P A 7
P A C
In s tr u c tio n
D e c o d e r
W D T
P O R T C
P C
A C C
P D C
P O R T D
P D
P C 0 ~ P C 7
P D 0 ~ P D 7
Pin Assignment
P C 3
1
2 8
P C 2
V D D
2
2 7
P C 0
V 3 3 O
3
2 6
P A 0
U S B D + /C L K
4
2 5
P A 1
2 4
P A 2
2 3
P A 3
5
U S B D -/D A T A
6
P B 0
7
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6 /S C L
P B 7 /S D A
V S S
8
9
1 0
1 1
1 2
1 3
1 4
2 2
P C 4
2 1
P A 4
2 0
P A 5
1 9
P A 6 /T M R 0
1 8
P A 7 /T M R 1
1 7
O S C 1
1 6
O S C 2
1 5
R E S
H T 8 2 K 9 5 E E /H T 8 2 K 9 5 A E
2 8 S O P -A
Rev. 1.20
2
August 28, 2006
HT82K95EE/HT82K95AE
Pin Description
Pin Name
PA0~PA5
PA6/TMR0
PA7/TMR1
I/O
ROM Code
Option
Description
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register).
Pull-high
Pull-high resistor options: PA0~PA7
I/O
Wake-up
CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7
Wake up options: PA0~PA7
PA6 and PA7 are pin-shared with TMR0 and TMR1 input, respectively.
PB0~PB5
PB6/SCL
PB7/SDA
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
Wake-up options: PB0~PB5
Falling edge wake-up options: PB6, PB7
PB6 is wire-bonded with SCL pad of the Data EEPROM
PB7 is wire-bonded with SDA pad of the Data EEPROM
PD0~PD7
I/O
Pull-high
Wake-up
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
Wake-up options: PD0~PD7
VSS
¾
¾
I/O
Pull-high
Wake-up
RES
I
¾
Schmitt trigger reset input. Active low
VDD
¾
¾
Positive power supply
V33O
O
¾
3.3V regulator output
USBD+/CLK
I/O
¾
USBD+ or PS2 CLK I/O line
USB or PS2 function is controlled by software control register
USBD-/DATA
I/O
¾
USBD- or PS2 DATA I/O line
USB or PS2 function is controlled by software control register
OSC1
OSC2
I
O
¾
OSC1, OSC2 are connected to a 6MHz or 12MHz Crystal/resonator
(determined by software instructions) for the internal system clock.
PC0~PC7
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
Wake-up options: PC0~PC7
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
3
August 28, 2006
HT82K95EE/HT82K95AE
D.C. Characteristics
Symbol
VDD
Ta=25°C
Parameter
Operating Voltage
Test Conditions
VDD
¾
Min.
Typ.
Max.
Unit
fSYS=6MHz
4.2
¾
5.5
V
fSYS=12MHz
4.2
¾
5.5
V
Conditions
IDD1
Operating Current (6MHz Crystal)
5V
No load, fSYS=6MHz
¾
6.5
12
mA
IDD2
Operating Current (12MHz Crystal)
5V
No load, fSYS=12MHz
¾
7.5
16
mA
ISTB1
Standby Current (WDT Enabled)
5V
No load, system HALT,
USB suspend
¾
¾
250
mA
ISTB2
Standby Current (WDT Disabled)
5V
No load, system HALT,
USB suspend
¾
¾
230
mA
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.8
V
VIH1
Input High Voltage for I/O Ports
5V
¾
2
¾
5
V
5V
¾
0
¾
0.4VDD
V
5V
¾
0.9VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
VIH2
Input High Voltage (RES)
IOL1
I/O Port Sink Current for PA1~PA7, PB, PC,
5V
PD
VOL=3.4V
10
15
20
mA
IOL2
I/O Port Sink Current for PA1~PA7, PB, PC,
5V
PD
VOL=0.4V
2
4
8
mA
IOL3
I/O Port Sink Current for PA0
5V
VOL=0.4V
7
10
13
mA
IOH1
I/O Port Source Current for PA1~PA7, PB,
5V
PC, PD
VOH=3.4V
-2
-4
-8
mA
IOH2
I/O Port Source Current for PA0
5V
VOH=3.4V
-12
-18
-24
mA
RPH
Pull-high Resistance for PA, PB, PC, PD
5V
¾
25
50
80
kW
VLVR
Low Voltage Reset
¾
¾
3
3.4
4.0
V
VV33O
3.3V Regulator Output
5V
IV33O=-5mA
3.0
3.3
3.6
V
A.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min.
Typ. Max.
Unit
fSYS
System Clock (Crystal OSC)
5V
¾
6
¾
12
MHz
fTIMER
Timer I/P Frequency (TMR)
5V
¾
0
¾
12
MHz
5V
¾
15
31
70
ms
tWDTOSC Watchdog Oscillator
tWDT1
Watchdog Time-out Period (WDT OSC)
5V
Without WDT prescaler
4
8
16
ms
tWDT2
Watchdog Time-out Period (System Clock)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Wake-up from HALT
¾
1024
¾
tSYS
tSST
System Start-up Timer Period
¾
Power-up, Watchdog
Time-out from normal
¾
1024
¾
tWDTOSC
1
¾
¾
ms
tINT
Rev. 1.20
Interrupt Pulse Width
¾
4
¾
August 28, 2006
HT82K95EE/HT82K95AE
EEPROM A.C. Characteristics
Symbol
Ta=25°C
Parameter
Remark
Standard Mode*
VCC=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the first
clock pulse is generated
4000
¾
600
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
ns
4700
¾
1200
¾
ns
¾
100
¾
50
ns
¾
5
¾
5
ms
tBUF
Bus Free Time
Time in which the bus must
be free before a new transmission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
tWR
Write Cycle Time
Note:
¾
These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams
Rev. 1.20
5
August 28, 2006
HT82K95EE/HT82K95AE
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
a crystal. The system clock is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupts, the PC manipulates
the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme allows each instruction
to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
USB interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.20
@[email protected]: PCL bits
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August 28, 2006
HT82K95EE/HT82K95AE
· Location 00CH
Program Memory - ROM
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
· Table location
Certain locations in the program memory are reserved
for special usage:
Any location in the program memory can be used as
look-up tables. There are three method to read the
ROM data by two table read instructions: ²TABRDC²
and ²TABRDL², transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H).
The three methods are shown as follows:
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
0 0 0 H
U S B In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Instruction
The instructions ²TABRDC [m]² (the current page,
one page=256words), where the table locations is
defined by TBLP (07H) in the current page. And the
ROM code option TBHP is disabled (default).
¨
The instructions ²TABRDC [m]², where the table locations is defined by registers TBLP (07H) and
TBHP (01FH). And the ROM code option TBHP is
enabled.
¨
The instructions ²TABRDL [m]², where the table locations is defined by Registers TBLP (07H) in the
last page (0F00H~0FFFH).
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before accessing the table, the location must be placed in the
TBLP and TBHP (If the OTP option TBHP is disabled,
the value in TBHP has no effect). The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
¨
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
@[email protected]: Table pointer bits
Rev. 1.20
P11~P8: Current program counter bits when TBHP is disabled
TBHP register bit3~bit0 when TBHP is enabled
7
August 28, 2006
HT82K95EE/HT82K95AE
B a n k 0
It will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the ROM code option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM
data as defined by TBLP and the current program
counter bits.
0 0 H
Stack Register - STACK
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
U S C
1 B H
U S R
1 C H
S C C
S p e c ia l P u r p o s e
D a ta M e m o ry
1 D H
1 E H
1 F H
2 0 H
T B H P
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
: U n u s e d ,
re a d a s "0 0 "
B F H
Bank 0 RAM Mapping
Data Memory - RAM for Bank 0
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H, PD;18H), I/O
control registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H). USB/PS2 status and control register
(USC;1AH), USB endpoint interrupt status register
(USR;1BH), system clock control register (SCC;1CH).
The remaining space before the 20H is reserved for future expansion usage and reading these locations will
get ²00H². The general purpose data memory, addressed from 20H to BFH, is used for data and control
information under instruction commands.
The data memory is designed with 190´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (160´8). Most are read/write, but some are read
only.
The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register
(BP, 04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H, TBHP;1FH), table higher-order
byte register (TBLH;08H), status register
Rev. 1.20
In d ir e c t A d d r e s s in g R e g is te r 0
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
8
August 28, 2006
HT82K95EE/HT82K95AE
Data Memory - RAM for Bank 1
Accumulator
The special function registers used in USB interface are
located in RAM bank 1. In order to access the Bank1
register, only the Indirect addressing pointer MP1 can
be used and the Bank register BP should be set to ²1².
The mapping of RAM bank 1 is as shown.
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Indirect Addressing Register
Arithmetic and Logic Unit - ALU
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results
in no operation.
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
The indirect addressing pointer (MP0) always point to
Bank0 RAM addresses regardless of the value of the
Bank Register (BP).
· Branch decision (SZ, SNZ, SIZ, SDZ)
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
The ALU not only saves the results of a data operation
but also changes the status register.
The indirect addressing pointer (MP1) can access
Bank0 or Bank1 RAM data according to the value of BP
which is set to ²0² or ²1² respectively.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
4 0 H
4 1 H
P IP E _ C T R L
4 2 H
A W R
4 3 H
S T A L L
4 4 H
P IP E
4 5 H
S IE S
4 6 H
M IS C
4 7 H
E n d p t_ E N
4 8 H
F IF O 0
4 9 H
F IF O 1
4 A H
F IF O 2
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended.
The TO flag can be affected only by system power-up, a
WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.
4 B H
4 C H
U n d e fin e d , r e s e r v e d
fo r fu tu r e e x p a n s io n
F F H
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Bank 1 RAM Mapping
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
9
August 28, 2006
HT82K95EE/HT82K95AE
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the HT82K95EE/
HT82K95AE, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When the interrupt
has been served, the corresponding bit should be
cleared by firmware. When the HT82K95EE/
HT82K95AE receives a USB Suspend signal from the
Host PC, the suspend line (bit0 of the USC) of the
HT82K95EE/HT82K95AE is set and a USB interrupt is
also triggered.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from
becoming full.
Also when the HT82K95EE/HT82K95AE receives a Resume signal from the Host PC, the resume line (bit3 of
the USC) of HT82K95EE/HT82K95AE is set and a USB
interrupt is triggered.
Whenever a USB reset signal is detected, the USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (; bit 5 of INTC), caused by a timer 0 overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
The internal Timer/Even Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (;bit 6 of INTC), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and the T1F
is set, a subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (if the stack is not full).
To return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
· The corresponding USB FIFO is accessed from the
PC
· The USB suspends signal from the PC
· The USB resumes signal from the PC
· The USB sends Reset signal
Bit No.
Label
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
Function
1
EUI
Controls the USB interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
4
USBF
USB interrupt request flag (1= active; 0= inactive)
5
T0F
6
T1F
7
¾
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.20
10
August 28, 2006
HT82K95EE/HT82K95AE
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Priority Vector
a
USB interrupt
1
04H
b
Timer/Event Counter 0 overflow
2
08H
c
Timer/Event Counter 1 overflow
3
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable USB interrupt bit (EUI) and enable master interrupt
bit (EMI) constitute an interrupt control register (INTC)
which is located at 0BH in the data memory. EMI, EUI,
ETI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags (TF,
USBF) are set, they will remain in the INTC register until
the interrupts are serviced or cleared by a software instruction.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determines the ROM code option. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator, normally with a period of 31ms at 5V) is selected, it is first divided by 256 (8-stage) to get the nominal time-out
period of 8ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s at 5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are reserved for user¢s defined flags, which can only be set to
²10000² (WDTS.7~WDTS.3).
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
O S C 1
O S C 2
C r y s ta l O s c illa to r
System Oscillator
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an external signal to conserve power.
S y s te m
C lo c k /4
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.20
11
August 28, 2006
HT82K95EE/HT82K95AE
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
cuting the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP, the others remain
in their original status.
The I/O ports wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
bit in the Port A can be independently selected to wake
up the device by option. PB, PC and PD can also be selected to wake up the device by option. Upon awakening
from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full,
the regular interrupt response takes place. If an interrupt
request flag is set to ²1² before entering the HALT mode,
the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In
other words, a dummy period will be inserted after a
wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake up
results in the next instruction execution, this will be executed immediately after the dummy period is completed.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are employed; external reset
(a low level to RES), software instruction and a ²HALT²
instruction. The software instruction include ²CLR
WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the ROM code option - ²CLR
WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of
the ²CLR WDT² instruction will clear the WDT. In the
case wherein ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT,
otherwise, the WDT may reset the chip as a result of
time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
Power Down Operation - HALT
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
TO PDF
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on I/O ports or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when exe-
Rev. 1.20
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
12
August 28, 2006
HT82K95EE/HT82K95AE
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
when the system awakes from the HALT state.
H A L T
When a system reset occurs, an SST delay is added
during the reset period. Any wake up from HALT will enable the SST delay.
R E S
W a rm
W D T
tS
S T
S y s te m
S S T T im e - o u t
C h ip
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
V D D
R E S
R e s e t
R e s e t
Reset Configuration
R e s e t
The functional unit chip reset status are shown below.
Reset Timing Chart
V
D D
R E S
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Reset Circuit
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The status of the registers are summarized in the following table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
Program
Counter
000H
000H
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
Register
Rev. 1.20
13
August 28, 2006
HT82K95EE/HT82K95AE
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PIPE_CTRL
0000 0111
uuuu uuuu
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PIPE
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0111
uuuu uuuu
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
SIES
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
Endpt_EN
0000 0111
uuuu uuuu
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
USC
11xx 0000
uuxx uuuu
11xx 0000
11xx 0000
uuxx uuuu
uu00 0u00
uu00 0u00
USR
0100 0000
uuuu uuuu
0100 0000
0100 0000
uuuu uuuu
u1uu 0000
u1uu 0000
SCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0uu0 u000
0uu0 u000
Register
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may comes from an external source or from
fSYS/4.
The Timer/Event Counter 1 contains an 16-bit programmable count-up counter and the clock may come from
an external source or from the system clock divided by
4.
Bit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
Function
3
TE
To define the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
4
TON
To enable/disable timer 0 counting (0=disabled; 1=enabled)
6
7
TM0
TM1
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
Function
3
TE
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
4
TON
To enable/disable timer 1 counting (0=disabled; 1=enabled)
6
7
TM0
TM1
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.20
14
August 28, 2006
HT82K95EE/HT82K95AE
fS
Y S
D a ta B u s
/4
T M 1
T M 0
T M R 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T im e r /E v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
O v e r flo w
to In te rru p t
Timer/Event Counter 0
D a ta B u s
fS
Y S /4
T M 1
T M 0
T M R 1
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
L o w B y te
B u ffe r
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 1
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4
(Timer0/Timer1). The pulse width measurement mode
can be used to count the high or low level duration of the
external signal (TMR0/TMR1). The counting is based on
the fSYS/4 (Timer0/Timer1).
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 0. The internal clock
source is coming from fSYS/4.
The external clock input allows the user to count external events, measure time intervals or pulse widths.
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 1. The internal clock
source is coming from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH or
FFFFH. Once overflow occurs, the counter is reloaded
from the Timer/Event Counter 0/1 preload register and
generates the interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
There are 2 registers related to the Timer/Event Counter
0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 makes
the starting value be placed in the Timer/Event Counter
0 preload register and reading TMR0 gets the contents
of the Timer/Event Counter 0. The TMR0C is a timer/
event counter control register, which defines some options.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low if the
TE bits is ²0²) it will start counting until the TMR0/TMR1
returns to the original level and resets the TON. The
measured result will remain in the Timer/Event Counter
0/1 even if the activated transient occurs again. In other
words, only one cycle measurement can be done. Until
setting the TON, the cycle measurement will function
again as long as it receives further transient pulse. Note
that, in this operating mode, the Timer/Event Counter
0/1 starts counting not according to the logic level but
according to the transient edges. In the case of counter
overflows, the Counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting enable or disable and active edge.
Rev. 1.20
15
August 28, 2006
HT82K95EE/HT82K95AE
structures can be reconfigured dynamically under software control. To function as an input, the corresponding
latch of the control register must write a ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction. For output function,
CMOS/NMOS/PMOS configurations can be selected
(NMOS and PMOS are available for PA only). These
control registers are mapped to locations 13H, 15H, 17H
and 19H.
of TMR0C/TMR1C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in
the other two modes the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload register will also reload that data to the Timer/Event Counter
0/1. But if the Timer/Event Counter 0/1 is turned on, data
written to it will only be kept in the Timer/Event Counter
0/1 preload register. The Timer/Event Counter 0/1 will still
operate until overflow occurs (a Timer/Event Counter 0/1
reloading will occur at the same time). When the
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 32 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to the data memory of [12H], [14H], [16H] and
[18H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m=12H,
14H, 16H or 18H). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten.
Each line of all the I/O ports have the capability of waking up the device.
There are pull-high (PA only) options available for I/O
lines. Once the pull-high option of an I/O line is selected,
the I/O line have pull-high resistor. Otherwise, the
pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS/NMOS/PMOS output
or Schmitt trigger input with or without pull-high resistor
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
D D
P u ll- h ig h
Q
C K
S
P A
P A
P A
P B
P B
P B
P C
P D
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
W a k e -u p fo r a n y I/O
D a ta B it
Q
D
C K
S
0 ~
6 /T
7 /T
0 ~
6 /S
7 /S
0 ~
0 ~
P A
M
M
P B
C
D
P C
P D
L
5
R 0
R 1
5
A
7
7
Q
M
P u ll- lo w
U
X
P o rt
W a k e - u p O p tio n fo r a n y I/O
P A 7 /T M R
P o rt
Input/Output Ports
Rev. 1.20
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August 28, 2006
HT82K95EE/HT82K95AE
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .3 V
· For a valid LVR signal, a low voltage i.e. a voltage in
3 .0 V
the range between 0.9V~VLVR must exist for greater
than 1ms. If the low voltage state does not exceed
1ms, the LVR will ignore it and do not perform a reset
function.
· The LVR uses the ²OR² function with the external
Note:
RES signal to perform chip reset.
V
V
0 .9 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1. To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2. Since low voltage has to be maintained for over 1ms in its original state, therefore there¢s a 1ms delay
before entering the reset mode
Rev. 1.20
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August 28, 2006
HT82K95EE/HT82K95AE
Data EEPROM Functional Description
· Serial clock (SCL)
Device Addressing
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
The 1K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
The next three bits are the fixed to be ²0².
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Memory Organization
· 1K Serial EEPROM
Internally organized with 128 8-bit words, the 1K requires an 8-bit data word address for random word addressing.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Device Operations
1
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
0
1
0
0
0
0
R /W
D e v ic e A d d r e s s
Write Operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth
clock cycle.
· Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
D a ta a llo w e d
to c h a n g e
S D A
S C L
S ta rt
c o n d itio n
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
S to p
c o n d itio n
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A
S
S ta rt
P
R /W
A C K
A C K
A C K
S to p
Byte Write Timing
Rev. 1.20
18
August 28, 2006
HT82K95EE/HT82K95AE
first page. The address roll over during write from the
last byte of the current page to the first byte of the
same page. Once the device address with the
read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address
data word is serially clocked out. The microcontroller
should respond a No ACK (High) signal and following
stop condition (refer to Current read timing).
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
· Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition.
(refer to Random read timing).
N o
Y e s
N e x t O p e r a tio n
Acknowledge Polling Flow
· Read operations
· Sequential read
The data EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an
acknowledgment. As long as the EEPROM receives an
acknowledgment, it will continue to increment the data
word address and serially clock out sequential data
words. When the memory address limit is reached, the
data word address will roll over and the sequential read
continues. The sequential read operation is terminated
when the microcontroller responds with a ²no ACK² signal (high) followed by a stop condition.
· Current address read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the
D e v ic e a d d r e s s
S D A
D A T A
S to p
S
P
S ta rt
A C K
N o A C K
Current Read Timing
D e v ic e a d d r e s s
W o rd a d d re s s
S
S
S D A
D A T A
D e v ic e a d d r e s s
S ta rt
P
A C K
S ta rt
A C K
S to p
A C K
N o A C K
Random Read Timing
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
S
S ta rt
D A T A n + x
S to p
P
A C K
A C K
N o A C K
Sequential Read Timing
Rev. 1.20
19
August 28, 2006
HT82K95EE/HT82K95AE
Data EEPROM Timing Diagrams
tf
tr
tL
S C L
tS
S D A
U
:S
tH
T A
tS
tH
IG H
D
O W
:S
T A
tH
D
:D
tS
A T
:D
U
A T
tS
U
tB
U F
:S
T O
P
tA
S D A
A
V a lid
O U T
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
S to p
C o n d itio n
Note:
R
S ta rt
C o n d itio n
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Suspend Wake-Up and Remote Wake-Up
S U S P E N D
If there is no signal on the USB bus for over 3ms, the
HT82K95EE/HT82K95AE will go into suspend mode.
The Suspend line (bit 0 of the USC) will be set to ²1² and
a USB interrupt is triggered to indicate that the
HT82K95EE/HT82K95AE should jump to the suspend
state to meet the 500mA USB suspend current spec.
U S B R e s u m e S ig n a l
U S B _ IN T
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the
USBCKEN (bit3 of the SCC) to ²0². The suspend current is 400mA.
The device with remote wake up function can wake up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of the USC). Once the USB Host receives
a wake-up signal from the HT82K95EE/HT82K95AE, it
will send a Resume signal to the device. The timing is as
follows:
User can further decrease the suspend current to 250mA
by setting the SUSP2 (bit4 of the SCC). But if the
SUSP2 is set, user should make sure not to enable the
LVR OPT o p t i on, ot her w i s e t h e H T82K 9 5 E E /
HT82K95AE will be reset.
S U S P E N D
M in . 1 U S B C L K
When the resume signal is sent out by the host, the
HT82K95EE/HT82K95AE will wake-up the MCU by
USB interrupt and the Resume line (bit 3 of the USC) is
set. In order to make the HT82K95EE/HT82K95AE
function properly, the firmware must set the USBCKEN
(bit 3 of the SCC) to ²1² and clear the SUSP2 (bit4 of the
SCC). Since the Resume signal will be cleared before
the Idle signal is sent out by the host, the Suspend line
(bit 0 of the USC) will be set to ²0². So when the MCU is
detecting the Suspend line (bit0 of USC), the Resume
line should be remembered and taken into consideration.
R M W K
U S B R e s u m e S ig n a l
M in .2 .5 m s
U S B _ IN T
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The following is the timing diagram.
Rev. 1.20
20
August 28, 2006
HT82K95EE/HT82K95AE
To Configure the HT82K95EE/HT82K95AE as PS2 Device
The HT82K95EE/HT82K95AE can be configured as a USB interface or PS2 interface device, by configuring the SPS2
(bit 4 of USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the HT82K95EE/HT82K95AE is configured as a
PS2 interface, pin USBD- is configured as a PS2 Data pin and USBD+ is configured as a PS2 Clk pin. User can easily
read or write to the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit
5 of the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7 of the USC) respectively.
User should make sure that in order to read the data properly, the corresponding output bit must be set to ²1². For example, if it is desired to read the PS2 Data by reading PS2DAI, the PS2DAO should set to ²1². Otherwise it is always
read as ²0².
If SPS2=0, and SUSB=1, the HT82K95EE/HT82K95AE is configured as a USB interface. Both the USBD- and USBD+
is driven by the SIE of the HT82K95EE/ HT82K95AE. User can only write or read the USB data through the corresponding FIFO.
Both SPS2 and SUSB default is ²0².
USB Interface
There are ten registers, including PIPE_CTRL (41H in bank 1), AWR (address + remote wake-up 42H in bank 1),
STALL (43H in bank 1), PIPE (44H in bank 1), SIES (45H in bank 1), MISC (46H in bank 1), Endpt_EN (47H in bank 1),
FIFO0 (48H in bank 1), FIFO1 (49H in bank 1), and FIFO2 (4AH in bank 1) used for the USB function. AWR register
contains current address and a remote wake up function control bit. The initial value of AWR is ²00H². The address
value extracted from the USB command is not to be loaded into this register until the SETUP stage is completed.
Bit No.
Label
R/W
Function
0
WKEN
W
Remote wake-up enable/disable
7~1
AD6~AD0
W
USB device address
AWR (42H) Register
STALL and PIPE, PIPE_CTRL, Endpt_EN Registers
PIPE register represents whether the endpoint corresponding is accessed by host or not. After ACT_EN signal being
sent out, MCU can check which endpoint had been accessed. This register is set only after the time when host access
the corresponding endpoint.
STALL register shows whether the endpoint corresponding works or not. As soon as the endpoint work improperly, the
bit corresponding must be set.
PIPE_CTRL Register is used for configuring IN (Bit=1) or OUT (Bit=0)Pipe. The default is define IN pipe. Where Bit0
(DATA0) of the PIPE_CTRL Register is used to setting the data toggle of any endpoint (except endpoint0) using data
toggles to the value DATA0. Once the user want the any endpoint (except endpoint0) using data toggles to the value
DATA0. the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle.
Endpt_EN Register is used to enable or disable the corresponding endpoint (except endpoint 0) Enable Endpoint
(Bit=1) or disable Endpoint (Bit=0)
The bitmaps are list as follows :
Register
Name
R/W
Register
Address
Bit7~Bit3 Reserved
Bit 2
Bit 1
Bit 0
Default
Value
PIPE_CTRL
R/W
01000001B
¾
Pipe 2
Pipe 1
Pipe 0
00000111
STALL
R/W
01000011B
¾
Pipe 2
Pipe 1
Pipe 0
00000111
R
01000100B
¾
Pipe 2
Pipe 1
Pipe 0
00000000
R/W
01000001B
¾
Pipe 2
Pipe 1
Pipe 0
00000111
PIPE
Endpt_EN
PIPE_CTRL (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers
Rev. 1.20
21
August 28, 2006
HT82K95EE/HT82K95AE
The SIES Register is used to indicate the present signal state which the SIE receives and also defines whether the SIE
has to change the device address automatically.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Func.
NMI
EOT
CRC_ERR
NAK
IN
OUT
F0_ERR
Adr_set
R/W
R/W
R
R/W
R
R
R/W
R/W
R/W
01000101B
Reg_ Adr
SIES (45H) Register Table
Func. Name
R/W
Description
Adr_ set
R/W
This bit is used to configure the SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register (42H).
When this bit is set to ²1² by F/W, the SIE will update the device address with the value
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully
read the data from the device by the IN operation. The SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to ²0², the SIE will update
the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H)
Default 0
F0_Err
R/W
This bit is used to indicate that some errors have occurred when accessing the FIFO0.
This bit is set by SIE and cleared by F/W.
Default 0
Out
R/W
This bit is used to indicate that an OUT token (except for the OUT zero length) has
been received. The F/W clear the bit after the OUT data has been read. This bit will
also be cleared by the SIE after the next valid SETUP token is received.
Default 0
IN
R
This bit is used to indicate that the current signal the USB is receiving from the PC
Host is IN token.
NAK
R
This bit is used to indicate that the SIE is transmitting NAK signal to the Host in response to the PC Host IN or OUT token.
CRC_ERR
R/W
This bit is used to indicate there are CRCerror (bit=1). Firmware must do something to
save the device and keep it in good condition.
This bit is set by SIE and cleared by F/W.
EOT
R
End of transaction flag, normal status is 1. If suspend=¢1¢ line & EOT=¢0¢ indicates that
something is wrong in the USB Interface. Firmware in-charge must do something to
save the device and keep it in good condition.
R/W
This bit is used to control whether the USB interrupt is output to the MCU in NAK response to the PC Host IN or OUT token.
1: has only USB interrupt, data is transmitted to the PC host or data is received from
the PC Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
NMI
SIES Function Table
Rev. 1.20
22
August 28, 2006
HT82K95EE/HT82K95AE
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the
desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No.
Label
0
REQ
R/W
Function
R/W
After setting the other status of the desired one in the MISC, endpoint FIFO can be
requested by setting this bit to ²1². After the job has been done, this bit has to be
cleared to ²0².
1
TX
R/W
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to ²1², this means that the MCU wants to write data to the endpoint FIFO. After the job has been done, this bit has to be cleared to ²0² before terminating request to represent the end of transferring. For reading action, this bit has to
be cleared to ²0² to represent that MCU wants to read data from the endpoint FIFO
and has to be set to ²1² after the job is done.
2
CLEAR
R/W
Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
4
3
SELP1
SELP0
R/W
Defines which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: reserved
5
SCMD
R/W
Used to show that the data in endpoint FIFO is a SETUP command. This bit has to
be cleared by firmware. That is to say, even the MCU is busy, the device will not miss
any SETUP commands from the host.
6
READY
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready to work.
7
LEN0
R/W
Used to indicate that a 0-sized packet is sent from a host to the MCU. This bit should
be cleared by firmware.
MISC (46H) Register
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which address is listed in
the following table. After reading the current data, next data will show after 2ms, used to check the endpoint FIFO status
and response to MISC register, if read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay 2ms, check 4BH®write* to FIFO1 register and
check not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO1 can be written or not
0AH®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH
Read 0-sized packet sequence form FIFO0
00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H
Write 0-sized packet sequence to FIFO1
0AH®0BH®delay 2ms, check 0BH®0FH®0DH®08H
Note:
*: There are 2ms existing between 2 reading action or between 2 writing action
Rev. 1.20
23
August 28, 2006
HT82K95EE/HT82K95AE
The definitions of the USB/PS2 status and control register (USC; 1AH) are as shown.
Bit No.
Label
R/W
Function
0
SUSP
R
Read only, USB suspend indication. When this bit is set to ²1² (set by SIE), it indicates the USB bus enters suspend mode. The USB interrupt is also triggered on any
changes of this bit.
1
RMWK
W
USB remote wake up command. It is set by MCU to force the USB host leaving the
suspend mode. When this bit is set to ²1², 2ms delay for clearing this bit to ²0² is
needed to insure the RMWK command is accepted by SIE.
R/W
USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect
which bus (PS2 or USB) is attached. When the URST is set to ²1², this indicates that
a USB reset has occurred (the attached bus is USB) and a USB interrupt will be initialized.
2
URST
3
RESUME
R
USB resume indication. When the USB leaves the suspend mode, this bit is set to
²1² (set by SIE). This bit will appear 20ms waiting for the MCU to detect. When the
RESUME is set by the SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set the USBCKEN and clear
SUSP2 (in SCC register) to enable the SIE detecting function. The RESUME will be
cleared while the SUSP is going ²0². When the MCU is detecting the SUSP, the RESUME (wakes-up the MCU ) should be remembered and taken into consideration.
4
PS2DAI
R
Read only, USBD-/DATA input
5
PS2CKI
R
Read only, USBD+/CLK input
6
PS2DAO
W
Data for driving the USBD-/DATA pin when working under 3D PS2 mouse function.
(Default=²1²)
7
PS2CKO
W
Data for driving the USBD+/CLK pin when working under 3D PS2 mouse function.
(Default=²1²)
USC (1AH) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF and EP2IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served,
the endpoint request flag has to be cleared to ²0².
Bit No.
Label
R/W
Function
0
EP0IF
R/W
When this bit is set to ²1² (set by the SIE), it indicates the endpoint 0 is accessed and
a USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
1
EP1IF
R/W
When this bit is set to ²1² (set by the SIE), it indicates the endpoint 1 is accessed and
a USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
2
EP2IF
R/W
When this bit is set to ²1² (set by the SIE), it indicates the endpoint 2 is accessed and
a USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
3, 6
¾
¾
4
SPS2
R/W
The PS2 function is selected when this bit is set to ²1². (Default=²0²)
5
SUSB
R/W
The USB function is selected when this bit is set to ²1². (Default=²0²)
7
USB_flag
R/W
This flag is used to show the MCU is in USB mode. (Bit=1)
This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)
Reserved
USR (1BH) Register
Rev. 1.20
24
August 28, 2006
HT82K95EE/HT82K95AE
There is a system clock control register implemented to select the clock used in the MCU. This register consists of the
USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).
Bit No.
Label
R/W
2~0, 7
¾
¾
3
Function
Undefined, should be cleared to ²0²
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=²0²)
USBCKEN R/W
4
SUSP2
R/W
This bit is used for decreasing power consumption in suspend mode.
In normal mode clean this bit=0 (Default=²0²)
In HALT mode set this bit=1 for decreasing power consumption.
5
PS2_flag
R/W
This flag is used to show the MCU is under PS2 mode. (Bit=1)
This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)
6
SYSCLK
R/W
This bit is used to specify the system oscillator frequency used by the MCU. If a
6MHz crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz
crystal oscillator or resonator is used, this bit should be cleared to ²0² (default).
SCC (1CH) Register
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
Register
TBHP (0X1F)
Bits
Labels
Read/Write
Option
3~0
PGC3~PGC0
R/W
¾
Functions
Store current table read bit11~bit8 data
Options
The following table shows all kinds of option in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Option
1
Chip lock bit (by bit)
2
PA0~PA7 pull-high resistor enabled or disabled (by bit)
3
PB0~PB7 pull-high resistor enabled or disabled (by nibble)
4
PC0~PC7 pull-high resistor enabled or disabled (by nibble)
5
PD0~PD7 pull-high resistor enabled or disabled (by nibble)
6
LVR enable or disable
7
WDT enable or disable
8
WDT clock source: fSYS/4 or WDTOSC
9
²CLRWDT² instruction(s): 1 or 2
10
PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit)
11
PA0~PA7 wake-up enabled or disabled (by bit)
12
PB0~PB7 wake-up enabled or disabled (by nibble)
13
PC0~PC7 wake-up enabled or disabled (by nibble)
14
PD0~PD7 wake-up enabled or disabled (by nibble)
15
TBHP enable or disable (default disable)
Rev. 1.20
25
August 28, 2006
HT82K95EE/HT82K95AE
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
5 W
V D D
U S B -
0 .1 m F
U S B +
*
*
3 3 W
1 0 m F
1 0 0 k W
P A 0 ~ P A 7
*
V D D
0 .1 m F
1 M W ***
P D 0 ~ P D 7
2 2 p F
V S S
5 W
**
*
O S C 1
X 1
2 2 p F
1 0 k W
0 .1 m F
*
O S C 2
**
0 .1 m F
P B 0 ~ P B 7
P C 0 ~ P C 7
R E S
0 .1 m F
4 7 p F *
3 3 W
U S B D -/D A T A
4 7 p F *
*
V S S
*
*
*
4 7 p F
3 3 W
U S B D + /C L K
H T 8 2 K 9 5 E E /H T 8 2 K 9 5 A E
Note:
1 .5 k W
V 3 3 O
*
4 7 p F
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible.
Components with * are used for EMC issue.
Components with ** are used for resonator only.
Components with *** are used for 12MHz application.
Rev. 1.20
26
August 28, 2006
HT82K95EE/HT82K95AE
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.20
27
August 28, 2006
HT82K95EE/HT82K95AE
Mnemonic
Description
Instruction
Cycle
Flag
Affected
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
2(1)
2(1)
2(1)
None
None
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Branch
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m](5) Read ROM code (locate by TBLP and TBHP) to data memory and TBLH
TABRDC [m](6) Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
(5)
: ²ROM code TBHP option² is enabled
(6)
: ²ROM code TBHP option² is disabled
Rev. 1.20
28
August 28, 2006
HT82K95EE/HT82K95AE
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
29
August 28, 2006
HT82K95EE/HT82K95AE
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
August 28, 2006
HT82K95EE/HT82K95AE
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
August 28, 2006
HT82K95EE/HT82K95AE
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
August 28, 2006
HT82K95EE/HT82K95AE
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
August 28, 2006
HT82K95EE/HT82K95AE
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
August 28, 2006
HT82K95EE/HT82K95AE
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
August 28, 2006
HT82K95EE/HT82K95AE
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
36
August 28, 2006
HT82K95EE/HT82K95AE
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
August 28, 2006
HT82K95EE/HT82K95AE
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
August 28, 2006
HT82K95EE/HT82K95AE
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
August 28, 2006
HT82K95EE/HT82K95AE
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code
TBHP is enabled)
Description
The low byte of ROM code addressed by the table pointer (TBLP and TBHP) is moved to
the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory (ROM code TBHP is disabled)
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
August 28, 2006
HT82K95EE/HT82K95AE
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
August 28, 2006
HT82K95EE/HT82K95AE
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
42
August 28, 2006
HT82K95EE/HT82K95AE
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
330±1
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.20
43
August 28, 2006
HT82K95EE/HT82K95AE
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.20
21.3
44
August 28, 2006
HT82K95EE/HT82K95AE
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
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709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this handbook is believed to be accurate at the time of publication. However, Holtek assumes
no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for
the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without
further modification, nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.20
45
August 28, 2006