S PDS106A SP Voice Engine SEP. 05, 2001 Version 1.0 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. SPDS106A Table of Contents PAGE 1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 4. APPLICATION FIELDS ............................................................................................................................................................................... 3 5. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 6.1. DATA RAM MAPPING.............................................................................................................................................................................. 5 6.2. PWM .................................................................................................................................................................................................... 5 6.3. SPC MAPPING ...................................................................................................................................................................................... 5 6.4. RTC (REAL TIME CLOCK)....................................................................................................................................................................... 5 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 6 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 6 7.2. DC CHARACTERISTICS (VDD = 4.5V, TA = 25℃).................................................................................................................................... 6 7.3. THE RELATIONSHIP BETWEEN THE ROSC AND THE SYSTEM CLOCK (FOSC) ................................................................................................. 7 7.4. IOA, IOB, IOC, IOD I/O DRIVING CHARACTERISTIC ............................................................................................................................... 7 8. APPLICATION CIRCUITS........................................................................................................................................................................... 8 8.1. APPLICATION CIRCUIT - (1)..................................................................................................................................................................... 8 8.2. APPLICATION CIRCUIT - (2)..................................................................................................................................................................... 9 8.3. APPLICATION CIRCUIT - (3)................................................................................................................................................................... 10 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 11 9.1. PAD ASSIGNMENT ................................................................................................................................................................................11 9.2. ORDERING INFORMATION ......................................................................................................................................................................11 9.3. PAD LOCATIONS .................................................................................................................................................................................. 12 10. DISCLAIMER............................................................................................................................................................................................. 13 11. REVISION HISTORY ................................................................................................................................................................................. 14 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 SEP. 05, 2001 Version: 1.0 SPDS106A VOICE ENGINE 1. GENERAL DESCRIPTION 3. BLOCK DIAGRAM SPDS106A, a single chip contains an 8-bit RISC microprocessor The integration method of CPU and DSP is using a shared (CPU) and a 16-bit digital signal processor (DSP), is applied for memory block in between two processors and each register or I/O constituting long duration audio applications. in CPU will correspond to specified register in DSP. The CPU The transmits commands and data to DSP by the means of following diagram simply describes the access between CPU and memory-mapped (parallel interface). DSP. The CPU employs 23 general I/Os to access external devices. The 256K x 8 ROM RTC (Real Time Clock) hold the system control program, audio processing program and audio data. The DSP receives the commands and data from CPU and finally runs the decompressing algorithm. Both CPU and DSP share a PWM output for audio. CPU DSP 2. FEATURES CPU View DSP View ! 8-bit RISC microprocessor (CPU) with 256K bytes ROM for program and audio data. (mapping) Address I/O Registers ! CPU with 128 working RAM ! 23 general I/Os Data Bus Address I/O Registers Data Bus ! 7 interrupt sources ! Key change wake up ! 2Hz, 1sec, 2sec, 10sec, 30sec, 1min, 2min or 4min programmable RTC wake up and interrupt. 4. APPLICATION FIELDS ! Shared D/A converter supports three PWM modes: ― 10-bit Push-Pull mode ! Long Duration Audio System ― 10-bit Single-pin double-ended mode ! Intelligent Talking Toys ― 9-bit single-pin single-ended mode ! Talking Instructions ! Kid-Story Books ! Single clock: Crystal OSC or ROSC 20MHz to DSP and 20MHz ! And relevant applications divided by N to CPU, where N = 2, 4, 6, 8, 10, 12, 14 ! Volume control function ! Serial interface I/O ! CPU with two 12-bit timers/counters ! Low voltage reset ! Sleep mode for power saving ! Multi-phase for remote control application ! Max. CPU clock: 5.0MHz @ 2.4V - 5.5V ! SACM_S480, SACM_S720, SACM_S240, SACM_A2400/A3200 and FM synthesizer © Sunplus Technology Co., Ltd. Proprietary & Confidential 3 SEP. 05, 2001 Version: 1.0 SPDS106A 5. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type VDD 8, 16 I Power for chip except shared PWM (Two VDD pins) VSS 7, 23 I Ground for chip except shared PWM (Two VSS pins) XI/R 21 I X’TAL OSC input or ROSC XO 22 O X’TAL OSC output AUDP 2 O Push-Pull and single pin PWM output (shared) AUDN 4 O Push-Pull PWM output (shared) TEST1 24 I Test input, internal pull low, NC TEST2 19 I Test input, internal pull low, NC RESET 20 I Reset input (Active low), internal pull high IOA3 - 0 37 - 40 I/O Programmable I/O pin IOB3 - 0 33 - 36 I/O Programmable I/O pin IOC6 - 0 9 - 15 I/O Programmable I/O pin IOD7 - 0 25 - 32 I/O Programmable I/O pin VDD1 1, 5 I Power for AUDP and AUDN (Two VDD1 pins) VSS1 3 I Ground for AUDP and AUDN TEST3 6 O TEST pin, NC X32I 18 I 32768Hz X’TAL input (for RTC function) X32O 17 O 32768Hz X’TAL output (for RTC function) © Sunplus Technology Co., Ltd. Proprietary & Confidential Description 4 SEP. 05, 2001 Version: 1.0 SPDS106A 6. FUNCTIONAL DESCRIPTIONS 6.1. Data RAM Mapping 6.3. SPC Mapping 6.1.1. DSP *I/O PORT: $0000 ─ PORT IOA Internal Working RAM *MEMORY MAP (From ROM view) $0002 IOB $0003 IOC $0004 IOD $0005 $00000 HW register, I/ Os $00080 USER RAM and STACK ─ I/O CONFIG $0000 $07FF $00100 $0001 $0800 UNUSED $00200 *NMI SOURCE: SUNPLUS TEST PROGRAM ─ INTA (from TIMER A) $00600 USER'S PROGRAM & DATA AREA ROM BANK #0 Exteranl data RAM shared with CPU *INT SOURCE: ─ INTA (from TIMER A) ─ INTB (from TIMER B) $EEEF ─ RTC $FF00 ─ CPU CLK / 1024 $08000 ROM BANK #1 $10000 ROM BANK #2 $18000 ─ CPU CLK / 8192 See Below $FF07 ─ CPU CLK / 65536 $FF08 ─ EXT INT ROM BANK #3 $1FFFF $20000 ROM BANK #4 Memory Mapped I/O $FFFF $38000 FF00: PWM_WR ROM BANK #7 $3FFFF FF01: PWM_SET FF02: TM1_WR & TM1_RD 6.4. RTC (Real Time Clock) FF03: TM2_WR & TM2_RD Some applications require a real time clock for time tracking. Note: Sunplus products are not authorized for use as critical components in SPDS106A provides a RTC based on 2Hz, 1sec, 2sec, 10sec, life support devices/ systems or aviation devices/systems, where a 30sec, 1min, 2min or 4min programmable frequency. malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written SPDS106A approval of the President of Sunplus. 2-second, provides 10-second, programmable 30-second, 1/2-second, 1-minute, The 1-second, 2-minute and 4-minute wake-up sources, the system wakes up every specified 6.2. PWM wake-up source and users can use it as the time tracking resource. SPDS106A offers one set of PWM output for CPU and DSP. In addition, SPDS106A supports 32768 OSC strong mode and Three PWM modes include Push-Pull, Single-pin Double-ended auto mode. and Single-pin Single-ended. highest power. With strong mode, 32768 OSC always runs in the With auto mode, the first 2-second is strong mode and then switch to weak mode to save power. © Sunplus Technology Co., Ltd. Proprietary & Confidential 5 SEP. 05, 2001 Version: 1.0 SPDS106A 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Rating Symbol Supply Voltage Value Unit VDD +0.0 to <7.0 V Input voltage VIN -0.3 to VDD +0.3 V Operating Temperature TA 0 to 55 ℃ TSTG -55 to 125 ℃ Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 7.2. DC Characteristics (VDD = 4.5V, TA = 25℃) Characteristics Symbol Limit Unit Test condition Min. Typ. Max. VDD 2.4 - 5.5 V Operating Current IOP - 17 - mA FOSC = 20MHz @ 4.5V, no load Standby Current ISTB - - 2.0 µA VDD = 4.5V Oscillation Resistor ROSC - 36.5 - KΩ VDD = 4.5V, FSYS = 20MHz Operating Voltage System Clock FSYS - 20 - MHz CPU Clock FCPU 1.4 - 5.0 MHz Input High Voltage VIH 0.7*VDD - VDD V Input Low Voltage VIL VSS - 0.2*VDD V IOH - -3.0 - mA IOL - 7.5 - mA RINH - 64 - KΩ RINL - 24 - KΩ Output High Current (IOA - IOD) Output Low Current (IOA - IOD) Input Pull High Resistor (IOA) Input Pull Low Resistor (IOD) © Sunplus Technology Co., Ltd. Proprietary & Confidential 6 VDD = 4.5V VOH = 4.0V VDD = 4.5V VOH = 0.6V VDD = 4.5V VIN = 0.7*VDD = 3.15V VDD = 4.5V VIN = 0.2*VDD = 0.9V SEP. 05, 2001 Version: 1.0 SPDS106A 7.3. The Relationship between the ROSC and the System 7.4. IOA, IOB, IOC, IOD I/O Driving Characteristic Clock (FOSC) Fosc vs. VDD IOH vs. VOH 1 20.5 Output Current (IOH) Fosc (MHz) 21.0 20.0 19.5 19.0 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 5.8 VDD (V) 1.5 2 2.5 3 3.5 4 4.5 0 -4 -8 -12 -16 Output Voltage (VOH) Fosc vs. Rosc (@VDD=4.5V) 25 IOL vs. VOL 20 15 Output Current (IOL) Fosc (MHz) 30 10 28 30 32 34 36 38 40 42 44 Rosc (KΩ) 20 16 12 8 4 0 0 0.5 1 1.5 2 2.5 Output Voltage (VOL) © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 SEP. 05, 2001 Version: 1.0 SPDS106A 8. APPLICATION CIRCUITS 8.1. Application Circuit - (1) IOA3-0 IOC6-0 IOB3-0 IOD7-0 0.1µ VDD X'TAL/CERAMIC OSC C3 20p C4 XO X32I X32O AUDP (1)VDD1 (5)VDD1 (3)VSS1 AUDN RESET RESET 0.1µ 20p XI/R IOA (I/O) IOC (I/O) TEST1 TEST2 IOB(I/O) IOD (I/O) VDD(16) VDD(8) VSS(7) VSS(23) R1 50K C5 0.1 µ 20p 20p Speaker ~16 Ω IOA3-0 IOC6-0 IOB3-0 IOD7-0 20p* 0.1µ VDD VDD XI/R XO X32I X32O AUDP RESET RESET AUDN (3)VSS1 (5)VDD1 (1)VDD1 Resistor R1 IOA (I/O) IOC (I/O) TEST1 TEST2 IOB(I/O) IOD (I/O) VDD(8) VDD(16) VSS(7) VSS(23) R1 50K C5 0.1 µ SPDS106A Application circuit (PWM Push-Pull Output) VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground SPDS106A 0.1µ 20p 20p Speaker ~16 Ω VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground SEP. 05, 2001 Version: 1.0 8 © Sunplus Technology Co., Ltd. Proprietary & Confidential SPDS106A Note: Capacitor may be increased if necessary. (Cmax = 120p) SPDS106A 8.2. Application Circuit - (2) IOA3-0 IOC6-0 IOB3-0 IOD7-0 VDD X'TAL/CERAMIC OSC C3 C4 XO RESET RESET (3)VSS1 AUDN AUDP (1)VDD1 (5)VDD1 X32O X32I 20p XI/R VSS(23) VSS(7) VDD(8) VDD(16) IOD (I/O) IOB(I/O) TEST2 TEST1 IOC (I/O) IOA (I/O) 20p 0.1µ R1 50K C5 0.1 µ 20p 1K 1K 0.1µ 20p 1K 1K 0.1µ VDD 10K 47µ 47 µ 470 Battery VDD 8050 IOA3-0 IOC6-0 IOB3-0 IOD7-0 VDD 20p* 0.1µ R1 50K VDD XI/R R1 X32I X32O RESET RESET (3)VSS1 AUDN AUDP (1)VDD1 (5)VDD1 XO Resistor IOA (I/O) IOC (I/O) TEST1 TEST2 IOB(I/O) IOD (I/O) VDD(8) VDD(16) VSS(7) VSS(23) C5 0.1 µ SPDS106A single-pin double-ended mode application circuit VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground SPDS106A 20p 1K 1K 0.1µ 20p 1K 1K 0.1µ VDD 10K 47µ 47 µ 470 Battery VDD 8050 VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground Version: 1.0 Proprietary & Confidential SEP. 05, 2001 9 © Sunplus Technology Co., Ltd. SPDS106A Note: *Capacitor may be increased if necessary. (Cmax = 120p) SPDS106A 8.3. Application Circuit - (3) IOA3-0 IOC6-0 IOB3-0 IOD7-0 VDD 0.1µ X'TAL/CERAMIC OSC C3 C4 XO RESET RESET (3)VSS1 AUDN AUDP (1)VDD1 (5)VDD1 X32O X32I 20p XI/R VSS(23) VSS(7) VDD(8) VDD(16) IOD (I/O) IOB(I/O) TEST2 TEST1 IOC (I/O) IOA (I/O) 20p R1 50K C5 0.1 µ 20p 1K 0.1µ 20p 1K 1K 0.1µ VDD 10K 47µ 47 µ 470 Battery VDD 8050 IOA3-0 IOC6-0 IOB3-0 IOD7-0 VDD 0.1µ 20p* R2 50K R1 Resistor XO X32I X32O (5)VDD1 (1)VDD1 AUDP AUDN (3)VSS1 RESET RESET VDD XI/R IOA (I/O) IOC (I/O) TEST1 TEST2 IOB(I/O) IOD (I/O) VDD(16) VDD(8) VSS(7) VSS(23) C3 0.1 µ 20p 1K 0.1µ SPDS106A single-pin single-ended mode application circuit VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground SPDS106A 20p 1K 1K 0.1µ VDD 10K 47µ 47 µ 470 Battery VDD 8050 VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground Version: 1.0 Proprietary & Confidential SEP. 05, 2001 10 © Sunplus Technology Co., Ltd. SPDS106A Note: *Capacitor may be increased if necessary. (Cmax = 120p) SPDS106A 9. PACKAGE/PAD LOCATIONS 9.1. PAD Assignment 1 VDD1 2 AUDP Y 3 VSS1 4 AUDN X (0,0) 5 VDD1 6 TEST3 7 VSS 8 IOA0 40 IOA1 39 IOA2 38 IOA3 37 IOB0 36 IOB1 35 IOB2 34 IOB3 33 IOD0 32 IOD1 31 IOD2 30 IOD3 29 IOD4 28 IOD5 27 IOD6 26 IOD7 25 TEST1 24 VDD VSS IOC1 IOC0 VDD 13 14 15 16 17 XI/R IOC2 12 RESET IOC3 11 TEST2 IOC4 10 X32I IOC5 9 X32O IOC6 XO 18 19 20 21 23 22 Chip Size: 3160µm x 3510µm This IC substrate should be connected to VSS Note1: Chip size included scribe line. Note2: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note3: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type SPDS106A-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z). © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 SEP. 05, 2001 Version: 1.0 SPDS106A 9.3. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y 1 VDD1 -1360 1573 21 XI/R 1216 -1535 2 AUDP -1378 1123 22 XO 1389 -1178 3 VSS1 -1378 708 23 VSS 1370 -1047 4 AUDN -1378 583 24 TEST1 1386 -917 5 VDD1 -1360 133 25 IOD7 1386 -766 6 TEST3 -1378 7 26 IOD6 1386 -607 7 VSS -1378 -156 27 IOD5 1386 -456 8 VDD -1360 -276 28 IOD4 1386 -297 9 IOC6 -857 -1515 29 IOD3 1386 -146 10 IOC5 -706 -1518 30 IOD2 1386 13 11 IOC4 -552 -1517 31 IOD1 1386 164 12 IOC3 -401 -1517 32 IOD0 1386 323 13 IOC2 -246 -1517 33 IOB3 1386 474 14 IOC1 -94 -1517 34 IOB2 1386 632 15 IOC0 61 -1517 35 IOB1 1386 784 16 VDD 214 -1486 36 IOB0 1386 942 17 X32O 384 -1534 37 IOA3 1386 1094 18 X32I 639 -1534 38 IOA2 1386 1249 19 TEST2 849 -1535 39 IOA1 1386 1400 RESET 1096 -1536 40 IOA0 1386 1555 20 © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 SEP. 05, 2001 Version: 1.0 SPDS106A 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 13 SEP. 05, 2001 Version: 1.0 SPDS106A 11. REVISION HISTORY Date Revision # Description JAN. 29, 2000 0.1 Original SEP. 22, 2000 0.2 1. 4 interrupt source -> 7 interrupt sources Page 2. Delete Watchdog timer 3. CPU with 12-bit timers -> CPU with 12-bit timers/counters 4. Operating voltage 2.4V - 5.5V -> 3.6V -> 5.5V 5. Add Volume control function, serial interface I/O, Low voltage reset function MAY. 15, 2001 0.3 1. Add PIN#5 to VDD1. 3 2. Add “Note3: The 0.1µF capacitor between VDD and VSS …” 9 3. Add “REVISION HISTORY” 11 4. Renew to a new document format SEP. 05, 2001 1.0 1. Delete “PRELIMINARY” 2. Modify operating voltage: 3.6V - 5.5V -> 2.4V - 5.5V 2. Connect VDD1 to VDD2, and indicate the pin number. 3. Connect VSS1 to VSS2, and indicate the pin number. 4. Origin: Each VDD (total of two) and VSS (total of two) are connected to 0.1µF capacitors individually. 1, 6 8 - 10 8 - 10 8 - 10 Modification: Connect two VDD together and similarly, connect two VSS and indicate the pin number. The number of capacitor is reduced to one. 5. Disconnet the VDD and speaker where is reindicated as "Battery VDD". 6. Add note in all application circuits 7. Correct chip size 8. Add Note1 in the “9.1 PAD Assignment” 8 - 10 8 - 10 11 11 9. Renew to a new document format © Sunplus Technology Co., Ltd. Proprietary & Confidential 14 SEP. 05, 2001 Version: 1.0