ETC U637256DC70G1

U637256
CapStore 32K x 8 nvSRAM
Features
Description
‡ CMOS non volatile static RAM
32768 x 8 bits
‡ 70 ns Access Time
‡ 35 ns Output Enable Access
Time
‡ ICC = 15 mA typ. at 200 ns Cycle
Time
‡ Unlimited Read and Write Cycles
to SRAM
‡ Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
‡ Software initiated STORE
‡ Automatic STORE Timing
‡ 106 STORE cycles to EEPROM
‡ 100 years data retention in
EEPROM
‡ Automatic RECALL on Power Up
‡ Software RECALL Initiation
‡ Unlimited RECALL cycles from
EEPROM
‡ Single 5 V ± 10 % Operation
‡ Operating temperature range:
0 to 70 °C
-40 to 85°C
‡ QS 9000 Quality Standard
(MIL STD 883C M3015.7)
‡ RoHS compliance and Pb- free
Package: PDIP28 (600 mil)
The U637256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disabled.
The U637256 is a static RAM with
a nonvolatile electrically erasable
PROM (EEPROM) element incorporated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integraed
capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U637256 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initiated under user control via a software sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initiated by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U637256 is pin compatible
with standard SRAMs and standard
battery backed SRAMs.
Pin Description
Pin Configuration
A14
1
28
VCC
A12
2
27
A7
3
26
W
A13
A6
4
25
A8
A5
5
24
A4
6
A3
7
A2
8
PDIP 21
A1
9
20
E
A0
10
19
DQ7
DQ0
11
18
DQ6
DQ1
DQ2
VSS
12
13
14
17
16
15
DQ5
DQ4
DQ3
Signal Name
Signal Description
A9
A0 - A14
Address Inputs
23
A11
DQ0 - DQ7
Data In/Out
22
G
E
Chip Enable
G
Output Enable
W
VCC
Write Enable
VSS
Ground
A10
Power Supply Voltage
Top View
March 31, 2006
STK Control #ML0054
1
Rev 1.0
U637256
Block Diagram
EEPROM Array
512 x (64 x 8)
A5
A6
A7
A8
A9
A11
A12
A13
A14
VCC
Row Decoder
STORE
SRAM
Array
VSS
RECALL
Power
Control
512 Rows x
64 x 8 Columns
Store/
Recall
Control
DQ0
DQ1
VCC
Input Buffers
Column I/O
DQ2
DQ3
DQ4
DQ5
DQ6
Column Decoder
Software
Detect
A0 A1 A2 A3 A4 A10
A0 - A13
G
DQ7
E
W
Truth Table forSRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
VCC
-0.5
7
V
Input Voltage
VI
-0.3
VCC+0.5
V
Output Voltage
VO
-0.3
VCC+0.5
V
Power Dissipation
PD
1
W
Power Supply Voltage
Operating Temperature
Storage Temperature
a:
C-Type
K-Type
Ta
0
-40
70
85
°C
°C
Tstg
-65
150
°C
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK Control #ML0054
2
Rev 1.0
March 31, 2006
U637256
Recommended
Operating Conditions
Symbol
Power Supply Voltage
VCC
Input Low Voltage
VIL
Input High Voltage
VIH
DC Characteristics
Symbol
Conditions
-2 V at Pulse Width
10 ns permitted
Min.
Max.
Unit
4.5
5.5
V
-0.3
0.8
V
2.2
VCC+0.3
V
C-Type
K-Type
Conditions
Unit
Min.
Max.
Min.
Max.
Operating Supply Currentb
ICC1
VCC
VIL
VIH
tc
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
60
65
mA
Average Supply Current duringc
STORE
ICC2
VCC
E
W
VIL
VIH
= 5.5 V
≤ 0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
6
7
mA
Operating Supply Currentb
at tcR = 200 ns
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
15
15
mA
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
tc
= 5.5 V
= VIH
= 70 ns
20
22
mA
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB)
VCC
E
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
3
3
mA
b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 is the average current required for the duration of the SoftStore STORE cycle.
d: Bringing E ≥ VIH will not produce standby current levels until a software initiated nonvolatile cycle in progress has timed out.
See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
STK Control #ML0054
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Rev 1.0
U637256
C-Type
DC Characteristics
Symbol
Unit
Min.
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
VCC
= 5.5 V
VIH
VIL
= 5.5 V
= 0V
VCC
= 5.5 V
VOH
VOL
= 5.5 V
= 0V
Input Leakage Current
High
Low
IIH
IIL
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
K-Type
Conditions
Max.
2.4
Min.
Max.
2.4
0.4
0.4
-4
8
-4
mA
mA
1
μA
μA
8
1
-1
-1
1
-1
1
-1
V
V
μA
μA
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
Min.
Alt.
IEC
Max.
Unit
1
Read Cycle Timef
tAVAV
tcR
2
Address Access Time to Data Validg
tAVQV
ta(A)
70
ns
3
Chip Enable Access Time to Data Valid
tELQV
ta(E)
70
ns
4
Output Enable Access Time to Data Valid
tGLQV
ta(G)
35
ns
5
E HIGH to Output in High-Zh
tEHQZ
tdis(E)
25
ns
6
G HIGH to Output in High-Zh
tGHQZ
tdis(G)
25
ns
7
E LOW to Output in Low-Z
tELQX
ten(E)
5
ns
8
G LOW to Output in Low-Z
tGLQX
ten(G)
0
ns
9
Output Hold Time after Address Change
tAXQX
tv(A)
3
ns
10 Chip Enable to Power Activee
tELICCH
tPU
0
ns
11 Chip Disable to Power Standbyd, e
tEHICCL
tPD
e:
f:
g:
h:
70
ns
70
ns
Parameter guaranteed but not tested.
Device is continuously selected with E and G both Low.
Address valid prior to or coincident with E transition LOW.
Measured ± 200 mV from steady state output voltage.
STK Control #ML0054
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Rev 1.0
March 31, 2006
U637256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
tcR (1)
Ai
Address Valid
ta(A) (2)
DQi
Output Data Valid
Previous Data Valid
Output
tv(A) (9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR (1)
Ai
Address Valid
ta(A) (2)
ta(E) (3)
E
tdis(E) (5)
tPD (11)
ten(E) (7)
G
ta(G) (4)
tdis(G) (6)
ten(G) (8)
DQi
High Impedance
Output
ACTIVE
ICC
No.
Output Data Valid
tPU (10)
STANDBY
Switching Characteristics
Write Cycle
Symbol
Min.
Alt. #1 Alt. #2
12 Write Cycle Time
tAVAV
13 Write Pulse Width
tWLWH
tAVAV
14 Write Pulse Width Setup Time
Max.
Unit
IEC
tcW
70
ns
tw(W)
55
ns
tWLEH
tsu(W)
55
ns
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0
ns
16 Address Valid to End of Write
tAVWH
tAVEH
tsu(A-WH)
55
ns
17 Chip Enable Setup Time
tELWH
tsu(E)
55
ns
tELEH
tw(E)
55
ns
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
tDVWH
tDVEH
tsu(D)
30
ns
20 Data Hold Time after End of Write
tWHDX
tEHDX
th(D)
0
ns
21 Address Hold after End of Write
tWHAX
tEHAX
th(A)
0
ns
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W)
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
March 31, 2006
STK Control #ML0054
5
25
5
Rev 1.0
ns
ns
U637256
Write Cycle #1: W-controlledj
tcW (12)
Ai
Address Valid
th(A) (21)
tsu(E) (17)
E
W
tsu(A-WH) (16)
tw(W) (13)
tsu(A)
(15)
Input
DQi
th(D) (20)
tsu(D) (19)
DQi
Previous Data
tdis(W) (22)
Input Data Valid
ten(W) (23)
High Impedance
Output
Write Cycle #2: E-controlledj
tcW (12)
Ai
E
Address Valid
tsu(A) (15)
th(A) (21)
tw(E) (18)
tsu(W) (14)
W
tsu(D) (19)
DQi
Input
th(D) (20)
Input Data Valid
DQi
High Impedance
Output
undefined
i:
j:
L- to H-level
H- to L-level
If W is low and when E goes low, the outputs remain in the high impedance state.
E or W must be VIH during address transition.
STK Control #ML0054
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Rev 1.0
March 31, 2006
U637256
Nonvolatile Memory Operations
Mode Selection
E
W
A13 - A0
(hex)
Mode
I/O
Power
Note
s
H
X
X
Not Selected
Output High Z
Standby
L
H
X
Read SRAM
Output Data
Active
L
L
X
Write SRAM
Input Data
Active
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
m
k:
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the U637256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
No.
Symbol
PowerStore
Power Up RECALL
Conditions
Alt.
Min.
Max.
Unit
IEC
24 Power Up RECALL Durationn
tRESTORE
650
μs
25 STORE Cycle Durationf, e
tPDSTORE
10
ms
26
Time allowed to Complete SRAM
Cyclef
Low Voltage Trigger Level
n:
tDELAY
1
VSWITCH
4.0
tRESTORE starts from the time VCC rises above VSWITCH.
March 31, 2006
STK Control #ML0054
7
Rev 1.0
μs
4.5
V
U637256
PowerStore and automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
PowerStore
(25)
tPDSTORE
Power Up
RECALL
(24)
(24)
tRESTORE
tRESTORE
W
tDELAY
DQi
POWER UP
RECALL
No.
Symbol
Min.
Max.
Unit
Alt.
IEC
27 STORE/RECALL Initiation Time
tAVAV
tcR
28 Chip Enable to Output Inactivep
tELQZ
tdis(E)SR
600
ns
29 STORE Cycle Timeq
tELQXS
td(E)S
10
ms
30 RECALL Cycle Timer
tELQXR
td(E)R
20
μs
31 Address Setup to Chip Enables
tAVELN
tsu(A)SR
0
ns
32 Chip Enable Pulse Widths, t
tELEHN
tw(E)SR
60
ns
33 Chip Disable to Address Changes
tEHAXN
th(A)SR
0
ns
o:
p:
q:
r:
s:
t:
Software Controlled STORE/RECALL
Cyclek, o
BROWN OUT
BROWN OUT
NO STORE
PowerStore
(NO SRAM WRITES)
70
ns
The software sequence is clocked with E controlled READs.
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note that STORE cycles (but not RECALL) are inhibited by VCC < VSWITCH (STORE inhibit).
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
STK Control #ML0054
8
Rev 1.0
March 31, 2006
U637256
Software Controlled STORE/RECALL Cyclet, u, v (E = HIGH after STORE initiation)
tcR (27)
tcR (27)
Ai
ADDRESS 1
ADDRESS 6
E
tw(E)SR
(32)
tsu(A)SR (31)
DQi
Output
High Impedance
(33)
th(A)SR
td(E)S (29)
td(E)R (30)
VALID
tdis(E)SR (28)
VALID
Software Controlled STORE/RECALL Cyclet, u, v (E = LOW after STORE initiation)
tcR (29)
Ai
E
DQi
Output
ADDRESS 1
tw(E)SR (34)
tsu(A)SR (33)
ADDRESS 6
th(A)SR (35)
(35)
(33)
th(A)SR
High Impedance
tsu(A)SR
VALID
td(E)R (32)
td(E)S (31)
VALID
tdis(E)SR (30)
u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U637256 performs a STORE
or RECALL.
v: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
March 31, 2006
STK Control #ML0054
9
Rev 1.0
U637256
Test Configuration for Functional Check
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E
W
G
Simultaneous measurement
of all 8 output pins
VIL
relevant test measurement
VIH
Input level according to the
5V
VCCx
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
480
VO
30 pF w
255
VSS
w: In measurement of tdis-times and ten-times the capacitance is 5 pF.
x:
Between VCC and V SS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Input Capacitance
Output Capacitance
Conditions
VCC
VI
f
Ta
Symbol
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Min.
Max.
Unit
CI
8
pF
CO
7
pF
All Pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U637256
D
K
70 G1
Type
Leadfree Option
G1 = Leadfree Green Package
Package
D = PDIP28 (600mil)
Access Time
70 = 70 ns
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Device Marking (example)
Product specification
ZMD
U637256DK
70 Z 0425
G1
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
Internal Code
STK Control #ML0054
10
Rev 1.0
March 31, 2006
U637256
Device Operation
The U637256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
SRAM READ
The U637256 performs a READ cycle whenever E and
G are LOW and W is HIGH. The address specified on
pins A0 - A14 determines which of the 32768 data
bytes will be accessed. When the READ is initiated by
an address transition, the outputs will be valid after a
delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later.
The data outputs will repeatedly respond to address
changes within the tcR access time without the need for
transition on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
SRAM READ and WRITE operations that are in progress after an automatic STORE cycle on power down
is requested are given time to complete before the
STORE operation is initiated.
During tDELAY multiple SRAM READ operations may
take place. If a WRITE is in progress it will be allowed a
time, tDELAY, to complete. Any SRAM WRITE cycles
requested after the VCC pin drops below VSWITCH will be
inhibited.
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the U637256 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U637256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U637256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by a
parallel programming of all the nonvolatile elements.
Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
Automatic STORE
During normal operation, the U637256 will draw current
from VCC to charge up an integrated capacitor. This
stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin
drops below VSWITCH, the part will automatically disconnect the internal components from the external power
supply with a typical delay of 150 ns and initiate a
STORE operation with tPDSTORE max. 10 ms.
March 31, 2006
STK Control #ML0054
11
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0FC0
Rev 1.0
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE
Cycle
U637256
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation. When VCC < VSWITCH all software STORE
operations will be inhibited.
Any SRAM WRITE cycles requested after the VCC pin
drops below VSWITCH will be inhibited.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ operations must be performed:
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0C63
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
td(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
Low Average Active Power
When E is HIGH the chip consumes only standby current.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL
Cycle
STK Control #ML0054
12
Rev 1.0
March 31, 2006
U637256
LIFE SUPPORT POLICY
SIMTEK products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SIMTEK product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by SIMTEK for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However SIMTEK Corporation (SIMTEK) makes no guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics.
SIMTEK does not guarantee that the use of any information contained herein will not infringe upon the patent,
trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby.
This document does not in any way extent SIMTEK’s warranty on any product beyond that set forth in its standard
terms and conditions of sale.
SIMTEK reserves terms of delivery and reserves the right to make changes in the products or specifications, or
both, presented in this publication at any time and without notice.
March 31, 2006
Simtek Corporation
4250 Buckingham Drive suite 100 • Colorado Springs, CO 80907 • USA
Phone: +(800)637-1667 • Fax: +(719)531-9481 • Email: [email protected] • http://www.simtek.com
Change record
Date/Rev
Name
Change
01.11.2001
Ivonne Steffens
format revision and release for „Memory CD 2002“
19.09.2002
Matthias Schniebel
removing „Preliminary“
21.04.2004
Matthias Schniebel
adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005
Stefan Günther
Page1: add RoHS compliance and Pb- free, 106 endurance cycles and
100a data retention
Simtek
Assigned Simtek Document Control Number
1.0