DATA SHEET PRELIMINARY DATA PRODUCT SHEET INFORMATION MOS INTEGRATED CIRCUIT µPD30550 VR5500TM 64-/32-BIT MICROPROCESSOR DESCRIPTION The µPD30550 (VR5500) is a member of the VR SeriesTM of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPSTM. The VR5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using protocols compatible with the VR5000 SeriesTM and VR5432TM. Detailed function descriptions are provided in the • VR5500 User’s Manual (U16044E) user’s manual. Be sure to read the manual before designing. FEATURES • MIPS 64-bit RISC architecture • High-speed operation processing • Two-way superscaler super pipeline • 300 MHz product: 603 MIPS 400 MHz product: 804 MIPS • High-speed translation lookaside buffer (TLB) 36 bits (64-bit bus selected) 32 bits (32-bit bus selected) • Virtual: • Bus width selectable during reset • Bus protocol compatibility with existing products retained • Maximum operating frequency • 300 MHz product: Internal 300 MHz, external 133 MHz (48 entries) • Address space • Physical: • 64-/32-bit address/data multiplexed bus 40 bits (in 64-bit mode) 31 bits (in 32-bit mode) • On-chip floating-point unit (FPU) • Supports sum-of-products instructions • On-chip primary cache memory (instruction/data: 32 KB each) • 2-way set associative • Supports line lock feature 400 MHz product: Internal 400 MHz, external 133 MHz • External/internal multiplication factor selectable from ×2 to ×5.5 by increments of .5 • Conforms to MIPS I, II, III, IV and MIPS64 instruction sets. Instruction set extensions supported include product-sum operation instruction, rotate instruction, register scan instruction, and instruction for low power mode. • Hardware debug functions supported are N-Wire and JTAG. • Supply voltage Core block: 1.5 V ±5% (300 MHz product) I/O block: 3.3 V ±5%, 2.5 V ±5% 1.6 to 1.7 V (400 MHz product) The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15700EJ1V0DS01 (2nd edition) Date Published September 2002 N CP(K) Printed in USA © 2002 2001 µPD30550 APPLICATIONS • Set-topboxes • RAID • High-end embedded devices, etc. ORDERING INFORMATION Part Number µPD30550F2-300-NN1 µPD30550F2-400-NN1 Package Maximum Operating Frequency (MHz) 272-pin plastic BGA (C/D advanced type) (29 × 29) 300 272-pin plastic BGA (C/D advanced type) (29 × 29) 400 PIN CONFIGURATION • 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550F2-300-NN1 µPD30550F2-400-NN1 Bottom view Top view 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A 2 A B C D E F G H J K L M N P R T U V W Y AA Data Sheet U15700EJ1V0DS µPD30550 (1/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name A1 VSS B17 SysAD27 D12 VSS H4 VDD A2 VSS B18 VDDIO D13 SysAD31 H18 VSS A3 VDDIO B19 VDDIO D14 VDD H19 VSS A4 VDDIO B20 VSS D15 SysAD60 H20 VSS A5 Reset# B21 VSS D16 VSS H21 SysAD21 A6 PReq# C1 VDDIO D17 SysAD26 J1 SysCmd7 A7 ValidIn# C2 VDDIO D18 VSS J2 SysCmd8 A8 ValidOut# C3 VSS D19 VSS J3 TIntSel A9 VSS C4 VSS D20 VDDIO J4 Int0# A10 SysADC7 C5 VSS D21 VDDIO J18 SysAD52 A11 SysADC3 C6 VDD E1 SysCmd0 J19 SysAD20 A12 SysADC1 C7 WrRdy# E2 DisDValidO# J20 SysAD51 A13 SysADC4 C8 VSS E3 DWBTrans# J21 SysAD19 A14 SysAD62 C9 SysID1 E4 O3Return# K1 Int1# A15 SysAD30 C10 VDD E18 SysAD57 K2 VSS A16 SysAD28 C11 SysADC2 E19 SysAD25 K3 VSS A17 SysAD59 C12 VSS E20 SysAD56 K4 VSS A18 VDDIO C13 SysAD63 E21 SysAD24 K18 VDD A19 VDDIO C14 VDD F1 SysCmd1 K19 VDD A20 VSS C15 SysAD29 F2 VSS K20 VDD A21 VSS C16 VSS F3 VSS K21 VDD B1 VSS C17 SysAD58 F4 VSS L1 Int2# B2 VSS C18 VDDIO F18 VDD L2 Int3# B3 VDDIO C19 VSS F19 VDD L3 Int4# B4 VDDIO C20 VDDIO F20 VDD L4 Int5# B5 ColdReset# C21 VDDIO F21 SysAD55 L18 SysAD17 B6 Release# D1 VDDIO G1 SysCmd2 L19 SysAD49 B7 ExtRqst# D2 VDDIO G2 SysCmd3 L20 SysAD18 B8 BusMode D3 VSS G3 SysCmd4 L21 SysAD50 B9 SysID2 D4 VSS G4 SysCmd5 M1 RMode#/BKTGIO# B10 VDD D5 IC G18 SysAD23 M2 VDD B11 SysADC6 D6 VDD G19 SysAD54 M3 VDD B12 VSS D7 RdRdy# G20 SysAD22 M4 VDD B13 SysADC0 D8 VSS G21 SysAD53 M18 VSS B14 VDD D9 SysID0 H1 SysCmd6 M19 VSS B15 SysAD61 D10 VDD H2 VDD M20 VSS B16 VSS D11 SysADC5 H3 VDD M21 VSS Caution Leave the IC pin open. Remark # indicates active low. Data Sheet U15700EJ1V0DS 3 µPD30550 (2/2) No. Pin Name No. Pin Name No. Pin Name Pin Name N1 VDDIO T21 SysAD12 W2 VDDIO Y12 VDD N2 NMI# U1 NTrcClk W3 VSS Y13 SysAD3 N3 VDDIO U2 NTrcData0 W4 VSS Y14 VSS N4 BigEndian U3 NTrcData1 W5 VDDPA2 Y15 SysAD37 N18 SysAD15 U4 NTrcData3 W6 VSS Y16 SysAD39 N19 SysAD47 U18 SysAD10 W7 VDDIO Y17 SysAD40 N20 SysAD16 U19 SysAD42 W8 VDD Y18 VDDIO N21 SysAD48 U20 SysAD11 W9 JTDI Y19 VDDIO P1 VSS U21 SysAD43 W10 VSS Y20 VSS P2 VSS V1 NTrcData2 W11 SysAD1 Y21 VSS P3 VSS V2 NTrcEnd W12 VDD AA1 VSS P4 VSS V3 VSS W13 SysAD35 AA2 VSS P18 VDD V4 VSS W14 VSS AA3 VDDIO P19 VDD V5 VSSPA2 W15 SysAD38 AA4 VDDIO P20 VDD V6 VSS W16 VDD AA5 VDDPA1 P21 SysAD46 V7 VDDIO W17 SysAD9 AA6 VDDIO R1 DivMode0 V8 VDD W18 VSS AA7 IC R2 DivMode1 V9 JTMS W19 VSS AA8 JTDO R3 DivMode2 V10 VSS W20 VDDIO AA9 DrvCon R4 VDDIO V11 SysAD33 W21 VDDIO AA10 VSS R18 SysAD44 V12 VDD Y1 VSS AA11 SysAD0 R19 SysAD13 V13 SysAD4 Y2 VSS AA12 SysAD2 R20 SysAD45 V14 VSS Y3 VDDIO AA13 SysAD34 R21 SysAD14 V15 SysAD7 Y4 VDDIO AA14 SysAD36 T1 VDD V16 VDD Y5 VSSPA1 AA15 SysAD5 T2 VDD V17 SysAD41 Y6 SysClock AA16 SysAD6 T3 VDD V18 VSS Y7 JTRST# AA17 SysAD8 T4 VDD V19 VSS Y8 VDD AA18 VDDIO T18 VSS V20 VDDIO Y9 JTCK AA19 VDDIO T19 VSS V21 VDDIO Y10 VSS AA20 VSS T20 VSS W1 VDDIO Y11 SysAD32 AA21 VSS Caution Leave the IC pin open. Remarks 1. # indicates active low. 4 No. Data Sheet U15700EJ1V0DS µPD30550 PIN NAMES BigEndian: Big endian PReq#: Processor request BKTGIO#: Break/trigger input/output RdRdy#: Read ready BusMode: Bus mode Release#: Release ColdReset#: Cold reset Reset#: Reset DisDValidO#: Disable delay ValidOut# SysAD(63:0): System address/data bus DivMode(2:0): Divide mode SysADC(7:0): System address/data check bus DrvCon: Driver control DWBTrans#: Doubleword block transfer SysClock: System clock ExtRqst#: External request SysCmd(8:0): System command/data IC Internally connected Int(5:0)#: Interrupt SysID(2:0): System bus identifier JTCK: JTAG clock TIntSel: Timer interrupt selection JTDI: JTAG data input ValidIn#: Valid input JTDO: JTAG data output ValidOut#: Valid output JTMS: JTAG mode select VDD: Power supply for CPU core JTRST#: JTAG reset VDDIO: Power supply for I/O NMI#: Non-maskable interrupt VDDPA1, VDDPA2: Noise Sensitive VDD for PLL NTrcClk: N-Trace clock VSS: Ground NTrcData(3:0) : N-Trace data output VSSPA1, VSSPA2: Noise Sensitive VSS for PLL NTrcEnd: N-Trace end WrRdy#: Write ready O3Return#: Out-of-Order Return mode Remark identifier bus # indicates active low. Data Sheet U15700EJ1V0DS 5 µPD30550 INTERNAL BLOCK DIAGRAM VR5500 IFU BHT Instruction cache RAS IMQ Control signal SysAD bus (64/32 bits) SIU WTB RCU RF ICU RNRF RS EXU CP0 Test interface SysClock ALU0 ALU1 BRU FPU/ MACU FPU LSU TLB Clock generator DCU Data cache SB RB 6 Data Sheet U15700EJ1V0DS µPD30550 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................8 1.1 List of Pin Functions ...................................................................................................................................... 8 1.2 Recommended Connection of Unused Pins .............................................................................................. 12 2. ELECTRICAL SPECIFICATIONS ..........................................................................................................14 3. PACKAGE DRAWING............................................................................................................................24 4. RECOMMENDED SOLDERING CONDITIONS .....................................................................................25 Data Sheet U15700EJ1V0DS 7 µPD30550 1. PIN FUNCTIONS Remark # indicates active low. 1.1 List of Pin Functions (1) System interface signals Pin Name SysAD(63:0) I/O I/O Function System address/data bus A 64-bit bus for communication between the processor and external agent. The lower 32 bits (SysAD(31:0)) are used in 32-bit bus mode. SysADC(7:0) I/O System address/data check bus A bus for SysAD bus parity. Valid only during a data cycle. The lower 32 bits (SysADC(3:0)) are used in 32-bit bus mode. SysCmd(8:0) I/O System command/data ID bus A 9-bit bus that transfers command and data identifiers between the processor and external agent SysID(2:0) I/O System bus protocol ID These signals transfer request identifiers in the out-of-order return mode. The processor drives a valid identifier in synchronization with the activation of the ValidOut# signal. The external agent must drive valid identifiers in synchronization with the activation of the ValidIn# signal. ValidIn# Input Valid In This signal indicates the external agent is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. ValidOut# Output Valid out This signal indicates the processor is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. RdRdy# Input Read ready This signal indicates the external agent is ready to accept a processor read request WrRdy# Input Write ready This signal indicates the external agent is ready to accept a processor write request ExtRqst# Input External request This signal indicates the external agent is requesting the right to use the system interface Release# Output Releases interface This signal indicates the processor is releasing the system interface to external agent control PReq# Output Processor request This signal indicates the processor has a request that is pending 8 Data Sheet U15700EJ1V0DS µPD30550 (2) Initialization interface signals Pin Name (1/2) I/O DivMode(2:0) Function Division mode These signals set the division ratio of PClock and SysClock as follows: 111: 5.5 110: 5 101: 4.5 100: 4 011: 3.5 010: 3 001: 2.5 000: 2 Set the input levels of these signals before a power-on reset. Make sure that the levels of these signals do not change while the VR5500 is operating. BigEndian Input Endian mode This signal sets the byte ordering for addressing. 1: Big endian 0: Little endian Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. BusMode Input Bus mode This signal sets the bus width of the system interface. 1: 64 bits 0: 32 bits Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. TIntSel Input Interrupt source select This signal sets the interrupt source to be assigned to the IP7 bit of the Cause register. 1: Timer interrupt 0: Int5# input and external write request (SysAD5) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. DisDValidO# Input ValidOut# delay enable 1: ValidOut# is active even while the address cycle is stalled 0: ValidOut# is active during the address issuance cycle only Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. DWBTrans# Input Doubleword block transfer enable (valid in 32-bit bus mode only) 1: Disabled 0: Enabled Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. Remark 1: High level, 0: Low level Data Sheet U15700EJ1V0DS 9 µPD30550 (2/2) Pin Name O3Return# I/O Input Function Out-of-Order Return mode This signal sets the protocol of the system interface. 1: Normal mode 0: Out-of-order return mode Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. ColdReset# Input Cold reset This signal completely initializes the internal status of the processor. Deassert it in synchronization with SysClock. Reset# Input Reset This signal logically initializes the internal status of the processor. Deassert it in synchronization with SysClock. DrvCon Input Drive control This signal sets the impedance of the external output driver. 1: Low 0: Normal (recommended) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change during VR5500 operation. Remark Applies to revision 2.0 or later products. Fixed to 0 in revision 1.x products. Remark 1: High level, 0: Low level The O3Return#, DWBTrans#, DisDValidO#, and BusMode signals are used for determining the protocol of the system interface. The protocol is selected as follows in accordance with the setting of these signals. Protocol O3Return# DWBTrans# DisDValidO# BusMode 1 1 1 1 RM523x compatible 1 1 1 0 VR5432 native mode compatible 1 0 0 0 Out-of-order return mode 0 Arbitrary Arbitrary Arbitrary VR5000 TM compatible Remark 1: High level, 0:Low level RM523x is a product of PMC-Sierra, Inc. (3) Interrupt interface signals Pin Name Int(5:0)# I/O Input Function Interrupt These are general-purpose processor interrupt requests. The input states can be checked by the Cause register. Whether Int5# is acknowledged or not depends on the status of the TIntSel signal during reset. NMI# Input Non-maskable interrupt This is the non-maskable interrupt request. 10 Data Sheet U15700EJ1V0DS µPD30550 (4) Clock interface signals Pin Name SysClock I/O Input Function System clock Clock input to the processor − VDDPA1 VDDPA2 VDD for PLL Power supply for the internal PLL − VSSPA1 VSSPA2 VSS for PLL Ground for the internal PLL (5) Power supply Pin Name I/O Function VDD − Power supply pin for core VDDIO − Power supply pin for I/O VSS − Ground potential pin Caution The VR5500 uses two separate power supply pins. The power supply pins can be applied in any sequence. Power application to the pins must occur within 100ms of each other. (6) Test interface signals Pin Name I/O Function NTrcData(3:0) Output Trace data NTrcEnd Output Trace end NTrcClk Output Trace clock RMode#/ I/O Reset mode/break trigger I/O Trace data output This signal indicates the end of a trace data packet. Clock for the test interface. The same clock as SysClock is output. BKTGIO# When the JTRST# signal is active, this is a debug reset mode input signal . During normal operation this serves as a break or trigger I/O signal. JTDI Input JTAG data input JTDO Output JTAG data output Serial data input for JTAG Serial data output for JTAG. Output is performed in synchronization with the rise of JTCK. JTMS Input JTAG mode select This signal selects the JTAG test mode. JTCK Input JTAG clock input Serial clock input for JTAG. The maximum frequency is 33 MHz. There is no need for it to be synchronized with SysClock. JTRST# Input JTAG reset input A signal for initializing the JTAG test module. Data Sheet U15700EJ1V0DS 11 µPD30550 1.2 Recommended Connection of Unused Pins (1) System interface pins (a) 32-bit bus mode The VR5500 allows selection of a SysAD bus width from 64 bits or 32 bits. When the 32-bit bus mode is selected, the VR5500 operates using only the required system interface pins. Therefore, set the unused pins as follows when operating the VR5500 in the 32-bit bus mode. Pin Name Recommended Connection of Unused Pins SysAD(63:32) Leave open SysADC(7:4) Leave open (b) Normal mode The VR5500 can process read/write transactions regardless of the order in which requests are issued in the out-of-order return mode. The SysID(2:0) signals are used to identify each request during this processing. Set these signals, which are not used in the normal mode, as follows. Pin Name Recommended Connection of Unused Pins SysID(2:0) Leave open (c) Parity bus The VR5500 allows selection of whether the data is protected using parity. When parity is used, the parity data is output from the processor or external agent to the SysADC bus. However, whether the parity is used or not is selected by software, so unless the program is started, the VR5500 cannot determine the operation of the SysADC bus. Therefore, care must be taken to prevent the SysADC bus from being left open or in a high-impedance state. Each pin of the SysADC bus should be connected to VDDIO via a high resistance value resistor when parity is not used. 12 Data Sheet U15700EJ1V0DS µPD30550 (2) Test interface pins The VR5500 can be used to perform testing and debugging via N-Wire and JTAG with the device mounted on the board. The test interface pins are used for connection with the external debug tool during this debugging. When this test interface is not going to be used and when it is in normal operation mode, set the test interface pins as follows. Pin Name Recommended Connection of Unused Pins JTCK Pull up JTDI Pull up JTMS Pull up JTRST# Pull up JTDO Leave open NTrcClk Leave open NTrcData(3:0) Leave open NTrcEnd Leave open RMode#/BKTGIO# Pull up Data Sheet U15700EJ1V0DS 13 µPD30550 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Input voltage Note Symbol Conditions Ratings Unit VDDIO −0.5 to +4.0 V VDD −0.5 to +2.0 V VDDP −0.5 to +2.0 V −0.5 to VDDIO + 0.3 V −1.5 to VDDIO + 0.3 V VI Pulse of less than 7 ns Operating case temperature TC −10 to +85 °C Storage temperature Tstg −40 to +125 °C Note The upper limit of the input voltage (VCCIO + 0.3) is +4.0 V. Cautions 1. Do not short-circuit two or more outputs at the same time. 2. The maximum ratings shown in the table above indicate the point at which the product is on the verge of being physically damaged. Exceeding the maximum ratings even momentarily on any parameter may cause such damage. Therefore do not use the product under conditions which will violate these ratings. The specifications and conditions shown in the following DC Characteristics and AC Characteristics sections are the ranges within which the product can normally operate and the quality can be guaranteed. Operating conditions (1) 300 MHz product Parameter Supply voltage MIN. MAX. Unit 2.375 2.625 V 3.135 3.465 V VDD 1.425 1.575 V VDDP 1.425 1.575 V Symbol Conditions VDDIO Caution VDD can also be used with the voltage range of the 400 MHz product (1.6 to 1.7 V). Internal operation at 300 MHz is still guaranteed. The core block supply current in this case (MAX. 1.8 A) is the same value as the 400 MHz product. (2) 400 MHz product Parameter Supply voltage Caution MIN. MAX. Unit 2.375 2.625 V 3.135 3.465 V VDD 1.6 1.7 V VDDP 1.6 1.7 V Symbol Conditions VDDIO VDD can also be used with the voltage range of the 300 MHz product (1.425 to 1.575 V). In this case, internal operation at 300 MHz is guaranteed only. The core block supply current in this case (MAX. 1.4 A) is the same value as the 300 MHz product. 14 Data Sheet U15700EJ1V0DS µPD30550 Supply Current Parameter Supply current of core block Symbol IDD MIN. Conditions MAX. Unit 1.4 A 1.8 A 0.35 A 0.45 A 300 MHz product, during normal operation, VDD = VDDP = 1.575 V 400 MHz product, during normal operation, VDD = VDDP = 1.7 V IDD_sb 300 MHz product, in standby mode, VDD = VDDP = 1.575 V 400 MHz product, in standby mode, VDD = VDDP = 1.7 V Remark The supply current in the I/O block varies depending on the application used. It is normally 20% IDD or lower. DC Characteristics (1) When VDDIO = 2.5 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Symbol Conditions Output voltage, high VOH VDDIO = MIN., IOH = 4 mA Output voltage, low VOL VDDIO = MIN., IOL = 4 mA Input voltage, high Note 1 Note 1 Input voltage, low Input voltage, high Note 2 Input voltage, low MAX. 0.8 × VDDIO Unit V 0.4 V VIH 2.0 VDDIO + 0.3 V VIL −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V VIHC 0.8 × VDDIO VDDIO + 0.3 V VILC −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V Pulse of less than 7 ns Note 2 MIN. Pulse of less than 7 ns Input current leakage, high ILIH VI = VDDIO 5.0 µA Input current leakage, low ILIL VI = 0 V −5.0 µA Output current leakage, high ILOH VO = VDDIO 5.0 µA Output current leakage, low ILOL VO = 0 V −5.0 µA Notes 1. Does not apply to the SysClock pin. 2. Only applies to the SysClock pin. Data Sheet U15700EJ1V0DS 15 µPD30550 (2) When VDDIO = 3.3 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Symbol Conditions Output voltage, high VOH VDDIO = MIN., IOH = 4 mA Output voltage, low VOL VDDIO = MIN., IOL = 4 mA Input voltage, high Note 1 Note 1 Input voltage, low Input voltage, high Note 2 Input voltage, low MAX. 2.4 Unit V 0.4 V VIH 2.0 VDDIO + 0.3 V VIL −0.5 0.8 V −1.5 0.8 V VIHC 0.8 × VDDIO VDDIO + 0.3 V VILC −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V Pulse of less than 7 ns Note 2 MIN. Pulse of less than 7 ns Input current leakage, high ILIH VI = VDDIO 5.0 µA Input current leakage, low ILIL VI = 0 V −5.0 µA Output current leakage, high ILOH VO = VDDIO 5.0 µA Output current leakage, low ILOL VO = 0 V −5.0 µA Notes 16 1. Does not apply to the SysClock pin. 2. Only applies to the SysClock pin. Data Sheet U15700EJ1V0DS µPD30550 Power-on Sequence The VR5500 uses two power supply pins. These power supply pins can be applied in any sequence. However, power may not be applied to one pin more than 100 ms before it is applied to the other. Parameter Power-on delay Symbol Conditions tDF MIN. MAX. Unit 0 100 ms MIN. MAX. Unit Capacitance (TA = 25°C, VDDIO = VDD = VDDP = 0 V) Parameter Symbol Conditions Input capacitance CIN fC = 1 MHz 5.0 pF Output capacitance COUT Unmeasured pins returned to 0 V 7.0 pF MAX. Unit AC Characteristics (300 MHz products: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Clock parameters (1/2) Parameter Symbol Conditions MIN. System clock high-level width tCH 1.8 ns System clock low-level width tCL 1.8 ns Pipeline clock frequency Note System clock frequency 300 MHz product 200 300 MHz 400 MHz product 200 400 MHz 300 MHz DivMode = 2:1 100 133 MHz product DivMode = 2.5:1 80 120 MHz DivMode = 3:1 66.7 100 MHz DivMode = 3.5:1 57.2 85.7 MHz 50 75 MHz 44.5 66.6 MHz 40 60 MHz DivMode = 5.5:1 36.4 54.5 MHz 400 MHz DivMode = 2:1 100 133 MHz product DivMode = 2.5:1 80 133 MHz DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 3:1 66.7 133 MHz DivMode = 3.5:1 57.2 114 MHz 50 100 MHz 44.5 88.8 MHz 40 80 MHz 36.4 72.7 MHz DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 Note This is the frequency at which the operation of the internal PLL is guaranteed. Data Sheet U15700EJ1V0DS 17 µPD30550 Clock parameters (2/2) Parameter System clock cycle Symbol tCP Conditions MIN. MAX. Unit 300 MHz DivMode = 2:1 7.5 10 ns product DivMode = 2.5:1 8.3 12.5 ns DivMode = 3:1 10 15 ns DivMode = 3.5:1 11.7 17.5 ns DivMode = 4:1 13.3 20 ns 15 22.5 ns DivMode = 5:1 16.7 25 ns DivMode = 5.5:1 18.3 27.5 ns 400 MHz DivMode = 2:1 7.5 10 ns product DivMode = 2.5:1 7.5 12.5 ns DivMode = 3:1 7.5 15 ns DivMode = 3.5:1 8.8 17.5 ns DivMode = 4.5:1 DivMode = 4:1 10 20 ns DivMode = 4.5:1 11.3 22.5 ns DivMode = 5:1 12.5 25 ns DivMode = 5.5:1 13.8 27.5 ns 5 % System clock jitter tJ System clock rise time tCR 1.2 ns System clock fall time tCF 1.2 ns JTAG clock frequency 33 MHz MAX. Unit Remarks 1. The system clock jitter is a cycle-to-cycle jitter. 2. The JTAG clock runs asynchronously to the system clock. System interface parameters Parameter Data output hold time Note 1 Data output delay time Data input setup time Data input hold time Note 1 Note 2 Note 2 Symbol Conditions tDM MIN. 1.0 tDO 5.0 tDS tDH ns ns 1.5 ns 300 MHz product 1.0 ns 400 MHz product 0.5 ns Notes 1. Applies to the Release#, ValidOut#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. 2. Applies to the ColdReset#, Reset#, Int(5:0), NMI#, ExtRqst#, RdRdy#, ValidIn#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. Load coefficient Parameter Load coefficient 18 Symbol Conditions CLD Data Sheet U15700EJ1V0DS MIN. MAX. Unit 1.0 ns/25 pF µPD30550 Measurement Conditions Measurement points SysClock 50% tDO tDM All output pins 50% Load conditions All output pins DUT CL = 50 pF Timing Charts Clock timing tCP tCH 80% SysClock 50% 20% tCL tCR Data Sheet U15700EJ1V0DS tCF 19 µPD30550 Clock jitter tJ tJ SysClock 50% System interface edge timing SysClock tDO tDH tDM SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) tDS Output Output tDO tDM ValidOut#, Release#, PReq# Output Output tDS tDH ValidIn#, ExtRqst#, RdRdy#, WrRdy#, Int(5:0)#, NMI# ColdReset#, Reset# 20 Input Data Sheet U15700EJ1V0DS Input µPD30550 Clock relationships (DivMode = 2:1) Cycle 1 2 3 4 SysClock (input) PClock (internal) tDO tDM Note (output) Data Note (input) Data Data Data Data Data Data Data tDS tDH Note SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) Power-on sequence tDF VDD VDDIO tDF 50% 50% Data Sheet U15700EJ1V0DS 21 µPD30550 Reset Timing Power-on reset timing VDD Note 1 VDDIO Note 2 SysClock (input) ≥100 ms ≥64 K SysClock tDS ColdReset# (input) tDS ≥16 SysClock Reset# (input) Notes 1. 2. 1.425 V (300 MHz product), 1.6 V (400 MHz product) 2.375 V at 2.5V operation or 3.135 V at 3.3V operation Cold reset timing VDD H VDDIO H SysClock (input) ≥64 K SysClock tDS tDS ColdReset# (input) ≥16 SysClock tDS tDS Reset# (input) 22 Data Sheet U15700EJ1V0DS µPD30550 Warm reset timing VDD H VDDIO H SysClock (input) ≥16 SysClock ColdReset# (input) H tDS tDS Reset# (input) Data Sheet U15700EJ1V0DS 23 µPD30550 3. PACKAGE DRAWING 272-PIN PLASTIC BGA (CAVITY DOWN ADVANCED TYPE) (29x29) D B A ZE ZD 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E AA Y W V U T R P N M L K J H G F E D C B A INDEX AREA 4-C1.4 A A2 A1 detail of A part S A φb e y S φ x1 M S A B φ x2 M S A4 ITEM D E e A A1 A2 MILLIMETERS 29.00±0.20 29.00±0.20 1.27 1.75±0.30 0.60±0.10 1.15 A4 0.25MIN. b x1 x2 φ 0.75±0.15 0.30 0.15 y 0.20 ZD 1.80 ZE 1.80 P272F2-127-BA1 24 Data Sheet U15700EJ1V0DS µPD30550 4. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For details on the recommended soldering conditions, refer to the Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 4-1. Surface mounting Type Soldering Conditions µPD30550F2-300-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550F2-400-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) Soldering Conditions Soldering Method Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-103-3 (at 210°C or higher), Count: Three times or less, Exposure limit: 3 days Note (after that, prebake at 125°C for 10 hours) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet U15700EJ1V0DS 25 µPD30550 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Note Reference document Electrical Characteristics for Microcomputer (U15170J) Note This document number is that of Japanese version. The related documents indicated in the publication may include preliminary versions. However, preliminary versions are not marked as such. 26 Data Sheet U15700EJ1V0DS µPD30550 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 • Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Hong Kong Ltd. • Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 NEC Electronics Hong Kong Ltd. • Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany • United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 • Sucursal en España Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 • Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 J02.4 Data Sheet U15700EJ1V0DS 27