ETC UPD30122F1-150-GA1

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30122
TM
VR4122
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30122 (VR4122) is one of NEC’s VR Series
TM
RISC (Reduced Instruction Set Computer) microprocessors
and is a high-performance 64-/32-bit microprocessor employing the MIPS
The VR4122 uses the high-performance, super power-saving VR4120
TM
TM
RISC architecture.
as the CPU core, and has many peripheral
functions such as a DMA controller, serial interface, IrDA interface, and real-time clock. Configured with these
functions, the VR4122 is suitable for high-speed battery-driven portable information systems. The external memory
bus width can be selected from 32 bits and 16 bits, realizing high-speed data transfer.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
• VR4122 User’s Manual (U14327E)
• VR4100 Series
TM
Architecture User’s Manual (U15509E)
FEATURES
• Employs 64-bit MIPS architecture
• Conforms to MIPS III instruction set (deleting FPU,
LL, LLD, SC, and SCD instructions)
• Optimized 5-stage pipeline
• Supports MIPS16 instruction set
• Supports high-speed product-sum operation
instructions
• High-capacity instruction/data separated cache
memories
Instruction: 32 KB
Data:
16 KB
• Memory controller (ROM, synchronous DRAM
(SDRAM), and flash memory supported)
• Supports PCI bus subset
• Supports four types of operating modes, enabling
more effective power-consumption management
• 4-channel DMA controller
• Serial interface (NS16550 compatible)
• Internal maximum operating frequency: 180/150 MHz
• On-chip clocked serial interface
• On-chip clock generator
• IrDA interface for infrared communication
• Address space physical: 32 bits
• Debug serial interface
virtual:
40 bits
Integrates 32 double-entry TLBs
• Power supply voltage:
VDD1 = 1.8 to 2.0 V (150 MHz model),
1.9 to 2.0 V (180 MHz model)
VDD3 = 3.0 to 3.6 V
• Package: 224-pin fine-pitch FBGA
APPLICATIONS
• Battery-driven portable information systems
• Embedded controllers, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15585EJ1V0DS00 (1st edition)
Date Published June 2002 N CP(K)
Printed in Japan
©
2002
µPD30122
ORDERING INFORMATION
Part Number
Package
Internal Maximum Operating Frequency
µPD30122F1-150-GA1
224-pin plastic FBGA (16 × 16)
150 MHz
µPD30122F1-180-GA1
224-pin plastic FBGA (16 × 16)
180 MHz
PIN CONFIGURATION
• 224-pin plastic FBGA (16 × 16)
µPD30122F1-150-GA1
µPD30122F1-180-GA1
Bottom view
Top view
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14
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11
10
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5
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V U T R P N M L K J H G F E D C B A
2
A B C D E F G H J K L M N P R T U V
Index mark
Data Sheet U15585EJ1V0DS
µPD30122
(1/2)
Pin No.
Power
Pin Name
Pin No.
Supply
Power
Pin Name
Pin No.
Supply
A1
3.3 V
CLKOUT
C14
A2
1.8 V
VDDPD
C15
A3
1.8 V
VDDP
C16
A4
3.3 V
CLKX1
C17
A5
3.3 V
CLKX2
C18
A6
3.3 V
PCLK
A7
3.3 V
A8
3.3 V
A9
3.3 V
Power
Pin Name
Supply
AD3
H3
3.3 V
ADD13
3.3 V
CBE2
H4
3.3 V
DATA5
3.3 V
DEVSEL#
H15
3.3 V
POWER
3.3 V
PAR
H16
3.3 V
GND3
3.3 V
FRAME#
H17
3.3 V
BKTGIO#
D1
3.3 V
ADD17
H18
3.3 V
FIRCLK/TRCCLK
AD28
D2
3.3 V
ADD21
J1
3.3 V
DATA8
AD23
D3
3.3 V
ADD22
J2
3.3 V
DATA7
3.3 V
AD19
D4
1.8 V
VDD1
J3
3.3 V
ADD11
A10
3.3 V
AD16
D5
3.3 V
GND3
J4
3.3 V
ADD12
A11
3.3 V
AD13
D6
3.3 V
CGND
J15
3.3 V
POWERON
A12
3.3 V
AD12
D7
3.3 V
AD29
J16
3.3 V
MPOWER
A13
3.3 V
AD10
D8
3.3 V
AD24
J17
1.8 V
GND1
A14
3.3 V
AD6
D9
3.3 V
AD20
J18
3.3 V
IRDOUT#/TRCDATA0
A15
3.3 V
AD2
D10
3.3 V
AD15
K1
3.3 V
DATA10
A16
3.3 V
RST#
D11
1.8 V
GND1
K2
3.3 V
DATA9
A17
3.3 V
CBE1
D12
3.3 V
AD8
K3
3.3 V
ADD10
A18
3.3 V
IRDY#
D13
3.3 V
AD4
K4
3.3 V
DATA11
B1
3.3 V
ADD23
D14
3.3 V
AD0
K15
3.3 V
GND3
B2
3.3 V
VDD3
D15
3.3 V
GND3
K16
1.8 V
VDD1
B3
1.8 V
GNDP
D16
3.3 V
GND3
K17
3.3 V
JTDI/RMODE#
B4
3.3 V
CVDD
D17
3.3 V
PERR#
K18
3.3 V
VDD3
B5
3.3 V
RTCX1
D18
3.3 V
STOP#
L1
3.3 V
DATA13
B6
3.3 V
AD30
E1
3.3 V
ADD15
L2
3.3 V
DATA12
B7
3.3 V
AD25
E2
3.3 V
ADD18
L3
3.3 V
GND3
B8
3.3 V
AD22
E3
3.3 V
ADD16
L4
3.3 V
ADD9
B9
3.3 V
AD17
E4
3.3 V
ADD19
L15
3.3 V
RTCRST#
B10
3.3 V
AD14
E15
3.3 V
GND3
L16
3.3 V
RSTSW#
B11
3.3 V
VDD3
E16
3.3 V
GND3
L17
3.3 V
JTCK
B12
3.3 V
AD9
E17
3.3 V
REQ1#
L18
3.3 V
IRDIN/TRCDATA1
B13
3.3 V
AD5
E18
3.3 V
CLKRUN
M1
3.3 V
DATA15
B14
3.3 V
AD1
F1
3.3 V
GND3
M2
3.3 V
DATA14
B15
3.3 V
CBE3
F2
3.3 V
DATA1
M3
3.3 V
DATA17/GPIO17
B16
3.3 V
CBE0
F3
3.3 V
DATA2
M4
3.3 V
ADD8
B17
3.3 V
VDD3
F4
3.3 V
DATA0
M15
3.3 V
DDIN/GPIO34
B18
3.3 V
TRDY#
F15
3.3 V
REQ0#
M16
3.3 V
LEDOUT#
C1
3.3 V
ADD20
F16
3.3 V
REQ2#
M17
3.3 V
JTMS
C2
3.3 V
ADD24
F17
3.3 V
GNT0#
M18
3.3 V
FIRDIN#/SEL/TRCDATA2
C3
1.8 V
GNDPD
F18
3.3 V
GNT2#
N1
3.3 V
ADD7
C4
3.3 V
AD27
G1
1.8 V
GND1
N2
3.3 V
DATA16/GPIO16
C5
3.3 V
GND3
G2
3.3 V
ADD14
N3
3.3 V
ADD6
C6
3.3 V
RTCX2
G3
3.3 V
VDD3
N4
3.3 V
DATA18/GPIO18
C7
3.3 V
AD31
G4
3.3 V
DATA3
N15
3.3 V
DRTS#/MIPS16EN/GPIO33
C8
3.3 V
AD26
G15
3.3 V
SERR#
N16
3.3 V
DDOUT/DBUS32/GPIO32
C9
3.3 V
AD21
G16
3.3 V
GNT1#
N17
3.3 V
JTDO
C10
3.3 V
AD18
G17
3.3 V
JTRST#
N18
3.3 V
TRCDATA3/HLDRQ#
C11
1.8 V
VDD1
G18
3.3 V
LOCK#
P1
3.3 V
DATA20/GPIO20
C12
3.3 V
AD11
H1
3.3 V
DATA6
P2
3.3 V
DATA19/GPIO19
C13
3.3 V
AD7
H2
3.3 V
DATA4
P3
3.3 V
GND3
Remark # indicates active low.
Data Sheet U15585EJ1V0DS
3
µPD30122
(2/2)
Pin No.
Power
Pin Name
Pin No.
Supply
Power
Pin Name
Pin No.
Supply
P4
3.3 V
GND3
P15
3.3 V
RTS#/CLKSEL1
P16
3.3 V
DCTS#/GPIO35
P17
3.3 V
TxD/CLKSEL2
T4
Power
Pin Name
Supply
3.3 V
DATA27/GPIO27
U12
1.8 V
GND1
T5
3.3 V
DATA31/GPIO31
U13
3.3 V
SIN
T6
3.3 V
CAS
U14
3.3 V
GPIO3
T7
3.3 V
SWR#
U15
3.3 V
GPIO7
GPIO8
P18
3.3 V
TRCEND/NWIREEN/HLDAK#
T8
3.3 V
CKE0
U16
3.3 V
R1
3.3 V
DATA21/GPIO21
T9
3.3 V
ROMCS0#
U17
3.3 V
VDD3
R2
3.3 V
ADD5
T10
3.3 V
IOCS0#
U18
3.3 V
DCD#/GPIO15
R3
3.3 V
VDD3
T11
1.8 V
VDD1
V1
3.3 V
DATA25/GPIO25
R4
3.3 V
DQM1
T12
3.3 V
GPIO0
V2
3.3 V
DATA26/GPIO26
R5
3.3 V
DATA29/GPIO29
T13
3.3 V
GPIO4
V3
3.3 V
DATA28/GPIO28
R6
3.3 V
WR#
T14
3.3 V
GND3
V4
3.3 V
DATA30/GPIO30
R7
3.3 V
RAS
T15
3.3 V
IORDY
V5
3.3 V
SCLK
R8
3.3 V
DQM3
T16
3.3 V
GPIO10
V6
3.3 V
VDD3
R9
3.3 V
CS1#
T17
3.3 V
GPIO13
V7
3.3 V
DQM0
CKE1
R10
3.3 V
SPOWER
T18
3.3 V
DTR#/CLKSEL0
V8
3.3 V
R11
3.3 V
VDD3
U1
3.3 V
DATA24/GPIO24
V9
3.3 V
CS2#/ROMCS2#
R12
3.3 V
SOUT
U2
3.3 V
VDD3
V10
3.3 V
ROMCS1#
R13
3.3 V
GPIO2
U3
3.3 V
ADD3
V11
3.3 V
GND3
R14
3.3 V
GND3
U4
3.3 V
ADD2
V12
3.3 V
SECLK
R15
3.3 V
BATTINH/BATTINT#
U5
3.3 V
ADD1
V13
3.3 V
GPIO1
R16
3.3 V
DSR#
U6
3.3 V
RD#
V14
3.3 V
GPIO5
R17
3.3 V
CTS#
U7
3.3 V
GND3
V15
3.3 V
GPIO6/SYSDIR
R18
3.3 V
RxD
U8
3.3 V
DQM2
V16
3.3 V
GPIO9
T1
3.3 V
DATA23/GPIO23
U9
3.3V
CS0#
V17
3.3 V
GPIO11
T2
3.3 V
DATA22/GPIO22
U10
3.3 V
CS3#/ROMCS3#
V18
3.3 V
GPIO12
T3
3.3 V
ADD4
U11
3.3 V
IOCS1#
Remark # indicates active low.
4
Data Sheet U15585EJ1V0DS
µPD30122
Pin Identification
AD(31:0):
Address/data bus
JTDI:
JTAG data input
ADD(24:1):
Address bus
JTDO:
JTAG data output
BATTINH:
Battery inhibit
JTMS:
JTAG mode select
BATTINT#:
Battery interrupt request
JTRST#:
JTAG reset
BKTGIO#:
Break trigger I/O
LEDOUT#:
LED output
CAS:
Column address strobe
LOCK#:
Lock
CBE(3:0):
Command/byte enable
MIPS16EN:
MIPS16 enable
CGND:
GND for oscillator
MPOWER:
Main power
CKE(1:0):
Clock enable
NWIREEN:
N-wire enable
CLKSEL(2:0):
Clock select
PAR:
Parity
CLKOUT:
Clock output
PCLK:
PCI clock
CLKRUN:
Clock run
PERR#:
Parity error
CLKX1:
Clock X1
POWER:
Power switch
CLKX2:
Clock X2
POWERON:
Power on state
CS(3:0)#:
Chip select
RAS:
Row address strobe
CTS#:
Clear to send
RD#:
Read
CVDD:
VDD for oscillator
REQ(2:0)#:
Request
DATA(31:0):
Data bus
RMODE#:
Reset mode
DBUS32:
Data bus 32
ROMCS(3:0)#:
ROM chip select
DCD#:
Data carrier detect
RST#:
Reset
DCTS#:
Debug serial clear to send
RSTSW#:
Reset switch
DDIN:
Debug serial data input
RTCRST#:
Real-time clock reset
DDOUT:
Debug serial data output
RTCX1:
Real-time clock X1
DEVSEL#:
Device select
RTCX2:
Real-time clock X2
DQM(3:0):
Data input/output
RTS#:
Request to send
DRTS#:
Debug serial request to send
RxD:
Receive data
DSR#:
Data set ready
SCLK:
SDRAM clock
DTR#:
Data terminal ready
SECLK:
Clocked serial clock
FIRCLK:
FIR clock
SEL:
IrDA module select
FIRDIN#:
FIR data input
SERR#:
System error
FRAME#:
Cycle frame
SIN:
Clocked serial input
GND1, GND3:
Ground
SOUT:
Clocked serial output
GNDP, GNDPD:
GND for PLL
SPOWER:
SDRAM power control
GNT(2:0)#:
Grant
STOP#:
Target assert stop
GPIO(13:0):
General purpose I/O
SWR#:
SDRAM write
GPIO(35:15):
General purpose I/O
SYSDIR:
System bus buffer direction
HLDAK#:
Hold acknowledge
TRCCLK:
Trace control clock
HLDRQ#:
Hold request
TRCDATA(3:0):
Trace data
IOCS(1:0)#:
I/O chip select
TRCEND:
Trace end
IORDY:
I/O ready
TRDY#:
Target ready
IRDIN:
IrDA data input
TxD:
Transmit data
IRDOUT#:
IrDA data output
VDD1, VDD3:
Power supply voltage
IRDY#:
Initiator ready
VDDP, VDDPD:
VDD for PLL
JTCK:
JTAG clock
WR#:
Write
Remark # indicates active low.
Data Sheet U15585EJ1V0DS
5
µPD30122
INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS
32.768 kHz 18.432 MHz
VRC4173TM
OSB
PLL
OSB
RTC
ICU
Touch panel
LCD panel
GIU
LED
VR4120 CPU core
PC card
PMU
CSI
LCDC
PCIU
SDRAM
SCU
CMU
DCU
DSIU
DMAAU
SIU
SDRAMU
ROM/
Flash memory
BCU
FIR
RS-232-C
driver
IR
driver
VR4122
48 MHz
CPU CORE INTERNAL BLOCK DIAGRAM
Virtual address bus
Internal data
bus
Control (o)
Control (i)
Bus
interface
Data
cache
(16 KB)
Instruction
cache
(32 KB)
Address/data (o)
TLB
Address/data (i)
Clock
generator
Internal clock
6
CP0
Data Sheet U15585EJ1V0DS
CPU
µPD30122
CONTENTS
1.
PIN FUNCTIONS ..................................................................................................................................8
1.1
Pin Functions ............................................................................................................................................. 8
1.2
Pin Status in Specific States .................................................................................................................. 17
1.3
Pin Handling and I/O Circuit Types........................................................................................................ 21
1.4
Pin I/O Circuits ......................................................................................................................................... 23
2.
ELECTRICAL SPECIFICATIONS .......................................................................................................24
3.
PACKAGE DRAWING........................................................................................................................56
4.
RECOMMENDED SOLDERING CONDITIONS ................................................................................57
Data Sheet U15585EJ1V0DS
7
µPD30122
1. PIN FUNCTIONS
Remark # indicates active low.
1.1 Pin Functions
(1) Memory interface signals
Signal
(1/2)
I/O
Function
SCLK
Output
Operation clock for SDRAM
ADD(24:1)
Output
Higher 24 bits of the 25-bit address bus
These signals are used to specify addresses for the VR4122, SDRAM, ROM, and I/O space.
DATA(15:0)
I/O
16-bit data bus
These signals are used to transfer data between the VR4122 and the SDRAM, ROM, or I/O space.
DATA(31:16)/
GPIO(31:16)
I/O
Functions may differ depending on the DBUS32 pin setting.
• When DBUS32 = 1
These signals function as the higher 16 bits of the 32-bit data bus. They are used to transfer
data between the VR4122 and the DRAM or ROM.
• When DBUS32 = 0
These signals function as general-purpose I/O ports.
CKE(1:0)
Output
Clock enable signals for SDRAM
CKE(1:0) supports the following banks.
SDRAM bank CKE(1:0)
Bank 3
CKE 1
Bank 2
CKE 0
Bank 1
CKE 1
Bank 0
CKE 0
32-bit data bus
CS3#/ROMCS3#
CS2#/ROMCS2#
CS1#
CS0#
16-bit data bus
DQM3
DQM2
CS1#
CS0#
DQM3
Output
The function differs depending on the setting of the DBUS32 pin and the connected device.
• When DBUS32 = 1 and
SDRAM is accessed:
This is the byte enable signal for DATA(31:24) of the 32-bit data bus.
A 32-bit external I/O device is accessed:
This is the byte enable signal for DATA(31:24) of the 32-bit data bus.
• When DBUS32 = 0 and
SDRAM is accessed:
This is the CS signal for SDRAM. This signal becomes active when a command is issued for
the SDRAM connected to the highest address.
DQM2
Output
The function differs depending on the setting of the DBUS32 pin and the connected device.
• When DBUS32 = 1 and
SDRAM is accessed:
This is the byte enable signal for DATA(23:16) of the 32-bit data bus.
A 32-bit external I/O device is accessed:
This is the byte enable signal for DATA(23:16) of the 32-bit data bus.
• When DBUS32 = 0 and
SDRAM is accessed:
This is the CS signal for SDRAM. This signal becomes active when a command is issued for
the SDRAM connected to the second highest address.
DQM1
Output
The function differs depending on the connected device.
When SDRAM is accessed: This is the byte enable signal for DATA(15:8).
When a 32-bit external I/O device is accessed: This is the byte enable signal for DATA(15:8).
When a 16-bit external I/O device is accessed: This is the ADD0 signal of the I/O device.
8
Data Sheet U15585EJ1V0DS
µPD30122
(2/2)
Signal
I/O
Function
DQM0
Output
The function differs depending on the connected device.
When SDRAM is accessed: This is the byte enable signal for DATA(7:0).
When a 32-bit external I/O device is accessed: This is the byte enable signal for DATA(7:0).
When a 16-bit external I/O device is accessed: This is the high-byte enable signal of the I/O bus.
CS(1:0)#
Output
Chip select signal for SDRAM
RAS
Output
RAS signal for SDRAM
CAS
Output
CAS signal for SDRAM
SYSDIR/GPIO6
I/O
Direction signal for SDRAM
If not used as the SYSDIR signal, this signal can be used as a GPIO pin.
SPOWER
Output
Power supply control signal for SDRAM
RD#
Output
This signal becomes active when a read access is performed for data from the I/O space and ROM.
WR#
Output
This signal becomes active when writing data to the I/O space.
SWR#
Output
This signal becomes active when writing data to SDRAM.
ROMCS(1:0)#
Output
Chip select signals for ROM
CS(3:2)#/
ROMCS(3:2)#
Output
Chip select signals for an expansion SDRAM or expansion ROM
• When using expansion SDRAM
These signals function as CS(3:2)#.
• When using expansion ROM
These signals function as ROMCS(3:2)#.
(2) I/O device interface signals
Signal
IOCS(1:0)#
IORDY
I/O
Output
Input
Function
Device chip select signals
These signals become active when the VR4122 accesses the I/O device using the ADD bus or
DATA bus.
Device ready signal
Make this signal active in a state in which the I/O device can be accessed from the VR4122.
(3) Clock interface signals
Signal
I/O
Function
RTCX1
Input
RTCX2
Output
This is the 32.768 kHz oscillator’s output pin. It is connected to one side of a crystal resonator.
CLKX1
Input
This is the 18.432 MHz oscillator’s input pin. It is connected to one side of a crystal resonator.
CLKX2
Output
FIRCLK/TRCCLK
CLKOUT
This is the 32.768 kHz oscillator’s input pin. It is connected to one side of a crystal resonator.
This is the 18.432 MHz oscillator’s output pin. It is connected to one side of a crystal resonator.
I/O
This is the 48 MHz clock input pin. This signal inputs a clock when FIR is used.
If not used as the FIRCLK signal, this signal can be used as the clock for trace data transfer.
Output
This is the clock output to supply an external device. A 9.216 MHz clock is output in the nonHibernate mode. The clock output stops at low level during Hibernate.
Data Sheet U15585EJ1V0DS
9
µPD30122
(4) Battery monitor interface signals
Signal
BATTINH/
BATTINT#
I/O
Function
Input
The function differs depending on the setting of the MPOWER pin.
• When MPOWER = 0
BATTINH function
This signal enables/disables activation at power-on.
1: Activation enabled
0: Activation disabled
• When MPOWER = 1
BATTINT# function
This is an interrupt signal that is output when the remaining power is low during normal
operation. An external circuit checks the remaining battery power. Activate the signal at this pin
if voltage sufficient for operation cannot be supplied.
(5) Initialization interface signals
Signal
I/O
Function
MPOWER
Output
This signal indicates that the VR4122 is operating. This signal is inactive in Hibernate mode.
POWERON
Output
This signal indicates that the VR4122 is ready to operate. It becomes active when a power-on
factor is detected and becomes inactive when the BATTINH/BATTINT# signal check operation is
completed.
POWER
Input
This is the VR4122 activation signal.
RSTSW#
Input
This is the VR4122 reset signal.
RTCRST#
Input
This signal resets the RTC. When power is first supplied to a device, an external circuit must
assert the signal at this pin for about 2 s.
10
Data Sheet U15585EJ1V0DS
µPD30122
(6) RS-232-C interface signals
Signal
I/O
Function
RxD
Input
This is a receive data signal. It is used when the RS-232-C controller sends serial data to the
VR4122.
CTS#
Input
This is a transmit enable signal. Assert this signal when the RS-232-C controller is ready to
receive transmission of serial data.
DCD#/GPIO15
Input
This is a carrier detection signal. Assert this signal when valid serial data is being received. It is
also used as a power-on factor for the VR4122.
When this pin is not used for the DCD# signal, this pin can be used as an interrupt detection input
for the GIU.
DSR#
Input
This is the data set ready signal. Assert this signal when the RS-232-C controller is ready to
transfer serial data between the controller and the VR4122.
TxD/CLKSEL2,
RTS#/CLKSEL1,
DTR#/CLKSEL0
I/O
This function differs depending on the operating status.
• During normal operation (output)
Signals used for serial communication
TxD signal:
This is a transmit data signal. It is used when the VR4122 sends serial data to the RS-232-C
controller.
RTS# signal:
This is a transmit request signal. This signal is asserted when the VR4122 is ready to receive
serial data from the RS-232-C controller.
DTR# signal:
This is a terminal equipment ready signal. This signal is asserted when the VR4122 is ready
to transmit or receive serial data.
• During RTC reset (input)
Signals (CLKSEL(2:0)) used to set the CPU core operation frequency, BUSCLK frequency, and
internal bus clock frequency. These signals are sampled when the RTCRST# signal changes
from low level to high level.
For the relationship between the CLKSEL pin setting and each clock frequency, see Table 1-1.
Setting of CLKSEL and Frequency of PClock, VTClock, TClock, and MasterOut (Default
Value).
Table 1-1. Setting of CLKSEL and Frequency of PClock, VTClock, TClock, and MasterOut (Default Value)
CLKSEL(2:0)
PClock (MHz)
VTClock (MHz)
TClock (MHz)
MasterOut (MHz)
111
RFU
RFU
RFU
RFU
110
180.6
30.1
15.1
3.8
101
164.2
32.8
16.4
4.1
100
150.5
30.1
15.1
3.8
011
129.0
32.3
16.1
4.0
010
100.4
33.5
16.7
4.2
001
90.3
30.1
15.1
3.8
000
78.5
26.2
13.1
3.3
Remark RFU: Reserved for Future Use
Data Sheet U15585EJ1V0DS
11
µPD30122
(7) Debug serial interface signals
Signal
I/O
Function
DDIN/GPIO34
I/O
Debug serial data input signal. It is used when serial data is transferred from the external serial
controller to the VR4122.
This signal can be used as a general-purpose output port when not being used as the DDIN signal.
DCTS#/GPIO35
I/O
Transmit enable signal.
Assert this signal when the RS-232-C controller can receive the serial data transmission.
This signal can be used as a general-purpose output port when not being used as the DCTS#
signal.
DDOUT/
DBUS32/GPIO32
I/O
The functions differs depending on the operating status.
• During normal operation (output)
DDOUT: This signal functions as the debug serial transmit data signal.
• During RTC reset (input)
DBUS32: This signal functions as the data bus width switching signal. When the RTCRST#
signal changes from low to high, this signal is sampled.
1: Data bus is used with 32-bit width
0: Data bus is used with 16-bit width
This signal can be used as a general-purpose output port when not being used as the DDOUT or
DBUS32 signal.
DRTS#/
MIPS16EN/
GPIO33
I/O
The functions differs depending on the operating status.
• During normal operation (output)
DRTS#:
This signal functions as the debug serial transmit request signal.
• During RTC reset (input)
MIPS16EN: This signal functions as the MIPS16 instruction enable signal. When the RTCRST#
signal changes from low to high, this signal is sampled.
1: MIPS16 instructions enabled
0: MIPS16 instructions disabled
This signal can be used as a general-purpose output port when not being used as the DRTS# or
MIPS16EN signal.
(8) IrDA interface signals
Signal
I/O
Function
IRDIN/
TRCDATA1
I/O
This is an IrDA serial data input signal. It is used when the serial data is transferred from the IrDA
controller to the VR4122. Both FIR and SIR can be used. If the IrDA controller used is a Hewlett
Packard Company product, however, this signal should be used only for SIR.
This signal can be used as a trace data output signal when not being used as the IRDIN signal.
FIRDIN#/SEL/
TRCDATA2
I/O
The function differs according to the IrDA controller to be used.
• Hewlett Packard controller or SHARP Semiconductor controller
FIRDIN#: It is an FIR receive data input signal.
• TEMIC Semiconductor controller
SEL:
It is a signal output for the FIR/SIR switching.
This signal can be used as a trace data output signal when not being used as the FIRDIN# or SEL
signal.
IRDOUT#/
TRCDATA0
O
This is the IrDA serial data output signal. It is used when the serial data is transferred from the
VR4122 to the IrDA controller.
This signal can be used as a trace data output signal when not being used as the IRDOUT# signal.
12
Data Sheet U15585EJ1V0DS
µPD30122
(9) Clocked serial signals
Signal
SIN
I/O
Input
Function
Clocked serial input signal
SOUT
Output
Clocked serial output signal
SECLK
Output
Synchronous clock output for the clocked serial interface
(10) General-purpose I/O signals
Signal
I/O
Function
GPIO(3:0)
I/O
Maskable activation factor input signals.
These signals can be used as general-purpose I/O ports after activation.
GPIO(5:4)
I/O
General-purpose I/O ports.
SYSDIR/GPIO6
I/O
Refer to (1) Memory interface signals.
GPIO(8:7)
I/O
General-purpose I/O ports.
GPIO(12:9)
I/O
Maskable activation factor input signals.
These signals can be used as general-purpose I/O ports after activation.
GPIO13
I/O
General-purpose I/O port. This signal is recommended to be used as a VRC4173 interrupt.
DCD#/GPIO15
Input
Refer to (6) RS-232-C interface signals.
GPIO(31:16)/
DATA(31:16)
I/O
Refer to (1) Memory interface signals.
DDOUT/
DBUS32/
GPIO32
I/O
Refer to (7) Debug serial interface signals.
DRTS#/
MIPS16EN/
GPIO33
I/O
Refer to (7) Debug serial interface signals.
DDIN/GPIO34
I/O
Refer to (7) Debug serial interface signals.
DCTS#/GPIO35
I/O
Refer to (7) Debug serial interface signals.
(11) LED interface signal
Signal
LEDOUT#
I/O
Output
Function
This is an output signal for lighting LEDs in normal operation mode.
Data Sheet U15585EJ1V0DS
13
µPD30122
(12) PCI Like bus interface signals
Signal
I/O
Function
AD(31:0)
I/O
This is a 32-bit address bus and data bus.
In the address phase, addresses are output, and in the data phase, data is output.
CBE(3:0)
I/O
These are the bus-command/byte-enable signals.
In the address phase, bus commands are output, and in the data phase, they operate as the byteenable signals.
DEVSEL#
I/O
This signal is asserted when the target is accessed and continues being asserted until the
completion of the transaction.
FRAME#
I/O
This signal is asserted when the initiator starts the transaction. It also remains asserted
throughout burst transfer.
REQ(2:0)#
Input
GNT(2:0)#
Output
These signals are asserted when the master sends a request to the VR4122 for the bus mastership.
These signals are asserted when the VR4122 grants bus mastership to the device making the
request with the REQ# signal.
IRDY#
I/O
This signal is asserted when the initiator is in the data transfer enabled state.
LOCK#
I/O
This signal indicates a resource lock.
PAR
I/O
This signal outputs a low level if the number of “1” bits from the 36 AD(31:0) and CBE(3:0) signals
is even, and a high level if the number is odd.
PERR#
I/O
This signal is asserted when a parity error occurs following a parity check by the data-read initiator
in the read cycle or the data-write target in the write cycle.
SERR#
I/O
This signal is asserted when a fatal error for the system occurs.
STOP#
I/O
This signal is asserted when the target requires the initiator to abort the transaction.
TRDY#
I/O
This signal is asserted when the target is in the transfer-enabled state.
PCLK
CLKRUN
RST#
14
Output
I/O
Output
This is the PCI bus reference clock.
This signal controls the clock for power management.
This is the PCI bus reset signal.
Data Sheet U15585EJ1V0DS
µPD30122
(13) Debug interface signals
Signal
(1/2)
I/O
Function
JTCK
Input
This is the N-Wire clock input.
JTMS
Input
This is the N-Wire serial transfer mode selection signal.
JTDI/RMODE#
Input
This is the RMODE#/JTDI alternate function pin. When JTRST# is active, it functions as
RMODE#, and when JTRST# is inactive, it functions as JTDI. If a debugging tool is not connected
externally, pull up to high level.
• RMODE#: Input
When JTRST# is active, this becomes the reset mode pin. The debug reset initial value is
determined according to the level of this signal. Debug reset resets the processor with two kinds
of resets: a debug cold reset and debug soft reset. These two resets function in the same way
as a cold reset input and a soft reset input from the target system.
0: The debug reset is valid; the CPU core is reset.
1: The debug reset is invalid; the CPU core is not reset.
• JTDI: Input
When JTRST# is inactive this becomes the N-Wire serial data input.
JTDO
Output
JTRST
Input
This is the N-Wire serial data output.
This is the N-Wire unit reset signal.
BKTGIO#
I/O
• BKTGIO#: In the input setting
When JTRST# is inactive and BKTGIO# is in the input setting, BKTGIO# becomes the event
trigger/break request input pin. When the event trigger input is valid and during a trace, if
BKTGIO# is made low level, the MATCH packet is output once. Also, if BKTGIO# is made low
level when the break request input is valid, the normal mode user program is aborted, and the
processor is forcibly changed to debug mode. If BKTGIO# becomes low level in debug mode,
the break request is held pending until the processor returns to normal mode.
0: The MATCH packet is output. A break is requested and the processor is forcibly changed to
debug mode.
1: The current status of the processor is maintained.
• BKTGIO#: In the output setting
When JTRST# is inactive and BKTGIO# is in the output setting, BKTGIO# becomes the event
trigger/break output pin. While the processor is operating in normal mode, if an event is
detected upon a match with either of the conditions of the hardware breakpoints (instruction
address breakpoint or data access breakpoint), a low level (1 pulse) is output from BKTGIO# as
an event trigger, and report of the event detection is sent to the external debugging tool. All the
events detected after the last event trigger has been output are sent as one event trigger. If the
processor mode is changed to debug mode, the low-level output continues, and none of the as
unreported events are sent.
0: Detects a hardware breakpoint (= 1 cycle pulse)
The processor is in debug mode (> 1 cycle pulse)
1: The processor is in normal mode
FIRCLK/TRCCLK
I/O
Refer to (3) Clock interface signals.
Data Sheet U15585EJ1V0DS
15
µPD30122
(2/2)
Signal
I/O
Function
TRCEND/
NWIREEN/
HLDAK#
I/O
The function differs depending on the operations status.
• During normal operation (output)
TRCEND:
The signal that indicates the trace data is complete.
• During RTC reset (input)
NWIREEN: The signal that enables use of N-Wire. This signal is sampled when the RTCRST#
signal changes from low level to high level.
1: Use of N-Wire trace function enabled
0: Use of N-Wire trace function disabled
• When N-Wire trace function is disabled and the HLDEN bit of the BCUCNTREG1 resister
is 1
HLDAK#:
The signal that gives the mastership of the system bus and DRAM bus to the
external bus master.
IRDOUT#/
TRCDATA0
Output
Refer to (8) IrDA interface signals.
IRDIN/
TRCDATA1
I/O
Refer to (8) IrDA interface signals.
FIRDIN#/SEL/
TRCDATA2
I/O
Refer to (8) IrDA interface signals.
TRCDATA3/
HLDRQ#
I/O
The function differs depending on the operating status.
• N-Wire trace function enabled
TRCDATA3: Trace data output.
• N-Wire trace function disabled and HLDEN bit of BCUCNTREG1 register is 1
HLDRQ#:
The request signal for mastership of the system bus and DRAM bus from the
external bus master.
(14) Dedicated VDD and GND signals
Signal Name
Power Supply
Function
VDDP
1.8 V
Dedicated VDD for the PLL analog unit
GNDP
1.8 V
Dedicated GND for the PLL analog unit
VDDPD
1.8 V
Dedicated VDD for the PLL digital unit. Its function is identical to VDD1.
GNDPD
1.8 V
Dedicated GND for the PLL digital unit. Its function is identical to GND1.
CVDD
3.3 V
Dedicated VDD for the oscillator
CGND
3.3 V
Dedicated GND for the oscillator
VDD1
1.8 V
Normal 1.8 V VDD
GND1
1.8 V
GND for normal 1.8 V system
VDD3
3.3 V
Normal 3.3 V VDD
GND3
3.3 V
GND for normal 3.3 V system
Remark The VR4122 has two power supplies, but there are no restrictions on the order of supply voltage
application.
16
Data Sheet U15585EJ1V0DS
µPD30122
1.2 Pin Status in Specific States
(1/4)
When Reset by
RTC
In Hibernate
Mode or During
HALTimer
Shutdown
When Reset by
RSTSW
In Suspend
Mode
During Bus Hold
AD(31:0)
0
0
0
Hold
Note 1
ADD(24:1)
0
0
0
Note 2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
BKTGIO#
1
1
1
Hold
Hold
CAS
0
0
0
Note 2
Hi-Z
CBE(3:0)
0
0
0
Hold
Note 1
CKE(1:0)
0
0
0
Note 2
Hi-Z
Pin Name
BATTINH/BATTINT#
CLKOUT
0
0
CLK
CLK
CLK
CLKRUN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CS(1:0)#
Hi-Z
1
1
Note 2
Hi-Z
CS2#/ROMCS2#
Hi-Z
Note 3
1
Note 2
Note 4
CS3#/ROMCS3#
Hi-Z
Note 5
1
Note 2
Note 6
CTS#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
Note 2
Hi-Z
DATA(15:0)
Notes 1. Normal operation.
2. Maintains the previous status.
For the pin status during the bus hold period, however, refer to the During Bus Hold column.
3. Depends on the status of the BCUCNTREG3 register’s EXT_ROMCS0 bit and the DBUS32 pin.
When the EXT_ROMCS0 bit is 0 and the DBUS32 pin = 1: High level
If a combination other than above: High impedance
4. Depends on the status of the BCUCNTREG3 register’s EXT_ROMCS0 bit and the DBUS32 pin.
When the EXT_ROMCS0 bit is 0 and the DBUS32 pin = 1: High impedance
If a combination other than above: High level
5. Depends on the status of the BCUCNTREG3 register’s EXT_ROMCS1 bit and the DBCS32 pin.
When the EXT_ROMCS1 bit is 0 and DBUS32 = 1: High level
If a combination other than above: High impedance
6. Depends on the status of the BCUCNTREG3 register’s EXT_ROMCS1 bit and the DBCS32 pin.
When the EXT_ROMCS1 bit is 0 and DBUS32 = 1: High impedance
If a combination other than above: High level
Remark 0: Low level, 1: High level, Hi-Z: High impedance, Hold: Maintains the status of the preceding Fullspeed
mode
Data Sheet U15585EJ1V0DS
17
µPD30122
(2/4)
Pin Name
DATA(31:16)/GPIO(31:16)
When Reset by
RTC
In Hibernate
Mode or During
HALTimer
Shutdown
When Reset by
RSTSW
In Suspend
Mode
During Bus Hold
Note 1
Note 1
Note 1
Note 2
Note 3
DCD#/GPIO15
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DCTS#/GPIO35
Hi-Z
Note 4
Note 4
Hold
Hold
DDIN/GPIO34
Hi-Z
Note 5
Note 5
Hold
Hold
DDOUT/DBUS32/GPIO32
Hi-Z
Note 6
Note 6
Hold
Hold
DEVSEL#
Hi-Z
Hi-Z
Hi-Z
Hold
Note 7
DQM(3:0)
Hi-Z
0
0
Note 2
Hi-Z
DRTS#/MIPS16EN/GPIO33
Hi-Z
Note 8
Note 8
Hold
Hold
DSR#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DTR#/CLKSEL0
Hi-Z
1
1
Hold
Hold
Note 9
Hi-Z
Note 9
Hi-Z
Note 9
Hi-ZNote 9
FIRCLK/TRCCLK
Hi-Z
FIRDIN#/SEL/TRCDATA2
Hi-ZNote 9
Hi-ZNote 9
Hi-ZNote 9
HoldNote 9
HoldNote 9
Hi-Z
Hi-Z
Hi-Z
Hold
Note 7
FRAME#
Hi-Z
Note 9
Notes 1. When the DBUS32 bit is 1: Low level
When the DBUS32 bit is 0: High impedance
2. Maintain the previous status.
For the pin status during the bus hold period, however, refer to the During Bus Hold column.
3. When the DBUS32 bit is 1: High impedance
When the DBUS32 bit is 0: Maintains the previous status
4. Depends on the status of the GIUPODATEN register’s PIOEN35 bit.
When the PIOEN35 bit is 0: High impedance
When the PIOEN35 bit is 1: Maintains the status of the preceding Fullspeed mode
5. Depends on the status of the GIUPODATEN register’s PIOEN34 bit.
When the PIOEN34 bit is 0: High impedance
When the PIOEN34 bit is 1: Maintains the status of the preceding Fullspeed mode
6. Depends on the status of the GIUPODATEN register’s PIOEN32 bit.
When the PIOEN32 bit is 0: High level
When the PIOEN32 bit is 1: Maintains the status of the preceding Fullspeed mode
7. Normal operation
8. Depends on the status of the GIUPODATEN register’s PIOEN33 bit.
When the PIOEN33 bit is 0: High level
When the PIOEN33 bit is 1: Maintains the status of the preceding Fullspeed mode
9. Pin status when NWIREEN = 0; the pin status is undefined when NWIREEN = 1.
Remark 0: Low level, 1: High level, Hi-Z: High impedance, Hold: Maintains the status of the preceding Fullspeed
mode
18
Data Sheet U15585EJ1V0DS
µPD30122
(3/4)
When Reset by
RTC
In Hibernate
Mode or During
HALTimer
Shutdown
When Reset by
RSTSW
In Suspend
Mode
During Bus Hold
GNT(2:0)#
Hi-Z
Hi-Z
Hi-Z
Hold
Hold
GPIO(5:0)
Hi-Z
Hi-Z
Hi-Z
Hold
Hold
0
Note 1
Note 1
Note 2
Note 3
GPIO(13:7)
Hi-Z
Hi-Z
Hi-Z
Hold
Hold
IOCS(1:0)#
Hi-Z
Hi-Z
1
1
1
IORDY
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pin Name
GPIO6/SYSDIR
IRDIN/TRCDATA1
Hi-Z
Note 4
Hi-Z
Note 4
Hi-Z
Note 4
Hi-Z
Note 4
Hi-ZNote 4
IRDOUT#/TRCDATA0
0Note 4
0Note 4
0Note 4
0Note 4
0Note 4
IRDY#
Hi-Z
Hi-Z
Hi-Z
Hold
Note 5
JTCK
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDI/RMODE#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTMS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTRST#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
LEDOUT#
Hi-Z
1
1
1
Note 5
LOCK#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 5
MPOWER
0
0
1
1
1
PAR
0
0
Note 6
Hold
Note 5
PCLK
0
0
0
Hold
Note 5
PERR#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 5
POWER
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
POWERON
0
0
0
0
0
RAS
0
0
0
Note 2
Hi-Z
RD#
Hi-Z
Hi-Z
1
Note 2
Hi-Z
Notes 1. Depends on the setting of the BCUCNTREG3 register’s SYSDIR_EN bit
When the SYSDIR_EN bit is 1: Low level
When the SYSDIR_EN bit is 0: High impedance
2. Maintains the previous status.
For the pin status during the bus hold period, however, refer to the During Bus Hold column.
3. Depends on the setting of the BCUCNTREG3 register’s SYSDIR_EN bit
When the SYSDIR_EN bit is 1: High impedance
When the SYSDIR_EN bit is 0: Maintains the previous status
4. Pin status when NWIREEN = 0; the pin status is undefined when NWIREEN = 1.
5. Normal operation
6. Undefined. Drive either a low or high level.
Remark 0: Low level, 1: High level, Hi-Z: High impedance, Hold: Maintains the status of the preceding Fullspeed
mode
Data Sheet U15585EJ1V0DS
19
µPD30122
(4/4)
Pin Name
When Reset by
RTC
In Hibernate
Mode or During
HALTimer
Shutdown
When Reset by
RSTSW
In Suspend
Mode
During Bus Hold
REQ(2:0)#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ROMCS(1:0)#
Hi-Z
Hi-Z
1
1
1
0
0
0
Hold
Note 1
RSTSW#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RTCRST#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RTS#/CLKSEL1
Hi-Z
1
1
1
Hold
RxD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCLK
0
0
Note 2
Note 3
Hi-Z
SECLK
0
0
1
Hold
Hold
SERR#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 4
SIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SOUT
0
0
0
0
0
SPOWER
0
1
1
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 4
RST#
STOP#
SWR#
Hi-Z
0
0
Note 3
Hi-Z
TRCDATA3/HLDRQ#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TRCEND/NWIREEN/HLDAK#
Hi-Z
Hi-Z
Hi-Z
Note 5
0
TRDY#
Hi-Z
Hi-Z
Hi-Z
Hold
Note 4
TxD/CLKSEL2
Hi-Z
1
1
1
Hold
WR#
Hi-Z
Hi-Z
1
Note 3
Hi-Z
Notes 1. Maintains the previous status.
2. Outputs clock.
3. Maintains the previous status.
For the pin status during the bus hold period, however, refer to the During Bus Hold column.
4. Normal operation
5. Depends on the setting of the BCUCNTREG1 register’s HLDEN bit.
When the HLDEN bit is 1: Normal operation as HLDAK# pin
When the HLDEN bit is 0: High impedance
Remark 0: Low level, 1: High level, Hi-Z: High impedance, Hold: Maintains the status of the preceding Fullspeed
mode
20
Data Sheet U15585EJ1V0DS
µPD30122
1.3 Pin Handling and I/O Circuit Types
(1/2)
Pin Name
Pin Handling
Recommended Connection of Unused
Pins
Drive
Capability
I/O Circuit
Type
AD(31:0)
−
−
A
ADD(24:1)
−
−
Note 1
A
BATTINH/BATTINT#
−
−
−
B
BKTGIO#
Connect to VDD via a resistor
Note 2
CAS
−
CBE(3:0)
−
CKE(1:0)
−
CLKOUT
−
CLKRUN
Leave open
Pull up
−
Leave open
−
−
A
−
A
−
A
120 pF
A
Leave open
−
A
Connect to VDD via a resistor
−
A
120 pF
A
CS(1:0)#
−
CS2#/ROMCS2#
−
Leave open
120 pF
A
CS3#/ROMCS3#
−
Leave open
120 pF
A
CTS#
−
Connect to VDD or GND
−
A
DATA(15:0)
−
DATA(31:16)/GPIO(31:16)
−
DCD#/GPIO15
−
DCTS#/GPIO35
−
DDIN/GPIO34
−
DDOUT/DBUS32/GPIO32
Pull up/pull down
DEVSEL#
Pull up
−
−
120 pF
A
120 pF
A
−
B
Connect to VDD or GND via a resistor
−
A
Connect to VDD or GND via a resistor
−
A
−
A
Connect to VDD or GND via a resistor
−
−
DRTS#/MIPS16EN/GPIO33
Pull up/pull down
−
DSR#
−
A
−
120 pF
A
−
−
A
−
A
Connect to VDD via a resistor
−
DQM(3:0)
Connect to VDD or GND
−
A
FIRCLK/TRCCLK
−
Connect to VDD via a resistor
−
A
FIRDIN#/SEL/TRCDATA2
−
Connect to VDD or GND via a resistor
−
A
DTR#/CLKSEL0
−
Pull up/pull down
Connect to VDD via a resistor
−
A
GNT(2:0)#
−
Leave open
−
A
GPIO(2:0)
−
Connect to VDD or GND via a resistor
−
B
GPIO3
−
−
B
GPIO(5:4)
−
Connect to VDD or GND via a resistor
−
B
GPIO6/SYSDIR
−
Leave open
−
B
GPIO(13:7)
−
Connect to VDD or GND via a resistor
−
B
IOCS(1:0)#
−
Leave open
−
A
IORDY
−
Connect to VDD or GND via a resistor
−
A
IRDIN/TRCDATA1
−
Connect to VDD or GND via a resistor
−
A
FRAME#
Pull up
−
Notes 1. The drive capability of ADD(4:1) is 120 pF and that of the other signals is 40 pF.
2. Pull-up processing is recommended for expansion to the next model.
Remarks 1. External handling is not required for the pins with no special directions in the Pin Handling column (−).
2. For the pins with no special directions in the Recommended Connection of Unused Pins column,
follow the directions in Pin Handling column.
Data Sheet U15585EJ1V0DS
21
µPD30122
(2/2)
Pin Name
Pin Handling
−
IRDOUT#/TRCDATA0
Recommended Connection of Unused
Pins
Drive
Capability
I/O Circuit
Type
Leave open
−
A
IRDY#
Pull up
Connect to VDD via a resistor
−
A
JTCK
Note
Connect to VDD
−
B
JTDI/RMODE#
−
Connect to VDD
−
A
JTDO
−
Leave open
−
A
JTMS
Note
Connect to VDD
−
A
JTRST#
Pull down
Connect to GND
−
B
LEDOUT#
Pull up
−
A
LOCK#
Pull up
−
A
−
A
−
Connect to VDD via a resistor
MPOWER
−
PAR
−
Leave open
−
A
−
Leave open
−
A
Connect to VDD via a resistor
−
A
PCLK
PERR#
Pull up
−
POWER
−
−
−
B
POWERON
−
−
−
A
RAS
−
−
−
A
RD#
−
−
−
A
REQ(2:0)#
−
ROMCS(1:0)#
−
RST#
−
RSTSW#
−
RTCRST#
−
RTS#/CLKSEL1
−
SCLK
−
−
SECLK
Pull up
A
−
120 pF
A
−
A
−
−
B
−
−
B
−
−
A
−
A
120 pF
A
Leave open
−
A
Connect to VDD via a resistor
−
A
Leave open
Pull up/pull down
RxD
SERR#
Connect to VDD
Connect to VDD or GND
−
SIN
−
Connect to VDD or GND
−
A
SOUT
−
Leave open
−
A
SPOWER
−
−
A
−
A
−
A
−
A
−
A
−
A
−
A
−
A
STOP#
Pull up
Connect to VDD via a resistor
SWR#
−
TRCDATA3/HLDRQ#
−
−
Leave open
−
TRCEND/NWIREEN/HLDAK#
Pull down
TRDY#
Pull up
TxD/CLKSEL2
Pull up/pull down
WR#
−
Connect to VDD via a resistor
−
−
Leave open
Note Pull-up processing is recommended for expansion to the next model.
Remarks 1. External handling is not required for the pins with no special directions in the Pin Handling column (−).
2. For the pins with no special directions in the Recommended Connection of Unused Pins column,
follow the directions in Pin Handling column.
22
Data Sheet U15585EJ1V0DS
µPD30122
1.4 Pin I/O Circuits
Type A
Type B
VDD
Data
VDD
P-ch
Data
P-ch
IN/OUT
Output
disable
N-ch
IN/OUT
Open drain
Output
disable
N-ch
Input
enable
Data Sheet U15585EJ1V0DS
23
µPD30122
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Supply voltage
Input voltage
Symbol
Rating
Unit
VDD2
1.8 V (VDDP, VDDPD, VDD1)
−0.5 to +2.5
V
VDD3
3.3 V (CVDD, VDD3)
−0.5 to +4.0
V
VDD3 ≥ 3.7 V
−0.5 to +4.0
V
VDD3 < 3.7 V
−0.5 to VDD3 + 0.3
V
−65 to +150
°C
VI
Storage temperature
Condition
Tstg
Cautions 1. Do not short-circuit two or more output pins simultaneously.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The specifications and conditions shown in DC Characteristics and AC Characteristics are
the ranges for normal operation and quality assurance of the product.
3. VI can be −1.5 V if the input pulse is less than 10 ns.
24
Data Sheet U15585EJ1V0DS
µPD30122
Operating Conditions
(1) 150 MHz model
Parameter
Symbol
Supply voltage
Condition
MIN.
MAX.
Unit
VDD2
1.8 V (VDDP, VDDPD, VDD1)
1.8
2.0
V
VDD3
3.3 V (CVDD, VDD3)
3.0
3.6
V
−40
+85
°C
Ambient temperature
TA
Note 1
VDDS
3.0
V
Note 2
VDDH1
2.5
V
Note 3
VDDH2
3.0
V
Oscillation start voltage
Oscillation hold voltage
Oscillation hold voltage
Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to
oscillators of 32.768 kHz and 18.432 MHz.
2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 32.768 kHz.
3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 18.432 MHz.
(2) 180 MHz model
Parameter
Symbol
Supply voltage
Ambient temperature
Condition
MIN.
MAX.
Unit
VDD2
1.8 V (VDDP, VDDPD, VDD1)
1.9
2.0
V
VDD3
3.3 V (CVDD, VDD3)
3.0
3.6
V
−10
+70
°C
TA
Note 1
VDDS
3.0
V
Note 2
VDDH1
2.5
V
Note 3
VDDH2
3.0
V
Oscillation start voltage
Oscillation start voltage
Oscillation start voltage
Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to
oscillators of 32.768 kHz and 18.432 MHz.
2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 32.768 kHz.
3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 18.432 MHz.
Capacitance (TA = 25°°C, VDD = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Condition
fC = 1 MHz
Unmeasured pins returned to 0 V.
Data Sheet U15585EJ1V0DS
MIN.
MAX.
Unit
10
pF
10
pF
25
µPD30122
DC Characteristics
(1) 150 MHz model (TA = −40 to +85°°C, VDD2 = 1.8 to 2.0 V, VDD3 = 3.0 to 3.6 V)
Parameter
Symbol
Condition
Output voltage, high
VOH1
IOH = −2 mA
Output voltage, low
VOL1
IOL = 2 mA
Clock input voltage, highNote 1
Note 1
Clock input voltage, low
Input voltage, high
Note 3
Input voltage, low
VIL1
Input voltage, high
Note 4
Input voltage, low
VIL2
Note 2
VIH3
VIL3
Pulse under 10 ns
Notes 4, 5
Note 2
VIH2
Pulse under 10 ns
Note 4
TYP.
MAX.
0.8VDD3
VIH1
Pulse under 10 ns
Note 3
MIN.
(1/2)
Note 2
Unit
V
0.4
V
0.8VDD3
VDD3 + 0.3
V
−0.3
0.3VDD3
V
−1.5
0.3VDD3
V
2.0
VDD3 + 0.3
V
−0.3
0.3VDD3
V
−1.5
0.3VDD3
V
0.85VDD3
VDD3 + 0.3
V
−0.3
0.6
V
−1.5
0.3VDD3
V
Hysteresis voltage
VH
0.17VDD3
V
Input leakage current
ILI
VDD3 = 3.6 V, VI = VDD3, 0 V
±5
µA
Output leakage current
ILO
VDD3 = 3.6 V, VI = VDD3, 0 V
±5
µA
Notes 1. Applies to FIRCLK/TRCCLK pin.
2. Precision tests have not been performed. Only guaranteed as design characteristics.
3. Except RTCX1, CLKX1, FIRCLK/TRCCLK, POWER, RSTSW#, RTCRST#, DCD#/GPIO15, GPIO(13:0),
and BATTINH/BATTINT# pins.
4. Applies to POWER, RSTSW#, DCD#/GPIO15, GPIO(13:0), and BATTINH/BATTINT# pins.
5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
26
Data Sheet U15585EJ1V0DS
µPD30122
(2/2)
Parameter
Supply current
Symbol
IDD1Note 2
Condition
MIN.
TYP.
Note 1
MAX.
Unit
In Fullspeed mode
135
250
mA
In Standby mode
52
100
mA
In Suspend mode
8
26
mA
In Hibernate mode, VDD2 = 0.0 V,
0
0
µA
In Fullspeed mode
30
60
mA
In Standby mode
15
45
mA
In Suspend mode
3.5
10.5
mA
In Hibernate mode, when LED unit is off.
50
350
µA
when LED unit is off.
Note 3
IDD3
Notes 1. Unless otherwise specified, these are reference values at TA = 25°C, VDD2 = 1.9 V, VDD3 = 3.3 V.
2. Total current flowing to the VDDP, VDDPD, and VDD1 pins.
3. Total current flowing to the CVDD and VDD3 pins.
Remarks 1. In the Fullspeed mode, the maximum values of IDD1 and IDD3 are not generated at the same time.
2. A current over the TYP. value may flow depending on the usage conditions, so consider the MAX.
value of the supply current when designing the power supplies.
Data Sheet U15585EJ1V0DS
27
µPD30122
(2) 180 MHz model (TA = −10 to +70°°C, VDD2 = 1.9 to 2.0 V, VDD3 = 3.0 to 3.6 V)
(1/2)
Parameter
Symbol
Output voltage, high
Output voltage, low
Note 1
Clock input voltage, high
Note 1
Clock input voltage, low
Condition
VOH1
IOH = −2 mA
VOL1
IOL = 2 mA
Input voltage, high
Note 3
Input voltage, low
VIL1
Input voltage, high
Note 4
Input voltage, low
VIL2
Note 2
VIH3
VIL3
Pulse under 10 ns
Notes 4, 5
Note 2
VIH2
Pulse under 10 ns
Note 4
TYP.
MAX.
0.8VDD3
VIH1
Pulse under 10 ns
Note 3
MIN.
Note 2
Unit
V
0.4
V
0.8VDD3
VDD3 + 0.3
V
−0.3
0.3VDD3
V
−1.5
0.3VDD3
V
2.0
VDD3 + 0.3
V
−0.3
0.3VDD3
V
−1.5
0.3VDD3
V
0.85VDD3
VDD3 + 0.3
V
−0.3
0.6
V
−1.5
0.3VDD3
V
Hysteresis voltage
VH
0.17VDD3
V
Input leakage current
ILI
VDD3 = 3.6 V, VI = VDD3, 0 V
±5
µA
Output leakage current
ILO
VDD3 = 3.6 V, VI = VDD3, 0 V
±5
µA
Notes 1. Applies to FIRCLK/TRCCLK pin.
2. Precision tests have not been performed. Only guaranteed as design characteristics.
3. Except RTCX1, CLKX1, FIRCLK/TRCCLK, POWER, RSTSW#, RTCRST#, DCD#/GPIO15, GPIO(13:0),
and BATTINH/BATTINT# pins.
4. Applies to POWER, RSTSW#, DCD#/GPIO15, GPIO(13:0), and BATTINH/BATTINT# pins.
5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
28
Data Sheet U15585EJ1V0DS
µPD30122
(2/2)
Parameter
Supply current
Symbol
Note 2
IDD1
IDD3Note 3
Condition
MIN.
TYP.
Note 1
MAX.
Unit
In Fullspeed mode
180
320
mA
In Standby mode
52
100
mA
In Suspend mode
10
30
mA
In Hibernate mode, VDD2 = 0.0 V,
when LED unit is off.
0
0
µA
In Fullspeed mode
30
60
mA
In Standby mode
15
45
mA
In Suspend mode
3.5
10.5
mA
In Hibernate mode, when LED unit is off.
50
350
µA
Notes 1. Unless otherwise specified, these are reference values at TA = 25°C, VDD2 = 1.95 V, VDD3 = 3.3 V.
2. Total current flowing to the VDDP, VDDPD, and VDD1 pins.
3. Total current flowing to the CVDD, and VDD3 pins.
Remarks 1. In the Fullspeed mode, the maximum values of IDD1 and IDD3 are not generated at the same time.
2. A current over the TYP. value may flow depending on the usage conditions, so consider the MAX.
value of the supply current when designing the power supplies.
Data Sheet U15585EJ1V0DS
29
µPD30122
Data Retention Characteristics (TA = 25°°C)
Parameter
Data retention voltageNote
Data retention input voltage, high
Symbol
Condition
MIN.
MAX.
Unit
VDDDR3
Hibernate mode, 3.3 V power supply
2.5
3.6
V
VIHDR
RTCRST# pins
0.9VDDDR3
V
Note The data retention voltage is the voltage at which the operation of the ElapsedTime counter and the data
retention of the registers of the following peripheral units are guaranteed, and is not applied to the internal
data of the CPU core.
BCU: BCUCNTREG3
PMU: PMUCNTREG(15:8), PMUCNT2REG, PMUWAITREG, PMUTCLKDIVREG, PMUINTRCLKDIVREG
RTC:
ETIMELREG,
ETIMEMREG,
ETIMEHREG,
ECMPLREG,
ECMPMREG,
ECMPHREG,
RTCL1LREG, RTCL1HREG, RTCL1CNTLREG, RTCL1CNTHREG, RTCL2LREG, RTCL2HREG,
RTCL2CNTLREG, RTCL2CNTHREG, RTCINTREG(2:0)
30
GIU:
GIUPODATL, GIUPODATEN
LED:
LEDHTSREG, LEDLTSREG, LEDCNTREG
Data Sheet U15585EJ1V0DS
µPD30122
AC Characteristics (TA = −40 to +85°°C)
AC test input waveform
(a) DATA(15:0), DATA(31:16)/GPIO(31:16), IORDY, RxD, CTS#, DSR#, TxD/CLKSEL2, FIRCLK/TRCCLK,
RTS#/CLKSEL1, DTR#/CLKSEL0, IRDIN/TRCDATA1, FIRDIN#/SEL/TRCDATA2, DDIN/GPIO34, DCTS#/
GPIO35, DDOUT/DBUS32/GPIO32, AD(31:0), CBE(3:0), DEVSEL#, FRAME#, REQ(2:0)#, IRDY#, LOCK#,
PAR, PERR#, SERR#, STOP#, TRDY#, CLKRUN, DRTS#/MIPS16EN/GPIO33, SIN, TRCDATA3/HLDRQ#
VDD
2.0 V
2.0 V
Measurement points
0.3 V
0.3 V
0V
(b) BATTINH/BATTINT#, DCD#/GPIO15, GPIO(13:7), SYSDIR/GPIO6, GPIO(5:0), POWER, RSTSW#, RTCRST#
VDD
0.75VDD
0.75VDD
Measurement points
0.2 V
0.2 V
0V
AC test output measurement points
VDD
0.5VDD
Measurement points
0.5VDD
0V
Data Sheet U15585EJ1V0DS
31
µPD30122
Load conditions
Note
(a) SCLK, ADD(24:10)
, ADD(4:1), CKE(1:0), DQM(3:0), ROMCS(1:0)#, CS(3:2)#/ROMCS(3:2)#, CS(1:0)#,
DATA(31:16)/GPIO(31:16), DATA(15:0), RAS
Note
Note
, CAS
SCLK, ADD(24:10)Note, ADD(4:1), CKE(1:0), DQM(3:0),
ROMCS(1:0)#, CS(3:2)#/ROMCS(3:2)#, CS(1:0)#,
DATA(31:16)/GPIO(31:16), DATA(15:0), RASNote, CASNote,
SWR#Note
, SWR#
Note
DUT
CL = 120 pF
Note The ADD(24:10), RAS, CAS, and SWR# pins are low-drive-capacity pins.
These pins are
measurement using 120 pF, but designing with an external load of 40 pF or lower is recommended.
(b) ADD(9:5), SPOWER, IOCS(1:0)#, RD#, WR#, MPOWER, POWERON, TxD/CLKSEL2, RTS#/CLKSEL1,
DTR#/CLKSEL0, FIRDIN#/SEL/TRCDATA2, IRDOUT#/TRCDATA0, DDOUT/DBUS32/GPIO32, DDIN/GPIO34,
DCTS#/GPIO35, GPIO(13:0), LEDOUT#, CLKOUT, AD(31:0), CBE(3:0), DEVSEL#, FRAME#, GNT(2:0)#,
IRDY#, LOCK#, PAR, PERR#, SERR#, TRDY#, STOP#, PCLK, CLKRUN, RST#, DRTS#/MIPS16EN/GPIO33,
SECLK, SOUT, TRCEND/NWIREEN/HLDAK#
ADD(9:5), SPOWER, IOCS(1:0)#, RD#, WR#, MPOWER,
POWERON, TxD/CLKSEL2, RTS#/CLKSEL1, DTR#/CLKSEL0,
FIRDIN#/SEL/TRCDATA2, IRDOUT#/TRCDATA0,
DDOUT/DBUS32/GPIO32, DDIN/GPIO34, DCTS#/GPIO35,
GPIO(13:0), LEDOUT#, CLKOUT, AD(31:0), CBE(3:0),
DEVSEL#, FRAME#, GNT(2:0)#, IRDY#, LOCK#, PAR,
PERR#, SERR#, TRDY#, STOP#, PCLK, CLKRUN, RST#,
DRTS#/MIPS16EN/GPIO33, SECLK, SOUT,
TRCEND/NWIREEN/HLDAK#
32
Data Sheet U15585EJ1V0DS
DUT
CL = 40 pF
µPD30122
(1) Clock parameter
Parameter
FIRCLK clock frequency
FIRCLK clock duty
Symbol
Note 1
Note 1
Note 2
SCLK high-level width
Note 2
SCLK low-level width
Note 3
SCLK jitter
Condition
MIN.
TYP.
MAX.
Unit
fFIRCYC1
In FIR 4 Mbps
47.99520
48
48.00480
MHz
fFIRCYC2
In FIR 1.152/0.576 Mbps
47.93800
48
48.02976
MHz
90
%
tFIRDUTY
10
tCH
3.5
ns
tCL
3.5
ns
tJitter
CPU core operating frequency
fPCYC
3.5
Note 4
%
CLKSEL(2:0) = 111
RFU
MHz
CLKSEL(2:0) = 110Note 5
180.6
MHz
CLKSEL(2:0) = 101Note 5
164.2
MHz
CLKSEL(2:0) = 100
150.5
MHz
CLKSEL(2:0) = 011
129.0
MHz
CLKSEL(2:0) = 010
100.4
MHz
CLKSEL(2:0) = 001
90.3
MHz
CLKSEL(2:0) = 000
78.5
MHz
Notes 1. Applies to the FIRCLK pin.
2. Applies to the SCLK pin.
3. Precision tests have not been performed. Only guaranteed as design characteristics.
4. Do not set CLKSEL(2:0) = 111.
5. The settings CLKSEL(2:0) = 110 and 101 are only guaranteed for the 180 MHz model. Do not apply
these settings to the 150 MHz model.
Remark CLKSEL(2:0): Value set to the TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins after reset.
tCH
tCL
SCLK
(output)
Data Sheet U15585EJ1V0DS
33
µPD30122
(2) Reset parameter
Parameter
Symbol
Reset input low-level width
tWRSL
Condition
MIN.
RTCRST# pin
MAX.
Unit
µs
305
tWRSL
RTCRST#
(input)
Remark For the RTCRST# characteristics at power application, refer to VR4122 User’s Manual.
(3) Initialization parameter
Parameter
Symbol
Data sampling time
(from RTCRST# ↑)
tSS
Output delay time (from RTCRST# ↑)
tOD
Condition
MIN.
61.04
RTC
(internal clock)
RTCRST#
(input)
TxD/CLKSEL2,
RTS#/CLKSEL1,
DTR#/CLKSEL0,
DDOUT/DBUS32/GPIO32,
DRTS#/MIPS16EN/GPIO33
(I/O)
tOD
tSS
Hi-Z
Sampling
Remark Set the input data level by using a pull-up or pull-down resistor with high resistance.
34
Data Sheet U15585EJ1V0DS
MAX.
Unit
61.04
µs
µs
µPD30122
(4) GPIO interface parameter (1/2)
Parameter
Note 1
Input level width
GPIO input rise time
GPIO input fall time
Output level width
Symbol
Condition
MIN.
MAX.
163 × N
Unit
tINP1
Note 2
tGPINR1
Note 3
200
ns
tGPINR2
Note 4
10
ns
tGPINF1
Note 3
200
ns
tGPINF2
Note 4
10
ns
tOUTP
Note 5
ns
30
ns
Notes 1. The N value is set using the IDIV(1:0) bits of the PMUINTRCLKDIVREG register.
IDIV(1:0)
N
11
RFU
10
4
01
8
00
2
2. Applies to the GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DCD#/GPIO15, and DATA(31:16)/GPIO(31:16)
pins.
3. Applies to the GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), and DCD#/GPIO15 pins.
4. Applies to the DATA(31:16)/GPIO(31:16) pins.
5. Applies to the GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DCD#/GPIO15, DATA(31:16)/GPIO(31:16),
DDOUT/DBUS32/GPIO32, DRTS#/MIPS16EN/GPIO33, DDIN/GPIO34, DCTS#/GPIO35 pins.
Caution These parameters apply when the SYSDIR/GPIO6, DATA(31:16)/GPIO(31:16), DDOUT/DBUS32/GPIO32,
DRTS#/MIPS16EN/GPIO33, DDIN/GPIO34, or DCTS#/GPIO35 pin is used as a GPIO signal.
Data Sheet U15585EJ1V0DS
35
µPD30122
(4) GPIO interface parameter (2/2)
(a) Input level width
tINP1Note
Note GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DATA(31:16)/GPIO(31:16) pins
(b) GPIO input rise/fall time
tGPINF1 Note 1
tGPINF2 Note 2
tGPINR1 Note 1
tGPINR2 Note 2
Notes 1. GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7) pins
2. DATA(31:16)/GPIO(31:16) pins
(c) Output level width
tOUTPNote
Note GPIO(5:0), SYSDIR/GPIO6, GPIO(13:7), DATA(31:16)/GPIO(31:16), DDOUT/DBUS32/GPIO32,
DRTS#/MIPS16EN/GPIO33, DDIN/GPIO34, DCTS#/GPIO35 pins
36
Data Sheet U15585EJ1V0DS
µPD30122
(5) Normal ROM parameter (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tACC
T × N − 19
ns
Data access time (from ROMCS(3:0)# ↓)
tCE
T × N − 19
ns
Data access time (from RD# ↓)
tOE
T × (N − 1) − 29
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note
Data access time (from address)
Note
Note
Note The value of N is set by using the rom2_wait(3:0) bits of the ROMSPEEDREG register.
The value of T is set by using the CLKSEL(2:0) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins) and the VTDIV(2:0) bits of the PMUTCLKDIVREG register.
rom2_wait(3:0)
N
rom2_wait(3:0)
N
1111
18
0111
10
1110
17
0110
9
1101
16
0101
8
1100
15
0100
7
1011
14
0011
6
1010
13
0010
5
1001
12
0001
4
1000
11
0000
3
VTDIV(2:0)
CLKSEL(2:0)
000
001
010
011
100
101
110
(Divided by 2) (Divided by 3) (Divided by 4) (Divided by 5) (Divided by 6)
111
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
110
RFU
RFU
RFU
16.6
22.1
27.6
33.2
RFU
101
RFU
RFU
RFU
18.2
24.3
30.4
RFU
RFU
100
33.2
RFU
RFU
19.9
26.6
33.2
RFU
RFU
011
31.0
RFU
15.5
23.3
31.0
RFU
RFU
RFU
010
29.9
RFU
19.9
29.9
RFU
RFU
RFU
RFU
001
33.2
RFU
22.1
33.2
RFU
RFU
RFU
RFU
000
38.2
RFU
25.5
38.2
RFU
RFU
RFU
RFU
Data Sheet U15585EJ1V0DS
111
37
µPD30122
(5) Normal ROM parameter (2/2)
ADD(24:1)
(output)
tACC
ROMCS(3:0)#
(output)
tCE
RD#
(output)
tOE
DATA
(I/O)
Invalid
Invalid
tDS
Remark The broken lines indicate high impedance.
38
Data Sheet U15585EJ1V0DS
tDH
µPD30122
(6) Page ROM parameter (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tACC1
T × N − 19
ns
tACC2
T × M − 18
ns
Data access time (from ROMCS(3:0)# ↓)
tCE
T × N − 19
ns
Data access time (from RD# ↓)
tOE
T × (N − 1) − 29
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
Note
Data access time (from address)
Note
Note
Note The value of N is set by using the rom2_wait(3:0) bits of the ROMSPEEDREG register.
The value of M is set by using the rom4_wait(1:0) bits of the ROMSPEEDREG register.
The value of T is set by using the CLKSEL(2:0) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins) and the VTDIV bit of the PMUTCLKDIVREG register.
rom2_wait(3:0)
N
rom2_wait(3:0)
N
rom4_wait(1:0)
M
1111
18
0111
10
11
5
1110
17
0110
9
10
4
1101
16
0101
8
01
3
1100
15
0100
7
00
2
1011
14
0011
6
1010
13
0010
5
1001
12
0001
4
1000
11
0000
3
VTDIV(2:0)
CLKSEL(2:0)
000
001
010
011
100
101
110
(Divided by 2) (Divided by 3) (Divided by 4) (Divided by 5) (Divided by 6)
111
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
110
RFU
RFU
RFU
16.6
22.1
27.6
33.2
RFU
101
RFU
RFU
RFU
18.2
24.3
30.4
RFU
RFU
100
33.2
RFU
RFU
19.9
26.6
33.2
RFU
RFU
011
31.0
RFU
15.5
23.3
31.0
RFU
RFU
RFU
010
29.9
RFU
19.9
29.9
RFU
RFU
RFU
RFU
001
33.2
RFU
22.1
33.2
RFU
RFU
RFU
RFU
000
38.2
RFU
25.5
38.2
RFU
RFU
RFU
RFU
Data Sheet U15585EJ1V0DS
111
39
µPD30122
(6) Page ROM parameter (2/2)
ADD(24:1)
(output)
tACC2
tACC1
ROMCS(3:0)#
(output)
tCE
RD#
(output)
tOE
DATA
(I/O)
Invalid
Invalid
tDS
Remark The broken lines indicate high impedance.
40
Data Sheet U15585EJ1V0DS
tDH
tDS
tDH
µPD30122
(7) Flash memory mode write parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Write cycle time
tAVAV
150
ns
Address setup time (to WR# ↑)
tAVWH
75
ns
Address setup time (to ROMCS(3:0)# ↓)
tAVEL
0
ns
ROMCS(3:0)# setup time (to WR# ↓)
tELWL
10
ns
WR# low-level width
tWLWH
75
ns
ROMCS(3:0)# hold time (from WR# ↑)
tWHEH
10
ns
Address hold time (from WR# ↑)
tWHAX
10
ns
WR# high-level width
tWHWL
75
ns
Address setup time (to WR# ↓)
tAVWL
25
ns
Data output setup time (to WR# ↑)
tDVWH
75
ns
Data output hold time (from WR# ↑)
tWHDX
10
ns
tAVAV
ADD(24:1)
(output)
tAVWH
ROMCS(3:0)#
(output)
tAVEL
tWLWH
WR#
(output)
DATA
(I/O)
tWHEH
tELWL
tAVWL
tWHWL
tWHAX
Invalid
tDVWH
Data Sheet U15585EJ1V0DS
tWHDX
41
µPD30122
(8)
Flash memory mode read parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data output delay time from address
tAVQV
180
ns
Data output delay time from ROMCS(3:0)#
tELQV
180
ns
Address setup time (to ROMCS(3:0)# ↓)
tAVEL
0
ns
Data output delay time from RD# ↓
tGLQV
80
ns
Address setup time (to RD# ↓)
tAVGL
0
ns
ROMCS(3:0)# hold time (from RD# ↑)
tGHEH
10
ns
Address hold time (from RD# ↑)
tGHAX
10
ns
RD# high-level width
tGHGL
75
ns
Data input setup time
tDS
0
ns
Data input hold time
tDH
5
ns
tELGL
10
ns
ROMCS(3:0)# setup time (to RD# ↓)
ADD(24:1)
(output)
tGHAX
ROMCS(3:0)#
(output)
tAVEL
tGHEH
tELGL
RD#
(output)
tGHGL
tAVGL
DATA
(I/O)
Invalid
Invalid
tDS
tGLQV
tELQV
tALQV
Remark The broken lines indicate high impedance.
42
Data Sheet U15585EJ1V0DS
tDH
µPD30122
(9) I/O (LCD) interface parameter (1/2)
Parameter
Symbol
Address setup time (to command signal ↓)
Note 1, 2
Address hold time (from command signal ↑)
Note 1, 2
Note 1, 2
Command signal recovery time
IORDY sampling start timeNote 2
Command signal delay time from IORDY ↑
Notes 1, 2
IORDY hold time (from command signal ↑)
Note 1
Condition
MIN.
MAX.
Unit
tAS
T × K − 15
ns
tAH
T × N − 15
ns
tRY
T × (N + 1) −
15
ns
tCLR
T × L − 15
ns
tRHCH
T × M − 15
T × (M + 2) + 15
ns
tRYZ
0
ns
Notes 1, 2
Data output setup time (to command signal ↓)
tDSTC
T × (K − 1) − 15
ns
Data output setup time (to command signal ↑)Notes 1, 2
tDVCH
T × (K + L + M − 1) − 15
ns
Data output hold time (from command signal ↑)Note 1, 2
tCHDV
T×N
ns
tDS
0
ns
tDH
5
ns
Data input setup time (to command signal ↑)
Note 1
Data input hold time (from command signal ↑)
Note 1
Notes 1. With the VR4122, the RD# and WR# signals are called the command signals for the LCD interface.
2. The values of K, L, M, and N are set by using the ion_1_wait(3:0) bits, ion_2_wait(3:0) bits,
ion_3_wait(3:0) bits, and ion_5_wait(1:0) bits, respectively, of the IOnSPEEDREG register. The value
of T is set by using the CLKSEL(2:0) bits (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins)
and the VTDIV(2:0) bits of the PMUTCLKDIVREG register (n = 0, 1).
ion_1_wait(3:0)
ion_2_wait(3:0)
ion_3_wait(3:0)
K
(ion_1_wait(3:0))
L
(ion_2_wait(3:0))
M
(ion_3_wait(3:0))
ion_5_wait(1:0)
N
1111
16
14
18
11
4
1110
15
13
17
10
3
1101
14
12
16
01
2
1100
13
11
15
00
1
1011
12
10
14
1010
11
9
13
1001
10
8
12
1000
9
7
11
0111
8
6
10
0110
7
5
9
0101
6
4
8
0100
5
3
7
0011
4
2
6
0010
3
1
5
0001
2
0
4
0000
1
−1
3
Remark n = 0, 1
Data Sheet U15585EJ1V0DS
43
µPD30122
(9) I/O (LCD) interface parameter (2/2)
VTDIV(2:0)
CLKSEL(2:0)
000
001
010
011
100
101
110
(Divided by 2) (Divided by 3) (Divided by 4) (Divided by 5) (Divided by 6)
111
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
110
RFU
RFU
RFU
16.6
22.1
27.6
33.2
RFU
101
RFU
RFU
RFU
18.2
24.3
30.4
RFU
RFU
100
33.2
RFU
RFU
19.9
26.6
33.2
RFU
RFU
011
31.0
RFU
15.5
23.3
31.0
RFU
RFU
RFU
010
29.9
RFU
19.9
29.9
RFU
RFU
RFU
RFU
001
33.2
RFU
22.1
33.2
RFU
RFU
RFU
RFU
000
38.2
RFU
25.5
38.2
RFU
RFU
RFU
RFU
ADD(24:1)
(output)
DQM(3:0)
(output)
IOCS0#,
IOCS1#
(output)
tAH
tAS
RD#/WR#
(output)
tRY
tCLR
IORDY
(input)
DATA
(output)
tDSTC
tRHCH
tRYZ
tDVCH
tCHDV
Invalid
tDS tDH
DATA
(input)
Invalid
Invalid
Remark The broken lines indicate high impedance.
44
Data Sheet U15585EJ1V0DS
111
µPD30122
(10) Bus hold parameter (1/3)
Parameter
Symbol
Note
Condition
MIN.
MAX.
Unit
HLDRQ# input pulse width
tHP
In Fullspeed/Standby/Suspend mode
271
ns
Data floating delay time
tOFF
In Fullspeed/Standby/Suspend mode
0
ns
Data valid delay time
tON
In Fullspeed/Standby/Suspend mode
0
ns
Note When the VR4122 receives an input signal of less than 271 ns, the bus hold operation may malfunction.
Change the signal input to the HLDRQ# pin to one with a pulse width of 271 ns or more.
(a) Starting bus hold
CLKX1
(input)
HLDRQ#
(input)
Sampling
HLDAK#
(output)
tOFF
Note
Note Applies to the following pins.
• ADD(24:1), DATA(15:0), CKE(1:0), DQM(3:0), CS(1:0)#, RAS, CAS, SCLK, RD#, WR#, and SWR#
pins
• SYSDIR/GPIO6 pin when the load-reducing buffer direction is controlled by setting the SYSDIR_EN
bit of the BCUCNTREG3 register
• DATA(31:16)/GPIO(31:16) pins in 32-bit data bus mode
• CS(3:2)#/ROMCS(3:2)# pins when using the expansion memory space as SDRAM by setting the
EXT_ROMCS(1:0) bits of the BCUCNTREG3 register in the 32-bit data bus mode
Remark The broken lines indicate high impedance.
Data Sheet U15585EJ1V0DS
45
µPD30122
(10) Bus hold parameter (2/3)
(b) Releasing bus hold (HLDRQ#)
CLKX1
(input)
HLDRQ#
(input)
Sampling
HLDAK#
(output)
tON
Note
Note Applies to the following pins.
• ADD(24:1), DATA(15:0), CKE(1:0), DQM(3:0), CS(1:0)#, RAS, CAS, SCLK, RD#, WR#, and SWR#
pins
• SYSDIR/GPIO6 pin when the load-reducing buffer direction is controlled by setting the SYSDIR_EN
bit of the BCUCNTREG3 register
• DATA(31:16)/GPIO(31:16) pins in 32-bit data bus mode
• CS(3:2)#/ROMCS(3:2)# pins when using the expansion memory space as SDRAM by setting the
EXT_ROMCS(1:0) bits of the BCUCNTREG3 register in the 32-bit data bus mode
Remark The broken lines indicate high impedance.
46
Data Sheet U15585EJ1V0DS
µPD30122
(10) Bus hold parameter (3/3)
(c) Releasing bus hold (RSTSW#)
RTCX1
(input)
CLKX1
(input)
RSTSW#
(input)
Sampling
HLDRQ#
(input)
HLDAK#
(output)
tON
Note
Note Applies to the following pins.
• ADD(24:1), DATA(15:0), CKE(1:0), DQM(3:0), CS(1:0)#, RAS, CAS, SCLK, RD#, WR#, and SWR#
pins
• SYSDIR/GPIO6 pin when the load-reducing buffer direction is controlled by setting the SYSDIR_EN
bit of the BCUCNTREG3 register
• DATA(31:16)/GPIO(31:16) pins in 32-bit data bus mode
• CS(3:2)#/ROMCS(3:2)# pins when using the expansion memory space as SDRAM by setting the
EXT_ROMCS(1:0) bits of the BCUCNTREG3 register in the 32-bit data bus mode
Remark The broken lines indicate high impedance.
Data Sheet U15585EJ1V0DS
47
µPD30122
(11) Serial interface parameter (1/2)
Parameter
Symbol
Note
TxD output pulse width
Note
RxD input pulse width
Note
IRDOUT# high-level output pulse width
IRDIN input pulse width
Condition
MIN.
MAX.
Unit
tTXD
N – 0.1
N + 0.1
µs
tRXD
(9/16) × N
tIRDOUT
(3/16) × N – 1
tIRDIN
1
µs
(3/16) × N + 1
µs
µs
Note N indicates the data transfer rate per bit, which is determined by the divisor of the baud-rate generator that
is set with the SIUDLL and SIUDLM registers.
Baud Rate (bps)
Divisor
(SIUDLM, SIUDLL Resister)
N (µs)
50
23,040
20,000.00
75
15,360
13,333.33
110
10,473
9,090.91
134.5
8,565
7,434.94
150
7,680
6,666.67
300
3,840
3,333.33
600
1,920
1,666.67
1,200
960
833.33
1,800
640
555.56
2,000
576
500.00
2,400
480
416.67
3,600
320
277.78
4,800
240
208.33
7,200
160
138.89
9,600
120
104.17
19,200
60
52.08
38,400
30
26.04
57,600
20
17.36
115,200
10
8.68
128,000
9
7.81
144,000
8
6.94
192,000
6
5.21
230,400
5
4.34
288,000
4
3.47
384,000
3
2.60
576,000
2
1.74
1,152,000
1
0.868
Remark Baud rate = (18.432 MHz/16)/(value set in the SIUDLM or SIUDLL register)
48
Data Sheet U15585EJ1V0DS
µPD30122
(11) Serial interface parameter (2/2)
TxD
(output)
tTXD
RxD
(input)
tRXD
IRDOUT#
(output)
tIRDOUT
IRDIN
(input)
tIRDIN
Data Sheet U15585EJ1V0DS
49
µPD30122
(12) Debug serial interface parameter
Parameter
Note
DDOUT output pulse width
Note
DDIN input pulse width
Symbol
Condition
MIN.
MAX.
Unit
tDDOUT
N – 0.1
N + 0.1
µs
tDDIN
(9/16) × N
µs
Note N indicates the data transfer rate per bit, which is determined by the divisor of the baud rate generator set
with the DSIUDLL and DSIUDLM registers.
Baud Rate (bps)
Divisor
(DSIUDLM, DSIUDLL Registers)
N (µs)
50
23,040
20,000.00
75
15,360
13,333.33
110
10,473
9,090.91
134.5
8,565
7,434.94
150
7,680
6,666.67
300
3,840
3,333.33
600
1,920
1,666.67
1,200
960
833.33
1,800
640
555.56
2,000
576
500.00
2,400
480
416.67
3,600
320
277.78
4,800
240
208.33
7,200
160
138.89
9,600
120
104.17
19,200
60
52.08
38,400
30
26.04
57,600
20
17.36
115,200
10
8.68
128,000
9
7.81
144,000
8
6.94
192,000
6
5.21
230,400
5
4.34
288,000
4
3.47
384,000
3
2.60
576,000
2
1.74
1,152,000
1
0.868
Remark Baud rate = (18.432 MHz/16)/(value set in the DSIUDLM or DSIUDLL register)
DDIN
(input)
tDDIN
DDOUT
(output)
tDDOUT
50
Data Sheet U15585EJ1V0DS
µPD30122
(13) SDRAM interface parameter (1/2)
Parameter
Note
Symbol
Condition
MIN.
MAX.
Unit
3.5
%
SCLK jitter
tJitter
SCLK high-level width
tCH
3.5
ns
SCLK low-level width
tCL
3.5
ns
Output delay time (from SCLK ↑)
tDSP
1.1
11.7
ns
Output delay time (from SCLK ↓)
tDSN
−5.8
18.6
ns
Data input setup time
tSDS
6.2
ns
Data input hold time
tSDH
2.9
ns
Note Precision tests have not been performed. Only guaranteed as design characteristics.
Data Sheet U15585EJ1V0DS
51
µPD30122
(13) SDRAM interface parameter (2/2)
tCH
tCL
SCLK
(output)
tDSP
CKE(1:0)
(output)
tDSP
Note 1
tDSN
ADD(24:10)
(output)
tDSN
RAS
(output)
tDSN
CAS,
SWR#
(output)
tDSP
Note 2
DQM
(output)
tDSP
Note 3
DATA
(output)
tSDS
tSDH
Note 3
DATA
(input)
Notes 1. The pins to which this signal applies differ depending on the state of the DBUS32 pin and the
EXT_ROMCS(1:0) bits of the BCUCNTREG3 register.
When DBUS32 = 0: CS(1:0)#, DQM(3:2)
When DBUS32 = 1 and EXT_ROMCS(1:0) = 11: CS(1:0)#
When DBUS32 = 1 and EXT_ROMCS(1:0) = 10: CS(1:0)#, CS2#/ROMCS2#
When DBUS32 = 1 and EXT_ROMCS(1:0) = 00: CS(1:0)#, CS(3:2)#/ROMCS(3:2)#
2. The pins to which this signal applies differ depending on the state of the DBUS32 pin.
When DBUS32 = 0: DQM (1:0)
When DBUS32 = 1: DQM (3:0)
3. The pins to which this signal applies differ depending on the state of the DBUS32 pin.
When DBUS32 = 0: DATA(15:0)
When DBUS32 = 1: DATA(15:0), DATA(31:16)/GPIO(31:16)
Remark The broken lines indicate high impedance.
52
Data Sheet U15585EJ1V0DS
µPD30122
(14) CSI (clocked serial interface) parameter
Parameter
Symbol
Condition
MIN.
Operating frequency
TYP.
MAX.
Unit
9.216
MHz
SECLK clock cycle time
tKCY1
108
ns
SECLK high-level width
tKH1
tKCY1/2 − 10
ns
SECLK low-level width
tKL1
tKCY1/2 − 10
ns
SECLK rise time
tR1
10
ns
SECLK fall time
tF1
10
ns
SIN input setup time (to SECLK ↑)
tSIK1
30
ns
SIN input hold time (from SECLK ↑)
tKSI1
20
ns
SOUT output delay time (from SECLK ↓)
tKSO1
20
ns
tKCY1
tKL1
tKH1
tR1
tF1
SECLK
(output)
tSIK1
SIN
(input)
Hi-Z
tKSI1
Input data
Hi-Z
tKSO1
SOUT
(output)
Output data
Data Sheet U15585EJ1V0DS
53
µPD30122
(15) PCI like bus interface parameter (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tSCLK
T×P
ns
tCLKH
(T × P/2) − 4
ns
tCLKL
(T × P/2) − 4
ns
tVAL
2
Delay time from floating to valid (from PCLK ↑)
tON
2
Output floating delay time (from PCLK ↑)
tOFF
Notes 1, 2
PCLK clock cycle
Notes 1, 2
PCLK high-level width
PCLK low-level widthNotes 1, 2
Output valid delay time (from PCLK ↑)
Note 3
Note 4
Note 4
Note 5
Data input setup time
Note 5
Data input hold time
20
ns
ns
28
ns
tSU
7
ns
tDH
0
ns
Notes 1. Applies to the PCLK pin.
2. The value of P is set by using the SEL_CLK(1:0) bits of the PCICLKSELREG register, and the value of
T is set by using the CLKSEL(2:0) signals (TxD/CLKSEL2, RTS#/CLKSEL1, DTR#/CLKSEL0) and the
VTDIV(2:0) bits of the PMUTCLKDIVREG register.
SEL_CLK(1:0)
P
11
RFU
10
1
01
4
00
2
VTDIV(2:0)
CLKSEL(2:0)
000
001
010
011
100
101
110
(Divided by 2) (Divided by 3) (Divided by 4) (Divided by 5) (Divided by 6)
111
111
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
110
RFU
RFU
RFU
16.6
22.1
27.6
33.2
RFU
101
RFU
RFU
RFU
18.2
24.3
30.4
RFU
RFU
100
33.2
RFU
RFU
19.9
26.6
33.2
RFU
RFU
011
31.0
RFU
15.5
23.3
31.0
RFU
RFU
RFU
010
29.9
RFU
19.9
29.9
RFU
RFU
RFU
RFU
001
33.2
RFU
22.1
33.2
RFU
RFU
RFU
RFU
000
38.2
RFU
25.5
38.2
RFU
RFU
RFU
RFU
3. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, TRDY#, GNT(2:0)#, and RST# pins.
4. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, and TRDY# pins.
5. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, TRDY#, and REQ(2:0)# pins.
54
Data Sheet U15585EJ1V0DS
µPD30122
(15) PCI like bus interface parameter (2/2)
tCLKH
tCLKL
tSCLK
PCLK
(output)
tVAL
Note 1
tOFF
Note 2
Note 2
tON
tSU
tDH
Note 3
Notes 1. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, TRDY#, GNT(2:0)#, and RST# pins.
2. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, and TRDY# pins.
3. Applies to the AD(31:0), CBE(3:0), DEVSEL#, FRAME#, IRDY#, LOCK#, PAR, PERR#, SERR#,
STOP#, TRDY#, and REQ(2:0)# pins.
Remark The broken lines indicate high impedance.
Load Coefficient (Delay Time per Load Capacitance)
Parameter
Symbol
Condition
Rating
MIN.
Load coefficient
CLD
Unit
MAX.
5
ns/20 pF
Caution Precision tests have not been performed. Only guaranteed as design characteristics.
Data Sheet U15585EJ1V0DS
55
µPD30122
3. PACKAGE DRAWING
224-PIN PLASTIC FBGA (16x16)
A
W
S B
B
B
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
C D
V U T R P NM L K J HG F E D C B A
P
Index mark
Q
W
S A
J
Y1
R
I
S
H
S
K
F
S
L
E
φM
M
G
S A B
ITEM
MILLIMETERS
A
16.00±0.10
B
15.4
C
15.4
D
16.00±0.10
E
1.20
F
0.8 (T.P.)
G
0.35±0.1
H
0.36
I
0.96
J
1.31±0.15
K
0.10
L
φ 0.50 +0.05
−0.10
M
0.08
P
C1.0
Q
R0.3
R
25°
W
0.20
Y1
0.20
S224S1-80-3C-2
56
Data Sheet U15585EJ1V0DS
µPD30122
4. RECOMMENDED SOLDERING CONDITIONS
The µPD30122 should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
µPD30122F1-150-GA1: 224-pin plastic FBGA (16 × 16)
µPD30122F1-180-GA1: 224-pin plastic FBGA (16 × 16)
Soldering
Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or
higher), Count: 2 times max., Exposure limit: 3 daysNote (after that, prebake at
125°C for 10 to 72 hours.)
IR30-103-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or
higher), Count: 2 times max. , Exposure limit: 3 daysNote (after that, prebake at
125°C for 10 to 72 hours.)
VP15-103-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U15585EJ1V0DS
57
µPD30122
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related documents
VRC4173 User’s Manual (U14579E)
µPD31173 (VRC4173) Data Sheet (U15338E)
Reference document
Electrical Characteristics for Microcomputer (U15170J)
Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
VR4100 Series, VR4120, VR4122, VRC4173, and VR Series are trademarks of NEC Corporation.
MIPS is a registered trademark of MIPS Technologies, Inc. in the United States.
58
Data Sheet U15585EJ1V0DS
µPD30122
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
NEC Electronics (Europe) GmbH Fax: 08-63 80 388
Duesseldorf, Germany
• United Kingdom Branch
Tel: 0211-65 03 01
Milton Keynes, UK
Fax: 0211-65 03 327
Tel: 01908-691-133
Fax: 01908-670-290
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
J02.4
Data Sheet U15585EJ1V0DS
59
µPD30122
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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M8E 00. 4