NEC UPD161643P

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD161643
176-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The µPD161643 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can
output a high gate scanning voltage in response to a CMOS-level input.
FEATURES
• High-withstanding-voltage output (VT-VEE = 42 V MAX.)
• 3.0 V CMOS level input
• Number of output: 176
ORDERING INFORMATION
★
Part number
Package
µPD161643P
Chip
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
S15796EJ1V0DS00 (1st edition)
Date Published February 2003 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
2001
µPD161643
1. BLOCK DIAGRAM
R,/L
CLK
STVSEL
STVR
SR1
SR87
SR2
SR88
SR89 SR90
SR175 SR176
STVL
MPX
OE1SEL
OE1
OE2SEL
OE2
VEE
VSS
VCC1
VT
Level Shifter
PVSS
PVCC1
VB
O1
Remark
2
O2
O87
O88
O89
/xxx indicates active low signal.
Data Sheet S15796EJ1V0DS
O90
O175
O176
µPD161643
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size: 2.3 x 7.05 mm
2
Bump size: INPUT/LEFT/RIGHT (include INPUT/OUTPUT/RIGHT side DUMMY): 49 x 85 µm
OUTPUT (include OUTPUT side DUMMY): 35 x 94 µm
No.94
2
2
No.95
Alignment mark 1
No.96
No.93
Face Up
Y
X
(0, 0)
No.1
No.283
Alignment mark 1
Alignment mark 2
No.285
No.284
Alignment mark 1
Alignment mark 2
30 µm 30 µm 30 µm
30 µm
10 µm 10 µm 10 µm
10 µm
30 µm
30 µm
Data Sheet S15796EJ1V0DS
10 µm
10 µm
3
µPD161643
Table 2−
−1. Pad Layout (1/4)
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
4
Gate Inputs 70 µ m pitch
Pad Name
X [mm]
Y [mm]
Alignment Mark1
-0.9995
-3.3745
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
PVCC1
OE1SEL
OE1SEL
PVSS
OE2SEL
OE2SEL
PVCC1
STVSEL
STVSEL
PVSS
R,/L
R,/L
PVCC1
DUMMY
DUMMY
VT
VT
VT
VT
VT
DUMMY
DUMMY
VCC1
VCC1
VCC1
VCC1
VCC1
DUMMY
DUMMY
VSS
VSS
VSS
VSS
VSS
DUMMY
DUMMY
VEE
VEE
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-3.2200
-3.1500
-3.0800
-3.0100
-2.9400
-2.8700
-2.8000
-2.7300
-2.6600
-2.5900
-2.5200
-2.4500
-2.3800
-2.3100
-2.2400
-2.1700
-2.1000
-2.0300
-1.9600
-1.8900
-1.8200
-1.7500
-1.6800
-1.6100
-1.5400
-1.4700
-1.4000
-1.3300
-1.2600
-1.1900
-1.1200
-1.0500
-0.9800
-0.9100
-0.8400
-0.7700
-0.7000
-0.6300
-0.5600
-0.4900
-0.4200
-0.3500
-0.2800
-0.2100
-0.1400
-0.0700
0.0000
0.0700
0.1400
0.2100
0.2800
0.3500
0.4200
0.4900
0.5600
0.6300
0.7000
0.7700
0.8400
0.9100
0.9800
1.0500
1.1200
1.1900
1.2600
Pad No.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
-
Data Sheet S15796EJ1V0DS
Gate Inputs 70 µ m pitch
Pad Name
X [mm]
Y [mm]
VEE
VEE
VEE
DUMMY
DUMMY
VB
VB
VB
VB
VB
DUMMY
DUMMY
STVR
STVR
DUMMY
STVL
STVL
DUMMY
CLK
CLK
DUMMY
OE1
OE1
DUMMY
OE2
OE2
DUMMY
DUMMY
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
-0.9995
1.3300
1.4000
1.4700
1.5400
1.6100
1.6800
1.7500
1.8200
1.8900
1.9600
2.0300
2.1000
2.1700
2.2400
2.3100
2.3800
2.4500
2.5200
2.5900
2.6600
2.7300
2.8000
2.8700
2.9400
3.0100
3.0800
3.1500
3.2200
Alignment Mark1
-0.9995
3.3745
µPD161643
Table 2−
−1. Pad Layout (2/4)
Pad No.
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Gate Outputs 35 µ m pitch
Pad Name
X [mm]
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
O176
O175
O174
O173
O172
O171
O170
O169
O168
O167
O166
O165
O164
O163
O162
O161
O160
O159
O158
O157
O156
O155
O154
O153
O152
O151
O150
O149
O148
O147
O146
O145
O144
O143
O142
O141
O140
O139
O138
O137
O136
O135
O134
O133
O132
O131
O130
O129
O128
O127
O126
O125
O124
O123
O122
O121
O120
O119
O118
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
Y [mm]
3.2725
3.2375
3.2025
3.1675
3.1325
3.0975
3.0625
3.0275
2.9925
2.9575
2.9225
2.8875
2.8525
2.8175
2.7825
2.7475
2.7125
2.6775
2.6425
2.6075
2.5725
2.5375
2.5025
2.4675
2.4325
2.3975
2.3625
2.3275
2.2925
2.2575
2.2225
2.1875
2.1525
2.1175
2.0825
2.0475
2.0125
1.9775
1.9425
1.9075
1.8725
1.8375
1.8025
1.7675
1.7325
1.6975
1.6625
1.6275
1.5925
1.5575
1.5225
1.4875
1.4525
1.4175
1.3825
1.3475
1.3125
1.2775
1.2425
1.2075
1.1725
1.1375
1.1025
1.0675
1.0325
Pad No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
Data Sheet S15796EJ1V0DS
Gate Outputs 35 µ m pitch
Pad Name
X [mm]
O117
O116
O115
O114
O113
O112
O111
O110
O109
O108
O107
O106
O105
O104
O103
O102
O101
O100
O99
O98
O97
O96
O95
O94
O93
O92
O91
O90
O89
O88
O87
O86
O85
O84
O83
O82
O81
O80
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
O63
O62
O61
O60
O59
O58
O57
O56
O55
O54
O53
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
Y [mm]
0.9975
0.9625
0.9275
0.8925
0.8575
0.8225
0.7875
0.7525
0.7175
0.6825
0.6475
0.6125
0.5775
0.5425
0.5075
0.4725
0.4375
0.4025
0.3675
0.3325
0.2975
0.2625
0.2275
0.1925
0.1575
0.1225
0.0875
0.0525
0.0175
-0.0175
-0.0525
-0.0875
-0.1225
-0.1575
-0.1925
-0.2275
-0.2625
-0.2975
-0.3325
-0.3675
-0.4025
-0.4375
-0.4725
-0.5075
-0.5425
-0.5775
-0.6125
-0.6475
-0.6825
-0.7175
-0.7525
-0.7875
-0.8225
-0.8575
-0.8925
-0.9275
-0.9625
-0.9975
-1.0325
-1.0675
-1.1025
-1.1375
-1.1725
-1.2075
-1.2425
5
µPD161643
Table 2−
−1. Pad Layout (3/4)
Pad No.
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
6
Gate Outputs 35 µ m pitch
Pad Name
X [mm]
O52
O51
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
0.8650
0.9950
Data Sheet S15796EJ1V0DS
Y [mm]
-1.2775
-1.3125
-1.3475
-1.3825
-1.4175
-1.4525
-1.4875
-1.5225
-1.5575
-1.5925
-1.6275
-1.6625
-1.6975
-1.7325
-1.7675
-1.8025
-1.8375
-1.8725
-1.9075
-1.9425
-1.9775
-2.0125
-2.0475
-2.0825
-2.1175
-2.1525
-2.1875
-2.2225
-2.2575
-2.2925
-2.3275
-2.3625
-2.3975
-2.4325
-2.4675
-2.5025
-2.5375
-2.5725
-2.6075
-2.6425
-2.6775
-2.7125
-2.7475
-2.7825
-2.8175
-2.8525
-2.8875
-2.9225
-2.9575
-2.9925
-3.0275
-3.0625
-3.0975
-3.1325
-3.1675
-3.2025
-3.2375
-3.2725
µPD161643
Table 2−
−1. Pad Layout (4/4)
Pad No.
94
95
Pad No.
-
Gate Left 600 µ m pitch
Pad Name
X [mm]
DUMMY
DUMMY
Pad Name
Alignment Mark2
Y [mm]
-0.3000
0.3000
3.3925
3.3925
X [mm]
0.9950
Y [mm]
-3.3925
Pad No.
284
285
Data Sheet S15796EJ1V0DS
Gate Right 600 µ m pitch
Pad Name
X [mm]
DUMMY
DUMMY
0.3000
-0.3000
Y [mm]
-3.3925
-3.3925
7
µPD161643
3. PIN FUNCTIONS
(1/2)
Symbol
O1 to O176
Pin Name
Driver output
Pad No.
277 to 102
I/O
Output
Function
Scan signal output pins that drive the gate electrode of a TFTLCD. The status of each output pin changes in synchronization
with the rising edge of shift clock. The output voltage of the driver
is VT-VB.
STVR,
Start pulse input/output
STVL
78, 79,
I/O
81, 82
Input/output pin of the internal shift register.
Read of start pulse signal is set at rising (or falling) edge of shift
clock, and outputs a scanning signal from a driver output pin. In
addition, the effective level of a STVR/STVL pin is determined
by setup of STVSEL pin. Moreover, an input/output level is VCC1VSS (logic level).
STVSEL = L: Start pulse is set to low level by the 176th falling
edge of shift clock, and is set to a high level by the 177th falling
edge.
STVSEL
Start pulse input
35, 36
Input
effective level selection
The effective level of the start pulse signal inputted into
STVR/STVL is selected.
STVSEL = L: Low level
STVSEL = H: High level
CLK
Shift clock input
84, 85
Input
Shift clock input for the internal shift register. The contents of
internal shift register is shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
R,/L
Shift direction
38, 39
Input
Shift direction switching input pin of the internal shift register.
R,/L = H (right shift): STVR → O1 → O2 ··· O175 → O176 → STVL
switching input
R,/L = L (left shift): STVL → O176 → O175 ··· O2 → O1 → STVR
OE1
Enable input
87, 88
Input
Input of the level selected by OE1SEL fixes a driver output to a
low level (input of a low level fixes driver output to low level at
the time of OE1SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE1 pin of sauce driver.
OE1SEL
OE1 effective level
29, 30
Input
selection
This pin selects effective level of OE1 pin.
OE1SEL = L: Low level
OE1SEL = H: High level
OE2
Enable input
90, 91
Input
Input of the level selected by OE2SEL fixes a driver output to a
high level (input of a low level fixes driver output to high level at
the time of OE2SEL = L). However, shift register is not cleared.
Moreover, output enable operation is asynchronous on a clock.
Connect with GOE2 pin of sauce driver.
OE2SEL
OE2 effective level
selection
32, 33
Input
This pin selects effective level of OE2 pin.
OE2SEL = L: Low level
OE2SEL = H: High level
8
Data Sheet S15796EJ1V0DS
µPD161643
(2/2)
Symbol
VT
Name
Positive power
Pad No.
43 to 47
I/O
−
supply for driver
VEE
Negative power
Function
Positive power supply for level shifter and output buffer.
Positive power supply for Liquid crystal.
64 to 68
−
Negative power supply for level shifter.
71 to 75
−
Negative power supply for output buffer.
50 to 54
−
Positive power supply for logic circuit.
supply for logic
VB
Negative power
supply for driver
VCC1
Positive power
Negative power supply for Liquid crystal.
supply for logic
VSS
Ground
57 to 61
−
Connect to the system ground.
PVCC1
Pull-up power
28, 34, 40
−
Pull-up power supply for mode setting pins (R,/L, STVSEL,
31, 37
−
supply
PVSS
OE1SEL, OE2SEL).
Pull-down power
supply
Pull-down power supply for mode setting pins (R,/L, STVSEL,
OE1SEL, OE2SEL).
4. MODE DESCRIPTION
Output Mode Selection
R,/L
STVR
STVL
Scan Direction
H
Input
Output
1 → 176
L
Output
Input
176 → 1
Remark H: VCC1, L: VSS
Data Sheet S15796EJ1V0DS
9
µPD161643
5. TIMING CHART
The timing chart in each condition is shown as follows.
R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L
1
2
3
4
176
177
178
179
180
181
4
176
177
178
179
180
181
CLK
OE1
OE2
STVR
O1
O2
O3
O 176
STVL
(O 1 )
(O 2 )
(O 3 )
R,/L = L, STVSEL = H, OE1SEL = H, OE2SEL = H
1
2
3
CLK
OE1
OE2
STVL
O 176
O 175
O 174
O1
STVR
(O 176 )
(O 175 )
(O 174 )
10
Data Sheet S15796EJ1V0DS
µPD161643
R,/L = H, STVSEL = H, OE1SEL = L, OE2SEL = H
1
2
3
4
176
177
178
179
180
181
4
176
177
178
179
180
181
CLK
OE1
OE2
STVR
O1
O2
O3
O 176
STVL
(O 1 )
(O 2 )
(O 3 )
R,/L = L, STVSEL = H, OE1SEL = H, OE2SEL = L
1
2
3
CLK
OE1
OE2
STVL
O 176
O 175
O 174
O1
STVR
(O 176 )
(O 175 )
(O 174 )
Data Sheet S15796EJ1V0DS
11
µPD161643
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Rating
Unit
Supply Voltage
Parameter
VT
–0.5 to +30
V
Supply Voltage
VCC1
–0.5 to +6.5
V
Supply Voltage
VT-VEE
–0.5 to +45
V
Supply Voltage
VEE
−25 to +0.5
V
Supply Voltage
VB
VEE − 0.5 to +0.5
V
Note
Symbol
VI
−0.5 to VCC1 + 0.5
V
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature
Tstg
−55 to +150
°C
Input Voltage
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = –40 to +85°°C, VSS = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply Voltage
VT
10
15
25
V
Supply Voltage
VEE
–20
–15
–10
V
Supply Voltage
VB
VEE
–15
–6.5
V
Supply Voltage
VT-VEE
20
30
42
V
Supply Voltage
VCC1
2.5
3.0
3.6
V
VCC1
V
Input Voltage
Note
VI
0
Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL
12
Data Sheet S15796EJ1V0DS
µPD161643
Electrical Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)
Parameter
High Level Input Voltage
Symbol
Condition
MAX.
Unit
0.8 VCC1
MIN.
TYP.
VCC1
V
0
0.2 VCC1
V
VCC1 – 0.4
VCC1
V
VIH1
R,/L, CLK, STVR, STVL, OE1, OE2,
Low Level Input Voltage
VIL1
STVSEL, OE1SEL, OE2SEL
High Level Output Voltage
VOH
STVR, STVL, IOH = –40 µA
Low Level Output Voltage
VOL
STVR, STVL, IOH = +40 µA
0
0.4
V
Output ON Resistance
RON1
O1 to O176, VOUT = VT − 0.5 V
5.0
7.5
kΩ
RON2
O1 to O176, VOUT = VEE + 0.5 V
5.0
7.5
kΩ
Input Current
II1
Logic input pin
±1.0
µA
Dynamic Current 1
ICC1
VCC1, Note
200
µA
Dynamic Current 2
IT
VT, Note
100
µA
Dynamic Current 3
IEE
VEE, Note
100
µA
ISS
VCC1, VT in stand-by mode
10
µA
Static Current
Note
Note fCLK = 20 kHz, frame frequency = 60 Hz, output no load
Switching Characteristics (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)
Parameter
Cascade Output Delay Time
MIN.
TYP.
MAX.
Unit
tPHL1
CL = 20 pF,
800
ns
CLK → STVL (STVR)
800
ns
tPHL2
CL = 50 pF,
1.5
µs
tPLH2
CLK → On
1.5
µs
tPHL3
CL = 50 pF,
1.5
µs
tPLH3
OE1 → On
1.5
µs
tPHL4
CL = 50 pF,
1.5
µs
tPLH4
OE2 → On
1.5
µs
Output Rise Time
tTLH
CL = 50 pF
1.5
µs
Output Fall Time
tTHL
1.5
µs
Driver Output Delay Time 1
★
Driver Output Delay Time2
★
Condition
tPLH1
★
★
Symbol
Driver Output Delay Time 3
Input Capacitance
CI
TA = 25°C
Clock Frequency
fCLK
When connected in cascade
15
pF
100
kHz
MAX.
Unit
20
Timing Requirement (TA = −40 to +85°°C, VCC1 = 2.5 to 3.6 V, VT = 15 V, VEE = VB = −15 V, VSS = 0 V)
Parameter
Symbol
Condition
Clock Pulse High Period
PW CLK(H)
Clock Pulse Low Period
PW CLK(L)
Enable Pulse High Period
PW OE
OE1, OE2
Data Setup Time
tSETUP
Data Hold Time
tHOLD
Remark
MIN.
TYP.
500
ns
500
ns
1
µs
STVR (STVL) ↓ → CLK ↑
200
ns
CLK ↑ → STVR (STVL) ↑
200
ns
The rise and fall times of logic input must be tr = tf = 20 ns (10 to 90%)
Data Sheet S15796EJ1V0DS
13
µPD161643
★ Switching Characteristics Waveform (R,/L = H, STVSEL = L, OE1SEL = L, OE2SEL = L)
( ): R,/L = L
1/fCLK
PWCLK(H)
PWCLK(L)
VCC1
CLK
50%
50%
50%
50%
VSS
tSETUP
tHOLD
VCC1
STVR
(STVL)
50%
50%
VSS
tPHL1
tPLH1
VCC1
STVL
(STVR)
50%
50%
VSS
tPLH2
tTLH
tPHL2
90%
tTHL
VT
90%
On
10%
10%
VB
PWOE
VCC1
OE1
50%
50%
VSS
tPHL3
tPLH3
VT
90%
On
10%
VB
PWOE
VCC1
OE2
50%
50%
VSS
tPLH4
tPHL4
VT
90%
On
10%
VB
14
Data Sheet S15796EJ1V0DS
µPD161643
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15796EJ1V0DS
15