VISHAY DG458AZ/883

DG458/459
Vishay Siliconix
Fault-Protected Single 8-Ch/Differential 4-Ch Analog Multiplexers
Fault and Overvoltage Protection
All Channels Off When Power Off
Latchup-Proof
Fast Switching—TA: 200 ns
Break-Before-Make Switching
Low On-Resistance: 180 Low Power Consumption: 3 mW
TTL and CMOS Compatible Inputs
Improved Ruggedness
Power Loss Protection
Prevents Adjacent Channel Crosstalk
Standard Logic Interface
Superior Accuracy
Fast Settling Time
Data Acquisition Systems
Industrial Process Control Systems
Avionics Test Equipment
High-Rel Control Systems
Telemetry
The DG458 and DG459 are 8-channel single-ended and
4-channel differential analog multiplexers, respectively,
incorporating fault protection. A series n-p-n MOSFET
structure provides device and signal-source protection in the
event of power loss or overvoltages. Under fault conditions the
multiplexer input (or output) appears as an open circuit and
only a few nanoamperes of leakage current will flow. This
protects not only the multiplexer and the circuitry following it,
but also protects the sensors or signal sources which drive the
multiplexer.
The DG458 and DG459 can withstand continuous overvoltage
inputs up to 35 V. All digital inputs have TTL compatible logic
thresholds. Break-before-make operation prevents channelto-channel interference.
The DG458 and DG459 are improved pin-compatible
replacements for HI-508A/509A and MAX358/359
multiplexers.
DG458
DG459
Dual-In-Line
Dual-In-Line
A0
EN
V–
S1
S2
S3
S4
D
16
1
2
Decoders/Drivers
15
3
14
4
13
5
12
6
11
7
10
8
9
Top View
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
A1
A0
A2
EN
GND
V–
V+
S1a
S5
S2a
S6
S3a
S7
S4a
S8
Da
16
1
2
Decoders/Drivers
15
3
14
4
13
5
12
6
11
7
10
8
9
A1
GND
V+
S1b
S2b
S3b
S4b
Db
Top View
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DG458/459
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE Ċ DG458
TRUTH TABLE Ċ DG459
A2
A1
A0
EN
On Switch
A1
A0
EN
On Switch
X
X
X
0
None
X
X
0
None
0
0
0
1
1
0
0
1
1
0
0
1
1
2
0
1
1
2
0
1
0
1
3
1
0
1
3
0
1
1
1
4
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
Logic “0” = VAL v 0.8 V
Logic “1” = VAH w 2.4 V
X = Don’t Care
ORDERING INFORMATION
Temp Range
Package
–40 to 85_C
16-Pin Plastic DIP
Part Number
DG458DJ
DG459DJ
DG458AK/883
16-Pin CerDIP
DG459AK/883
–55
55 to 125
125_C
C
DG458AZ/883
LCC-20
DG459AZ/883
*Block Diagram and Pin Configuration not shown.
ABSOLUTE MAXIMUM RATINGS
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V
V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
VEN, VA Digital Input . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –4 V to (V+) +4 V
VS, Analog Input Overvoltage
with Power On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –20 V to (V+) +20 V
VS, Analog Input Overvoltage
with Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35 V to +35 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
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Storage Temperature
(AK Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C
(DJ Suffix) . . . . . . . . . . . . . . . . . . –65 to 125_C
Power Dissipation (Package)a
16-Pin Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW
16-Pin CerDIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
LCC-20d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Notes:
a. All leads soldered or welded to PC board.
b. Derate 6.3 mW/_C above 25_C.
c. Derate 12 mW/_C above 75_C.
d. Derate 10 mW/_C above 75_C.
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
DG458/459
Vishay Siliconix
Test Conditions
Unless Otherwise Specified
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
V+ = 15 V, V– = –15 V
VAL = 0.8 V, VAH = 2.4 Vf
Tempb
VANALOG
Full
VD = "9.5 V, IS = –400 mA
0.45
rDS(on)
Room
Full
1.2
1.5
VD = "5 V, IS = –400 mA
Room
180
400
400
W
DrDS(on)
VD = 0 V, IS = –400 mA
Room
6
IS(off)
VEN = 0 V
VS = "10 V, VD = #10 V
Room
Full
0.03
–0.5
–50
0.5
50
–1
–20
1
20
DG458
ID(off)
VEN = 0 V
VD = "10 V
VS = #10 V
Room
Full
0.1
Drain Off
L k
Leakage
Current
C
t
–1
–200
1
200
–1
–50
1
50
DG459
Room
Full
0.1
–1
–100
1
100
–2
–25
2
25
Differential Off Drain
Leakage Current
IDIFF
–50
50
–20
20
Drain On
Leakage
Current
L k
C
t
ID(on)
Parameter
Symbol
Typc
Mind
Maxd Mind
Maxd
Unit
10
V
1.5
1.8
kW
Analog Switch
Analog Signal Rangeg
Drain-Source
On-Resistance
rDS(on) Matching Between
Channelsh
Source Off
Leakage Current
DG459 Only
–10
Room
10
–10
%
DG458
Room
Full
0.1
–2
–200
2
200
–5
–50
5
50
DG459
Room
Full
0.05
–2
–100
2
100
–5
–25
5
25
VS = "33 V, VD = 0 V
See Figure 2
Room
0.02
VS = "25 V, VD = "10 V,
See Figure 2
Room
0.005
–5
5
–10
10
VS = "25 V, VSUPS = 0 V
VD = A0, A1, A2, EN = 0 V
Room
0.001
–2
2
–5
5
VS = VD = "10 V
A
nA
Fault
Output Leakage Current
(with Overvoltage)
Input Leakage Current
(with Overvoltage)
Input Leakage Current
(with Power Supplies Off)
ID(off)
IS(off)
nA
mA
Digital Control
Input Low Threshold
VAL
Full
Input Low Threshold
VAL
Full
2.4
–1
Logic Input Control
IA
VA = 2.4 V or 0.8 V
Full
0.8
0.8
2.4
1
–1
1
V
mA
Dynamic Characteristics
Transition Time
tA
See Figure 3
Room
200
Break-Before-Make Time
tOPEN
See Figure 4
Room
45
Enable Turn-On Time
tON(EN)
Room
Full
140
250
500
250
500
Room
Full
50
250
500
250
500
See Figure 5
Enable Turn-Off Time
tOFF(EN)
To 0.1 %
Room
0.5
To 0.01%
Room
1.5
OIRR
VEN = 0 V, RL = 1 kW , CL = 15 pF VS =
3 VRMS, f = 100 kHz
Room
90
Logic Input Capacitance
Cin
f = 1 MHz
Room
5
Source Off Capacitance
CS(off)
Settling Time
ts
Off Isolation
Drain Off Capacitance
CD(off)
Drain On Capacitance
CD(on)
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
Room
5
DG458
Room
15
DG459
Room
10
DG458
Room
40
DG459
Room
35
500
10
500
10
ns
ms
dB
pF
F
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DG458/459
Vishay Siliconix
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified
Parameter
V+ = 15 V, V– = –15 V
VAL = 0.8 V, VAH = 2.4 Vf
Symbol
Tempb
Typc
Room
Full
0.05
Room
Full
–0.01
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
Mind
Maxd Mind
Maxd
Unit
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I–
VEN = 5.0 or 0 V, VA = 0 V
Power Supply Range for
Continuous Operation
Room
0.1
0.2
–0.1
–0.2
0.1
0.2
mA
–0.1
–0.2
"4.5
"18
"4.5
"18
V
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f.
VIN = input voltage to perform proper function.
g. When the analog signal exceeds the +13.5 V or –12 V, rDS(on) starts to rise until only leakage currents flow.
r DS(on) MAX – r DS(on) MIN
h. Dr
+
x 100%
DS(on)
r
AVE
ǒ
Ǔ
DS(on)
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Input Leakage vs. Input Voltage
Off-Channel Leakage Currents vs. Input Voltage
1 mA
1 mA
10 mA
10 mA
1 mA
1 mA
100 nA
10 nA
Operating Range
1 nA
10 nA
Operating Range
1 nA
100 pA
10 pA
10 pA
0
10
20
VS – Source Voltage (V)
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100 nA
100 pA
1 pA
–50 –40 –30 –20 –10
30
V+ = 15 V
V– = –15 V
100 mA
V+ = V– = 0 V
I S –Source Current
I S –Source Current
100 mA
40
50
1 pA
–50 –40 –30 –20 –10
0
10
20
30
40
50
VS – Source Voltage (V)
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
DG458/459
Vishay Siliconix
_ Output Leakage vs. Off-Channel Overvoltage
rDS(on) vs. Input Voltage
1 nA
r DS(on)– Drain-Source On-Resistance ( )
2000
V+ = 15 V
V– = –15 V
I D – Drain Current
100 pA
10 pA
1 pA
0.1 pA
–50 –40 –30 –20 –10
0
10
20
30
40
1600
5 V
Supplies
1200
10 V
800
15 V
400
20 V
0
–20
50
–15
–10
VS – Source Voltage (V)
15
20
25
12
15
Leakage Current vs. VS, VD
V+ = 15 V
V– = –15 V
V+ = 15 V
V– = –15 V
20
IS(off)
15
500
25_C
400
85_C
125_C
0_C
300
200
10
ID(off)
5
0
–5
ID(on)
–10
–15
100
–55_C
–20
0
–25
–10 –7.5
–5.0
–2.5
0
2.5
5.0
7.5
10
–15 –12 –9
–6
–3
0
3
6
9
VD – Drain Voltage (V)
VD or VS – Drain or Source Voltage (V)
Leakage Currents vs. Temperature
Switching Times (tTRANS, tON, tOFF)
vs. VSUPPLIES
240
10
V+ = 15 V
V– = –15 V
VS, VD = 10 V
tTRANS
ID(on)
200
1
Time (ns)
I S, I D (nA)
10
25
I S, I D – Leakage (pA)
r DS(on)– Drain-Source On-Resistance ( )
600
5
VS – Source Voltage (V)
rDS(on) vs. VD and Temperature
700
0
–5
ID(off)
IS(off)
160
tON(EN)
120
VIN = 2 V
0.10
80
tOFF(EN)
40
0.01
–55 –35 –15
5
25
45
65
Temperature (_C)
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
85
105
125
5
10
15
20
V+, V– Positive and Negative Supplies (V)
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DG458/459
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Temperature
QINJ vs. VS
280
0
V+ = 15 V
V– = –15 V
240
Charge Injection (pC)
tTRANS
200
Time (ns)
V+ = 15 V
V– = –15 V
–10
tON(EN)
160
120
tOPEN
80
–30
CL = 1 nF
–40
–50
tOFF(EN)
40
–20
0
CL = 10 nF
–60
–55 –35 –15
5
25
45
65
85
105
–10
125
–5
Temperature (_C)
10
Logic Input Switching Threshold vs. VSUPPLIES
3.0
V+ = 15 V
V– = –15 V
RL = 1 k
–100
2.5
2.0
V TH (V)
–90
(dB)
5
VS – Source Voltage (V)
Off Isolation and XTALK vs. Frequency
–110
0
–80
Off Isolation
Crosstalk
–70
1.5
1.0
–60
0.5
–50
0
10 k
100 k
1M
10 M
2.5
5
7.5
10
f – Frequency (Hz)
12.5
15
17.5
20
V+, Supply (V)
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
GND
V–
VREF
D
V+
A0
V–
V+
Level
Shift
AX
Decode/
Drive
S1
V–
V+
EN
Sn
V–
FIGURE 1.
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Document Number: 70064
S-52433—Rev. F, 06-Sep-99
DG458/459
Vishay Siliconix
+15 V
V+
IS(off)
"VS
ID(off)
Sn
A
D
A
VD
V–
–15 V
FIGURE 2. Analog Input Overvoltage
+15 V
+2.4 V
V+
EN
S1b
50%
*
A2
A1
3V
Logic
Input
"5 V
DG458
0V
S8b
A0
#5 V
Db
GND
VO
+5 V
Switch
Output
VO
V–
50 1 M
90%
–5 V
35 pF
tA
–15 V
* = S1a – S8a, S2b – S7b, Da
FIGURE 3. Transition Time
+15 V
+2.4 V
EN
V+
S1 , S8
Logic
Input
+5 V
3V
0V
S2 – S7
A0
DG458
A1
A2
Db, D
GND
50 VO
V–
–15 V
Switch
Output
50%
VO
1 k
35 pF
0V
tOPEN
FIGURE 4. Break-Before-Make Time
Document Number: 70064
S-52433—Rev. F, 06-Sep-99
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DG458/459
Vishay Siliconix
+15 V
V+
S1
3V
Enable
Input
+5 V
EN
50%
0V
S2 – S8
A0
VS
DG458
A1
A2
GND
V–
50 Switch
Output
D
1 k
VO
90%
VO
0V
tON(EN)
35 pF
tOFF(EN
–15 V
FIGURE 5. Enable Delay
The Vishay Siliconix DG458 and DG459 multiplexers are fully
fault- and overvoltage-protected for continuous input voltages
up to 35 V whether or not voltage is applied to the power
supply pins (V+, V–). These multiplexers are built on a
high-voltage junction-isolated silicon-gate CMOS process.
Two n-channel and one p-channel MOSFETs are connected
in series to form each channel (Figure 1).
–35 V
Overvoltage
n-Channel
MOSFET
is On
Q1 –35 V
S
D
G
Q2
S
D
G
Q3
S
D
+35 V
Overvoltage
n-Channel
MOSFET
is Off
G
p-Channel
MOSFET
is Off
Within the normal analog signal range (10 V), the rDS(on)
variation as a function of analog signal voltage is comparable
to that of the classic parallel N-MOS and P-MOS switches.
(a) Overvoltage with Multiplexer Power Off
–15 V
When the analog signal approaches or exceeds either supply
rail, even for an on-channel, one of the three series MOSFETs
gets cut-off, providing inherent protection against
overvoltages even if the multiplexer power supply voltages are
lost. This protection is good up to the breakdown voltage of the
respective series MOSFETs. Under fault conditions only sub
microamp leakage currents can flow in or out of the multiplexer.
This not only provides protection for the multiplexer and
succeeding circuitry, but it allows normal, undisturbed
operation of all other channels. Additionally, in case of power
loss to the multiplexer, the loading caused on the transducers
and signal sources is insignificant, therefore redundant
multiplexers can be used on critical applications such as
telemetry and avionics.
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Q1
–35 V
Overvoltage
n-Channel
MOSFET
is On
+15 V
–15 V
Q2
+15 V
–15 V
Q3
+35 V
Overvoltage
n-Channel
MOSFET
is Off
p-Channel
MOSFET
is Off
(b) Overvoltage with Multiplexer Power On
FIGURE 6. Overvoltage Protection
Document Number: 70064
S-52433—Rev. F, 06-Sep-99