DG406/407 Vishay Siliconix 16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers Low On-Resistance—rDS(on): 50 Low Charge Injection—Q: 15 pC Fast Transition Time—tTRANS: 200 ns Low Power: 0.2 mW Single Supply Capability 44-V Supply Max Rating Higher Accuracy Reduced Glitching Improved Data Throughput Reduced Power Consumption Increased Ruggedness Wide Supply Ranges: 5 V to 20 V Data Acquisition Systems Audio Signal Routing Medical Instrumentation ATE Systems Battery Powered Systems High-Rel Systems Single Supply Systems The DG406 is a 16-channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. The DG407 selects one of eight differential inputs to a common differential output. Break-before-make switching action protects against momentary shorting of inputs. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. Applications for the DG406/407 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. For additional application information order Faxback document numbers 70601 and 70604. Designed in the 44-V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 volts, allowing operation with 20-V supplies. Additionally single (12-V) supply operation is allowed. An epitaxial layer prevents latchup. For applications information please request FaxBack documents 70601 and 70604. DG406 DG407 Dual-In-Line and SOIC Wide-Body V+ NC 1 2 Dual-In-Line and SOIC Wide-Body 28 D V+ 1 28 Da 27 V– Db 2 27 V– NC 3 26 S8a NC 3 26 S8 S16 4 25 S7 S8b 4 25 S7a S7b 5 24 S6a S15 5 24 S6 S14 6 23 S5 S6b 6 23 S5a S5b 7 22 S4a S13 7 22 S4 S12 8 21 S3 S4b 8 21 S3a S3b 9 20 S2a S11 9 20 S2 S10 10 19 S1 S2b 10 19 S1a 18 EN S1b 11 18 EN 17 A0 GND 12 NC NC S9 11 GND 12 Decoders/Drivers NC 13 16 A1 A3 14 15 A2 Top View Document Number: 70061 S-00399—Rev. H, 13-Sep-99 17 A0 13 16 A1 14 15 A2 Decoders/Drivers Top View www.vishay.com FaxBack 408-970-5600 5-1 DG406/407 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Da S 8a V+ D 28 27 26 Db V+ 1 NC NC 2 S 8b NC 3 S8 S 16 4 V– PLCC and LCC DG407 4 3 2 1 28 27 26 V– PLCC and LCC DG406 S15 5 25 S7 S7b 5 25 S7a S14 6 24 S6 S6b 6 24 S6a S5b 7 23 S5a S13 7 23 S5 S12 8 22 S4 S4b 8 22 S4a S11 9 21 S3 S3b 9 21 S3a S10 10 20 S2 S2b 10 20 S2a S9 11 19 S1 S1b 11 19 S1a EN A0 A1 A2 NC NC GND EN A0 NC A1 12 13 14 15 16 17 18 A2 12 13 14 15 16 17 18 A3 Decoders/Drivers GND Decoders/Drivers Top View Top View TRUTH TABLE Ċ DG406 TRUTH TABLE Ċ DG407 A3 A2 A1 A0 EN On Switch A2 A1 A0 EN On Switch Pair X X X X 0 None X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 2 0 0 1 1 2 0 0 1 0 1 3 0 1 0 1 3 0 0 1 1 1 4 0 1 1 1 4 0 1 0 0 1 5 1 0 0 1 5 0 1 0 1 1 6 1 0 1 1 6 0 1 1 0 1 7 1 1 0 1 7 0 1 1 1 1 8 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 ORDERING INFORMATION Ċ DG406 Temp Range –40 40 to 85_C 85 C Package DG406DJ 28-Pin PLCC DG406DN 28-Pin Widebody SOIC DG406DW 28-Pin CerDIP DG406AK/883, 5962-9562301QXA LCC-28 DG406AZ/883, 5962-9562301Q3A –55 to 125_C www.vishay.com S FaxBack 408-970-5600 5-2 Part Number 28-Pin Plastic DIP Logic “0” = 1 = Logic “1” X = Don’t Care VAL v 0.8 V VAH w 2.4 V ORDERING INFORMATION Ċ DG407 Temp Range –40 40 to 85_C 85 C Package Part Number 28-Pin Plastic DIP DG407DJ 28-Pin PLCC DG407DN 28-Pin Widebody SOIC DG407DW 28-Pin CerDIP DG407AK/883’ 5962-9562302QXA LCC-28 DG407AZ/883 5962-9562302Q3A –55 to 125_C Document Number: 70061 S-00399—Rev. H, 13-Sep-99 DG406/407 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Power Dissipation (Package)b 28-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW 28-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W 28-Pin Plastic PLCCc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW LCC-28e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.35 W 28-Pin Widebody SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Voltages Referenced to V– V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or 20 mA, whichever occurs first Notes: a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6 mW/_C above 75_C d. Derate 12 mW/_C above 75_C e. Derate 13.5 mW/_C above 75_C Current (Any Terminal,) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AK, AZ Suffix) . . . . . . . . . . . . . . –65 to 150_C (DJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter A Suffix D Suffix –55 to 125_C –40 to 85_C V+ = 15 V, V– = –15 V VAL = 0.8 V, VAH = 2.4 Vf Tempb rDS(on) VD = "10 V, IS = –10 mA Sequence Each Switch On Room Full 50 DrDS(on) VD = "10 V Room 5 Room Full 0.01 –0.5 –50 0.5 50 –0.5 –5 0.5 5 DG406 Room Full 0.04 –1 –200 1 200 –1 –40 1 40 DG407 Room Full 0.04 –1 –100 1 100 –1 –20 1 20 DG406 Room Full 0.04 –1 –200 1 200 –1 –40 1 40 DG407 Room Full 0.04 –1 –100 1 100 –1 –20 1 20 Symbol Typc Mind Maxd Mind 15 –15 Maxd Unit Analog Switch Analog Signal Rangee VANALOG Drain-Source On-Resistance rDS(on) Matching Between Channelsg Source Off Leakage Current Drain Off Leakage Current L k C t Drain On L k Leakage Current C t Full IS(off) ID(off) ID(on) VEN = 0 V VD = "10 V VS = #10 V VS = VD = "10 V Sequence Each Switch On –15 100 125 15 V 100 125 W % nA A Digital Control Logic High Input Voltage VINH Full Logic Low Input Voltage VINL Full 2.4 2.4 Logic High Input Current IAH VA = 2.4 V, 15 V Full –1 1 –1 1 Logic Low Input Current IAL VEN = 0 V, 2.4 V, VA = 0 V Full –1 1 –1 1 Logic Input Capacitance Cin f = 1 MHz Room 7 Transition Time tTRANS See Figure 2 Room Full 200 Break-Before-Make Interval tOPEN See Figure 4 Room Full 50 Enable Turn-On Time tON(EN) Room Full 150 200 400 200 400 Enable Turn-Off Time tOFF(EN) Room Full 70 150 300 150 300 0.8 0.8 V mA pF Dynamic Characteristics See Figure 3 350 450 25 10 350 450 25 10 ns Q CL = 1 nF, VS = 0 V, Rs = 0 W Room 15 pC Off Isolationh OIRR VEN = 0 V, RL = 1 kW f = 100 kHz Room –69 dB Source Off Capacitance CS(off) VEN = 0 V, VS = 0 V, f = 1 MHz Room 8 Drain Off Capacitance CD(off) Room 130 Charge Injection VEN = 0 V, V, VD = 0 V f = 1 MHz MH Drain On Capacitance Document Number: 70061 S-00399—Rev. H, 13-Sep-99 CD(on) DG407 Room 65 DG406 Room 140 DG407 Room 70 pF F www.vishay.com S FaxBack 408-970-5600 5-3 DG406/407 Vishay Siliconix Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, V– = –15 V VAL = 0.8 V, VAH = 2.4 Vf Tempb Typc Room Full 13 A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit Power Supplies Positive Supply Current I+ Negative Supply Current I– Room Full –0.01 Positive Supply Current I+ Room Full 50 Negative Supply Current I– Room Full –0.01 VEN = VA = 0 or 5 V VEN = 2.4 V, VA = 0 V 30 75 –1 –10 30 75 –1 –10 500 900 –20 –20 500 700 mA A –20 –20 Test Conditions Unless Otherwise Specified Parameter Symbol V = 12 V V+ V, V V– = 0 V VAL = 0.8 V, VAH = 2.4 Vf Tempb Typc A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit 0 12 V 120 W Analog Switch Analog Signal Rangee Drain-Source On-Resistance rDS(on) Matching Between Channelsg VANALOG rDS(on) DrDS(on) Full Room 90 Room 5 Room 0.01 DG406 Room 0.04 DG407 Room 0.04 DG406 Room 0.04 DG407 Room 0.04 VD = 3 V,, 10 V,, IS = – 1 mA S Sequence E h Switch Each S it h On O Source Off Leakage Current IS(off) Drain Off L k Leakage Current C t ID(off) VEN = 0 V VD = 10 V or 0.5 05V VS = 0.5 V or 10 V Drain On L k Leakage Current C t ID(on) VS = VD = 10 V Sequence Each S E h Switch S it h On O 0 12 120 % nA A Dynamic Characteristics Switching Time of Multiplexer tTRANS VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V Room 300 450 450 Enable Turn-On Time tON(EN) Room 250 600 600 Enable Turn-Off Time tOFF(EN) VINH = 2.4 V,, VINL = 0 V VS1 = 5 V Room 150 300 300 Q CL = 1 nF, VS= 6 V, RS = 0 Room 20 Room Full 13 Room Full –0.01 Charge Injection ns pC Power Supplies Positive Supply Current I+ Negative Supply Current I– VEN = 0 V or 5 V V, VA = 0 V or 5 V 30 75 –20 –20 30 75 –20 –20 mA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. DrDS(on) = rDS(on) MAX – rDS(on) MIN. h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin. www.vishay.com S FaxBack 408-970-5600 5-4 Document Number: 70061 S-00399—Rev. H, 13-Sep-99 DG406/407 Vishay Siliconix _ rDS(on) vs. VD and Supply rDS(on) vs. VD and Temperature 160 80 120 r DS(on)– On-Resistance ( ) r DS(on)– On-Resistance ( ) 70 5 V 80 8 V 10 V 12 V 15 V 40 20 V 125_C 60 85_C 50 25_C 0_C 40 30 –40_C 20 –55_C 10 0 –15 0 –20 –12 –4 4 VD – Drain Voltage (V) 12 V+ = 15 V V– = –15 V 20 –10 –5 0 5 VD – Drain Voltage (V) 10 15 ID , IS Leakage Currents vs. Analog Voltage rDS(on) vs. VD and Supply 120 V+ = 7.5 V 80 200 I D, I S – Current (pA) r DS(on)– On-Resistance ( ) V+ = 15 V V– = –15 V VS = –VD for ID(off) VD = VS(open) for ID(on) V– = 0 V 240 160 10 V 120 12 V 15 V 80 20 V 22 V 40 IS(off) 0 DG406 ID(on), ID(off) –40 DG407 ID(on), ID(off) –80 40 –120 –15 0 0 4 8 12 VD – Drain Voltage (V) 16 20 ID , IS Leakages vs. Temperature 15 350 V+ = 15 V V– = –15 V VD = ”14 V 300 tTRANS 250 1 nA ID(on), ID(off) Time (ns) I D, I S – Current –5 0 5 10 VS , VD – Source Drain Voltage (V) Switching Times vs. Bipolar Supplies 100 nA 10 nA –10 100 pA 200 tON(EN) 150 IS(off) 10 pA 100 tOFF(EN) 1 pA 0.1 pA –55 50 0 –35 –15 5 25 45 65 Temperature (_C) Document Number: 70061 S-00399—Rev. H, 13-Sep-99 85 105 125 5 10 15 20 VSUPPLY – Supply Voltage (V) www.vishay.com S FaxBack 408-970-5600 5-5 DG406/407 Vishay Siliconix _ Switching Times vs. Single Supply Charge Injection vs. Analog Voltage 70 700 60 500 50 tTRANS 400 Q (pC) Time (ns) V– = 0 V 600 300 40 V+ = 12 V, V– = 0 V 30 tON(EN) 200 V+ = 15 V, V– = –15 V 20 100 10 tOFF(EN) 0 5 10 15 0 –15 20 –10 –5 V+ – Supply Voltage (V) 0 5 15 VS – Source Voltage (V) Off-Isolation vs. Frequency Supply Currents vs. Switching Frequency –140 10 EN = 5 V AX = 0 or 5 V 8 –120 I+ 6 –100 4 I – Current (mA) ISOL (dB) 10 –80 –60 2 0 IGND –2 –4 –40 I– –6 –20 –8 0 –10 100 1k 10 k 100 k 1M 10 M 10 100 1k f – Frequency (Hz) tON/tOFF vs. Temperature 10 M Switching Threshold vs. Supply Voltage V+ = 15 V V– = –15 V ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ 2 tTRANS V TH (V) Time (ns) 1M 3 220 tON(EN) 180 140 1 100 tOFF(EN) 0 60 –55 –35 –15 5 25 45 65 Temperature (_C) www.vishay.com S FaxBack 408-970-5600 5-6 100 k f – Frequency (Hz) 300 260 10 k 85 105 125 0 5 10 15 20 VSUPPLY – Supply Voltage (V) Document Number: 70061 S-00399—Rev. H, 13-Sep-99 DG406/407 Vishay Siliconix V+ VREF GND D A0 V+ Level Shift AX V– Decode/ Drive S1 V+ EN Sn V– FIGURE 1. +15 V +2.4 V V+ EN A2 A1 "10 V S1 A3 S2 – S15 DG406 #10 V S16 A0 VO D GND Logic Input V– tr <20 ns tf <20 ns 3V 50% 0V 50 35 pF 300 –15 V VS1 90% Switch Output +15 V +2.4 V V+ EN A2 VO S1b "10 V 0V 90% VS8 * DG407 S8b A1 A0 tTRANS #10 V S1 ON Db GND tTRANS S8 ON VO V– 50 300 35 pF –15 V * = S1a – S8a, S2b – S7b, Da FIGURE 2. Transition Time Document Number: 70061 S-00399—Rev. H, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 5-7 DG406/407 Vishay Siliconix +15 V V+ A3 A1 A0 –5 V S1 A2 S2 – S16 DG406 VO D EN GND V– 300 50 Logic Input 35 pF –15 V tr <20 ns tf <20 ns 3V 50% 0V tON(EN) +15 V V+ A2 S1b S1a – S8a S2b – S8b A1 A0 tOFF(EN) 0V Switch Output –5 V VO 90% 90% VO DG407 Da and Db EN GND VO V– 35 pF 50 300 –15 V FIGURE 3. Enable Switching Time +15 V Logic Input V+ EN +2.4 V All S and Da A3 A2 A1 +5 V tr <20 ns tf <20 ns 3V 50% 0V DG406 DG407 A0 GND 80% Switch Output V– 50 VS VO D,Db 300 35 pF VO –15 V 0V tOPEN FIGURE 4. Break-Before-Make Interval www.vishay.com FaxBack 408-970-5600 5-8 Document Number: 70061 S-00399—Rev. H, 13-Sep-99 DG406/407 Vishay Siliconix Sampling speed is limited by two consecutive events: the transition time of the multiplexer, and the settling time of the sampled signal at the output. tTRANS is given on the data sheet. Settling time at the load depends on several parameters: rDS(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired. The settling time for the multiplexer alone can be derived from the model shown in Figure 5. Assuming a low impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the RC network for a given accuracy is equal to nt: 0.25 8 6 0.012 12 9 0.0017 15 11 For the DG406 then, at room temp and for 12-bit accuracy, using the maximum limits: fs + 1 16 (9 x 100 W x 10–12F) ) 300 x 10–12 s (2) or fs = 694 kHz (3) From the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. This assumes perfect bandlimiting. In a real application sampling at three to four times the filter cutoff frequency is a good practice. Therefore from equation 2 above: fc = 1 4 x fs = 173 kHz (4) rDS(on) VOUT From this we can see that the DG406 can be used to sample 16 different signals whose maximum component frequency can be as high as 173 kHz. If for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled. RS = 0 CD(on) FIGURE 5. Simplified Model of One Multiplexer Channel The maximum sampling frequency of the multiplexer is: 1 fs = (1) N (tSETTLING + tTRANS) where N = number of channels to scan tSETTLING = nt = n x rDS(on) x CD(on) To Sensor 1 To Sensor 8 Analog Multiplexer The block diagram shown in Figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals. Differential multiplexing of small signals is preferred since this method helps to reject any common mode noise. This is especially important when the sensors are located at a distance and it may eliminate the need for individual amplifiers. A low rDS(on), low leakage multiplexer like the DG407 helps to reduce measurement errors. The low power dissipation of the DG407 minimizes on-chip thermal gradients which can cause errors due to temperature mismatch along the parasitic thermocouple paths. Please refer to Application Note AN203 for additional information. Inst Amp DG407 S/H 12-Bit A/D Converter Controller FIGURE 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique. Document Number: 70061 S-00399—Rev. H, 13-Sep-99 www.vishay.com FaxBack 408-970-5600 5-9