FUJITSU MB86835PMT2

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-05309-3E
Microprocessor SPARClite
CMOS
32-bit Embedded Controller
MB86830 Series
MB86831/832/833/834/835/836
■ DESCRIPTION
The MB86830 series is a SPARClite *1 series of RISC architecture processors, providing high performance for a
variety of embedded applications. Conforming to the SPARC *2 architecture, the MB86830 series is upward codecompatible with the conventional products in the SPARClite family. When running at 100 MHz, the MB86830 series
provides performance of 121 VAX-MIPS.
The MB86830 series has on-chip data and instruction caches, allowing the processor to operate independently of
the wait time for external memory. The independent instruction bus and internal data bus serve as high-bandwidth
interfaces between the IU (integer unit) and caches. The MB86830 series also contains an internal multiplier circuit
that facilitates interfacing with external devices, thereby providing high performance with continuous cache hits. The
DRAM controller supports both of EDO and fast-page mode DRAMs. The interrupt controller (IRC) supports eight
channels of interrupts, allowing a trigger mode and mask to be set for each of the channels. To get the most out of
the system with a minimum number of external circuits, the MB86830 series supports chip select output, programmable wait state generator, and page mode DRAM interfaces.
The combination of these features of the MB86830 series achieves high levels of speed, flexibility, and efficiency,
making it a line of ideal controllers for a variety of low-cost, high-performance embedded systems.
*1 : SPARClite is a trademark of SPARC International, Inc. in the United States.
Fujitsu Microelectronics, Inc. has been granted permission to use the trademark.
*2 : SPARC is a registered trademark of SPARC International, Inc. in the United States.
SPARC is based on technology developed by Sun Microsystems, Inc.
■ PACKAGE
176-pin plastic QFP
MB86831/832/834
144-pin plastic LQFP
MB86833/835/836
144-pin plastic FBGA
MB86836
(FPT-176P-M01)
(FPT-144P-M08)
(BGA-144P-M02)
MB86830 Series
■ FEATURES
• IU (integer unit)
Maximum operating frequency : 120 MHz
SPARC architecture V8E conforming
With 32-bits general register :136 / register window : 8
• Instruction cash
The entry lock function is supported
• Data cache
No cash controlling function supported
The entry lock function is supported
• BIU (bus interface unit)
Purifetchi baffa
:1
Write buffer
:4
The burst mode is supported
Programmable chip selection function :6
Programmable weight state control
:6
For 8/16/32-bits bus
Automatic insertion function of idling cycle after ROM region is accessed
For burst mode ROM
• With internal clock multiplication circuit
• Sleep mode (low power consumption mode) supported
• With DRAM controller (except on the MB86836)
• With interrupt request controller (IRC)
• On-chip general-purpose 16-bit timer (MB86836 only):1 channel (equivalent to the MB86942)
• Support for the JTAG test port (MB86836 only)
2
MB86830 Series
■ PRODUCT LINEUP
Part number
Item
CPU maximum frequency (MHz)
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
66/80
66/80/100
66
108/120
84
90/108*1
BUS maximum frequency (MHz)
Ancillary Version Register
40
(0000)16
33
(0001)16
(0002)16
40
(0003)16
(0004)16
(0001)16
Instruction cache
4 KB/2 way 8 KB/2 way
1 KB/Direct 16 KB/2 way 4 KB/2 way 8 KB/2 way
Data cache
2 KB/2 way 8 KB/2 way
1 KB/Direct 16 KB/2 way 2 KB/2 way 8 KB/2 way
Cache size change function
ADR pin
No
8/4/2/1 KB
selectable
ADR<27:2>
ADR enhancement (ASISEL)
No
Clock gear function
No
DSU
No
DRAM controller
No
ADR<23:2> ADR<27:2>
ADR<23:2>
ADR<31:2> ADR<27:2> ADR<31:2>
ADR<27:2>
Yes
Yes
4bank
No
Yes
1bank
4bank
No
1bank
No
JTAG test port
No
Yes
General porpose 16-bit timer*2
No
1ch
Internal pull-up/down resister pin
Internal power supply (VDD3)
I/O power supply (VDD5)
Package
P63
P63,
P162 to P164
3.3 V
3.3 V to 5.0 V
SQFP176
FPT-176P-M01
24 × 24 mm
P41 to
P44, P79
No
2.5 V
3.3 V
2.5 V
3.3 V
LQFP144
FPT-144PM08
20
× 20
LQFP144
SQFP176
LQFP144
mm
FPT-144P- FPT-176P- FPT-144PM08
M01
M08
FBGA144
20 × 20 mm 24 × 24 mm 20 × 20 mm
BGA144P-M02
12 × 12
mm
*1:MB86836 108 MHz version is under developement.
*2: The general-purpose timer on the MB86836 is a subset of the prescaler-integrated 16-bit timer on the MB86942.
For the type supporting only the internal clock mode, refer to the document for the MB86941/942.
3
MB86830 Series
■ FOR PACKAGE AND PART NUMBER
Package
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
FPT-176P-M01
Yes
Yes
No
Yes
No
No
FPT-144P-M08
No
No
Yes
No
Yes
Yes
BGA-144P-M02
No
No
No
No
No
Yes
Note:Refer to“PACKAGE DIMENSIONS” for details in each package.
■ DIFFERENCES
1.Package
• MB86831/832/834 : QFP176
• MB86833/835/836 : LQFP144
• MB86836 : FBGA144
2.Pin array
• MB86831/832/834 : The pin is interchangeable.However, the terminal of MB86834 is the pull-up resistor none.
• MB86833/835 : The pin is interchangeable.
• MB86836 : MB86833/835, from which DRAMC related pins are deleted and to which one channel of
general-purpose 16-bit timer and the JTAG pin are added.
3.Maximum operation frequency
• MB86831 : 66MHz/80MHz
• MB86832 : 66MHz/80MHz/100MHz
• MB86833 : 66MHz
• MB86834 : 108MHz/120MHz
• MB86835 : 84MHz
• MB86836 : 90MHz/108MHz
4.Power-supply voltage
Power-supply voltage
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Internal power-supply
voltage
3.3 V
2.5 V
3.3 V
2.5 V
I/O power-supply voltage
3.3 V or 5.0 V
3.3 V
3.3 V
3.3 V
* : The power-supply voltage is different (Refer to “ELECTRIC CHARACTERISTICS”) depending on the condition
of the operation frequency.
5.Cache memory
Cache memory
4
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Instruction cash
4 KB/2 way
8 KB/2 way
1 KB/Direct
16 KB/2 way
4 KB/2 way
8 KB/2 way
Data cash
2 KB/2 way
8 KB/2 way
1 KB/Direct
16 KB/2 way
2 KB/2 way
8 KB/2 way
MB86830 Series
6.Register
Register name
MB86831/832/833/835/836
MB86834
Instruction Cache Invalidate
Map of
Map of
Register
ASI = 0x0c, ADR = 0x00001000(Bank1) ASI = 0x0c, ADR = 0x00008000(Bank1)
(ICINVLD)
ASI = 0x0c, ADR = 0x80001000(Bank2) ASI = 0x0c, ADR = 0x80008000(Bank2)
Data Cache Invalidate
Register
(DCINVLD)
Map of
Map of
ASI = 0x0e, ADR = 0x00001000(Bank1) ASI = 0x0e, ADR = 0x00008000(Bank1)
ASI = 0x0e, ADR = 0x80001000(Bank2) ASI = 0x0e, ADR = 0x80008000(Bank2)
Register name
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Ancillary Version Register
(VER2)
(00)16
(01)16
(02)16
(03)16
(04)16
(01)16
7.Clock gear
• MB86832/833/834/835/836 : Supported
• MB86831 : No supported
8.External signal
Item
MB86831
MB86832
MB86833
MB86834
MB86835
MB86836
Multiplex of
Multiplex of
Multiplex of
Multiplex of ADR<27:24> and
ADR<31:28> ADR<27:24> ADR<31:28>
ASI<3:0>
and ASI<3:0> and ASI<3:0> and ASI<3:0>
ASISEL pin function
No
DSU (debugging
support unit)
No
Yes
No
Yes
DRAM controller
4Bank
supported
4Bank
supported
1Bank
supported*
4Bank
supported
No
1Bank
supported*
No
General-purpose
16-bit timer
No
Wih 1ch.
prescaler
(Equivalent to
MB86942)
JTAG
No
Support
Pull-up resistor or
pull-down resistor
Inclusion
Inclusion
No
Inclusion
*:RAS1# to RAS3# and DWE1# to DWE3# deletion.
5
MB86830 Series
■ PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
89
132
88
133
72
109
Index
Index
176
144
45
1
37
44
1
(FPT-176P- M01)
1
2
73
108
3
4
36
(FPT-144P-M08)
5
6
7
8
9
10 11 12 13
A 144 143 141 138 134 130 126 123 119 115 111 109 108
B
1
2 142 139 135 131 127 122 118 114 112 110 107
C
3
4
5 140 136 132 128 124 120 116 113 106 105
D
7
6
8
E
11
10
12
13
F
15
14
16
17
G
18
19
20
H
22
23
J
26
K
9 137 133 129 125 121 117 104 103 102
101 100
99
98
97
96
95
94
21
93
92
91
90
24
25
89
88
86
87
27
28
29
85
84
82
83
30
31
32
45
49
53
57 61
65
81
80
78
79
L
33
34
41
44
48
52
56 60
64
68
77
76
75
M
35
38
40
42
46
50
55 59
63
67
70
74
73
N
36
37
39
43
47
51
54 58
62
66
69
71
72
GND
: 12
VDD5 (VDD1) ; I/O power supply
:8
VDD3 (VDD2) ; Internal power supply : 8
(BGA-144P- M02)
6
MB86830 Series
• MB86831/832/834
Pin
Pin
Pin symbol
no.
no.
Pin symbol
Pin
no.
Pin symbol
Pin
no.
Pin symbol
Pin
no.
Pin symbol
1
VDD3
37
D<4>
73
BMREQ#
109
ADR<11>
145
FLOAT#
2
D<31>
38
BMODE8#
74
OVF#
110
READY#
146
PDOWN#
3
D<30>
39
VSS
75
SAMEPAGE#
111
VDD3
147
WKUP#
4
D<29>
40
D<3>
76
AS#
112
ADR<12>
148
RESET#
5
D<28>
41
D<2>
77
VDD3
113
ADR<13>
149
VSS
6
VSS
42
D<1>
78
RDWR#
114
ADR<14>
150
IDLEEN
7
BMODE16#
43
D<0>
79
RDYOUT#
115
ADR<15>
151
CLKSEL1
8
D<27>
44
VDD3
80
CS5#
116
VSS
152
CLKSEL0
9
D<26>
45
VSS
81
CS4#
117
ADR<16>
153
CLKEXT
10
D<25>
46
DWE3#
82
VDD5
118
ADR<17>
154
CLKIN
11
D<24>
47
DWE2#
83
VSS
119
ADR<18>
155
VDD5
12
VDD5
48
DWE1#
84
CS3#
120
ADR<19>
156
IRQ11
13
D<23>
49
DWE0#
85
CS2#
121
VDD5
157
IRQ10
14
D<22>
50
VSS
86
CS1#
122
ADR<20>
158
IRQ9
15
D<21>
51
VDD5
87
CS0#
123
ADR<21>
159
IRQ8
16
D<20>
52
RAS0#
88
VSS
124
ADR<22>
160
VSS
17
VSS
53
RAS1#
89
VDD3
125
ADR<23>
161
Reserved
18
D<19>
54
RAS2#
90
BE3#
126
MEXC#
162
[ASISEL *]
19
D<18>
55
RAS3#
91
BE2#
127
VSS
163 [EMUBRK# *]
20
D<17>
56
VDD3
92
BE1#
128
ADR<24>
164 [EMUENB# *]
21
D<16>
57
CAS0#
93
BE0#
129
ADR<25>
165
VDD3
22
BTEST#
58
CAS1#
94
VSS
130
ADR<26>
166
[EMUSD3]
23
VDD3
59
CAS2#
95
NONCACHE#
131
ADR<27>
167
[EMUSD2]
24
D<15>
60
CAS3#
96
Reserved
132
VDD3
16
[EMUSD1]
25
D<14>
61
VSS
97
Reserved
133
VSS
169
[EMUSD0]
26
D<13>
62
DOE#
98
ADR<2>
134
ASI<3>[/ADR<28>]
170
VDD5
27
D<12>
63
CLKSEL2 *
99
ADR<3>
135
ASI<2>[/ADR<29>]
171
VSS
28
VSS
64
ERROR#
100
VDD5
136
ASI<1>[/ADR<30>]
172
[EMUD3]
29
D<11>
65
LOCK#
101
ADR<4>
137
ASI<0>[/ADR<31>]
173
[EMUD2]
30
D<10>
66
CTEST#
102
ADR<5>
138
VSS
174
[EMUD1]
31
D<9>
67
VDD5
103
ADR<6>
139
VDD5
175
[EMUD0]
32
D<8>
68
BREQ#
104
ADR<7>
140
IRL<3>/IRQ15
176
VSS
33
VDD5
69
PBREQ#
105
VSS
141
IRL<2>/IRQ14
34
D<7>
70
BGRNT#
106
ADR<8>
142
IRL<1>/IRQ13
35
D<6>
71
BMACK#
107
ADR<9>
143
IRL<0>/IRQ12
36
D<5>
72
VSS
108
ADR<10>
144
VDD3
VDD3 :For internal power supply.
VDD5 :For I/O power supply.
Reserved:This pin must be open.
*:The pull-up resistor is built into. However, there is no pull-up resistor in MB86834.
[ ]:Pin is added with MB86832/834. Please use this terminal by the opening in case of MB86831-66 and 80.
7
MB86830 Series
• MB86833/835
Pin no.
Pin symbol
Pin no.
Pin symbol
Pin no.
Pin symbol
Pin no.
Pin symbol
1
VDD3
37
VDD3
73
VDD3
109
VDD3
2
BMODE16#
38
D<2>
74
BE3#
110
MEXC#
3
D<28>
39
D<1>
75
BE2#
111
ADR<23>
4
D<27>
40
D<0>
76
BE1#
112
ASI<3>/ADR<24>
5
D<26>
41
DWE0#
77
BE0#
113
ASI<2>/ADR<25>
6
D<25>
42
RAS0#
78
Reserved
114
ASI<1>/ADR<26>
7
D<24>
43
CAS0#
79
Reserved
115
ASI<0>/ADR<27>
8
D<23>
44
CAS1#
80
NONCACHE#
116
IRL<3>/IRQ15
9
VSS
45
VSS
81
VSS
117
VSS
10
D<22>
46
CAS2#
82
ADR<2>
118
IRL<2>/IRQ14
11
D<21>
47
CAS3#
83
ADR<3>
119
IRL<1>/IRQ13
12
D<20>
48
DOE#
84
ADR<4>
120
IRL<0>/IRQ12
13
D<19>
49
ERROR#
85
ADR<5>
121
FLOAT#
14
D<18>
50
LOCK#
86
ADR<6>
122
PDOWN#
15
D<17>
51
CTEST#
87
ADR<7>
123
WKUP#
16
D<16>
52
BREQ#
88
ADR<8>
124
RESET#
17
BTEST#
53
PBREQ#
89
ADR<9>
125
IDLEEN
18
VDD5
54
VDD5
90
VDD5
126
VDD5
19
VSS
55
VSS
91
VSS
127
VSS
20
D<15>
56
BGRNT#
92
ADR<10>
128
CLKSEL2
21
D<14>
57
BMACK#
93
ADR<11>
129
CLKSEL1
22
D<13>
58
BMREQ#
94
ADR<12>
130
CLKSEL0
23
D<12>
59
OVF#
95
ADR<13>
131
CLKEXT
24
D<11>
60
SAMEPAGE#
96
ADR<14>
132
CLKIN
25
D<10>
61
AS#
97
ADR<15>
133
IRQ11
26
D<9>
62
RDWR#
98
ADR<16>
134
IRQ10
27
D<8>
63
RDYOUT#
99
ADR<17>
135
IRQ9
28
BMODE8#
64
CS5#
100
READY#
136
IRQ8
29
VDD3
65
VDD3
101
VDD3
137
VDD3
30
VSS
66
VSS
102
VSS
138
VSS
31
D<7>
67
CS4#
103
ADR<18>
139
Reserved
32
D<6>
68
CS3#
104
ADR<19>
140
ASISEL
33
D<5>
69
CS2#
105
ADR<20>
141
D<31>
34
D<4>
70
CS1#
106
ADR<21>
142
D<30>
35
D<3>
71
CS0#
107
ADR<22>
143
D<29>
36
VDD5
72
VDD5
108
VDD5
144
VDD5
VDD3 :For internal power supply.
VDD5 :For I/O power supply.
Reserved:This pin must be open.
8
MB86830 Series
• MB86836
Pin no.
Pin symbol
Pin no.
Pin symbol
Pin no.
Pin symbol
Pin no.
Pin symbol
1
VDD3
37
VDD3
73
VDD3
109
VDD3
2
BMODE16#
38
D<2>
74
BE3#
110
MEXC#
3
D<28>
39
D<1>
75
BE2#
111
ADR<23>
4
D<27>
40
D<0>
76
BE1#
112
ASI<3>/ADR<24>
5
D<26>
41
TRST#
77
BE0#
113
ASI<2>/ADR<25>
6
D<25>
42
TCK*
78
VPD
114
ASI<1>/ADR<26>
7
D<24>
43
TMS*
79
IN0
115
ASI<0>/ADR<27>
8
D<23>
44
TDI*
80
NONCACHE#
116
IRL<3>/IRQ15
9
VSS
45
VSS
81
VSS
117
VSS
10
D<22>
46
TDO
82
ADR<2>
118
IRL<2>/IRQ14
11
D<21>
47
OUT0
83
ADR<3>
119
IRL<1>/IRQ13
12
D<20>
48
PRSCK0
84
ADR<4>
120
IRL<0>/IRQ12
13
D<19>
49
ERROR#
85
ADR<5>
121
FLOAT#
14
D<18>
50
LOCK#
86
ADR<6>
122
PDOWN#
15
D<17>
51
CTEST#
87
ADR<7>
123
WKUP#
16
D<16>
52
BREQ#
88
ADR<8>
124
RESET#
17
BTEST#
53
PBREQ#
89
ADR<9>
125
IDLEEN
18
VDD5
54
VDD5
90
VDD5
126
VDD5
19
VSS
55
VSS
91
VSS
127
VSS
20
D<15>
56
BGRNT#
92
ADR<10>
128
CLKSEL2
21
D<14>
57
BMACK#
93
ADR<11>
129
CLKSEL1
22
D<13>
58
BMREQ#
94
ADR<12>
130
CLKSEL0
23
D<12>
59
OVF#
95
ADR<13>
131
CLKEXT
24
D<11>
60
SAMEPAGE#
96
ADR<14>
132
CLKIN
25
D<10>
61
AS#
97
ADR<15>
133
IRQ11
26
D<9>
62
RDWR#
98
ADR<16>
134
IRQ10
27
D<8>
63
RDYOUT#
99
ADR<17>
135
IRQ9
28
BMODE8#
64
CS5#
100
READY#
136
IRQ8
29
VDD3
65
VDD3
101
VDD3
137
VDD3
30
VSS
66
VSS
102
VSS
138
VSS
31
D<7>
67
CS4#
103
ADR<18>
139
Reserved
32
D<6>
68
CS3#
104
ADR<19>
140
ASISEL
33
D<5>
69
CS2#
105
ADR<20>
141
D<31>
34
D<4>
70
CS1#
106
ADR<21>
142
D<30>
35
D<3>
71
CS0#
107
ADR<22>
143
D<29>
36
VDD5
72
VDD5
108
VDD5
144
VDD5
: 2.5-V power pin (for supplying internal power)
VDD3
VDD5
: 3.3-V power pin (for supplying I/O power)
Reserved : Leave the pin open.
VPD: Test pin. Usually fixed to the L level.
* : With an internal pull-down resistor
9
MB86830 Series
■ PIN DESCRIPTION
1. CPU Core Related Pins
Symbol
Pin name
I/O
Function
I
Clock input pin.
The clock regulates external bus operation.The bus AC characteristics
are determined based on the clock.
CLKIN
CLOCK
CLKEXT
EXTERNAL
CLOCK BYPASS
I
External clock select pin.
The “L” level at this pin selects the clock signal generated by the internal
PLL circuit; theC“H” level selects the external clock signal (input through
the CLKIN pin) as it is.Fix this pin usually at the “L” level.
RESET#
SYSTEM RESET
I
Reset input.
The “L” input to this pin initializes the CPU.
Internal clock setting pins.
These pins are used to set the IU (integer unit) and cache operating
clock frequencies to x1, x2, x3, x4, or x5 of the external clock frequency.
CLKSEL0
CLKSEL1
CLKSEL2
INTERNAL
CLOCK SELECT
CLKSEL2
CLKSEL1
CLKSEL0
Internal clock
H
L
L
×1
H
L
H
×2
H
H
L
×3
H
H
H
×4
L
H
H
×5
I
Any other setting is prohibited.
ASISEL
CTEST#
BTEST#
ADR<27:2>
or
ADR<23:2>
(MB86833/
835/836)
ADDRESS
SPACE IDENTIFIERS SELECT
CTEST
BTEST
ADDRESS BUS
ASI select signal
This pin selects the ASI or ADR pin.
Setting this pin to “L” prohibits the “L” input to the AS# pin in the bus
grant state.
On the MB86832, this pin is pulled up with a resistor of about 50 kΩ.
I
I
ASISEL
MB86832/834
ASI<3:0>/ADR<28:31>
MB86833/835/836
ASI<3:0>/ADR<24:27>
L
ADR<28:31>
ADR<24:27>
H
ASI<3:0>
ASI<3:0>
Test pins.
Fix these pins usually to the “H” level.
Address pin.
The ADR<27:2>pin (ADR<23:2>pin on the MB86833/835/836)handles
the signal for identifying an instruction address or data address.For using the 8/16-bit bus width, ADR<1> and ADR<0> are output multiplexed
with BE2# and BE3#, respectively.This pin remains enabled during the
I/O
bus cycle; the value output during the idle cycle is not guaranteed.
In the bus grant state, the pin serves as an input used, e.g., by the CS
generator circuit (while the “L” input to the AS# pin is prohibited with the
ASISEL pin at the “L” level) and ADR<31:28> (ADR<31:24> on the
MB86833/835/836) is handled internally as 0.
(Continued)
10
MB86830 Series
(Continued)
Symbol
D<31:0>
AS#
RDWR#
BE0#
BE1#
BE2#
BE3#
Pin name
DATA BUS
ADDRESS
STROBE
READ/WRITE
BUS
TRANSACTION
BYTE ENABLE
I/O
Function
I/O
Data bus signal.
This pin provides a bidirectional data bus used for instruction fetch,
data load, and data store operations. Instructions and word data must
be aligned at addresses which are multiples of the number 4.
Half words and double words must be aligned at addresses which are
multiples of the numbers 2 and 8, respectively. D<7:0> and D<15:0>
are used in the 8-bit and 16-bit bus modes, respectively. For use in the
16-bit bus mode, a pull-up resistor must be connected to the data bus
which is not used (D<31:8> for the 8-bit bus and D<31:16> for the 16bit bus).
I/O
Address strobe signal.
This pin outputs the “L” level signal for the first bus cycle. Basically, the
bus cycle starts with the AS# signal asserted and ends up with the
READY# or RDYOUT# signal asserted.
In the bus grant state, the pin serves as an input used for the signals to
actuate the CS generator and wait state generator circuits.
I/O
Read/write signal.
This pin outputs the “L” level signal when the current bus cycle is the
write cycle or the “H” level signal when it is the read or idle cycle. The
output level remains at “H” or“L” during the entire bus cycle from the beginning to end.
In the bus grant state, the pin serves as an input used for generating
the DWE0#-DWE3# and DOE# signals to enable the DRAM controller.
The signal at this pin is not used when the DRAM controller is disabled.
O
O
I/O
O
Bye enable signals.
These pins are used to indicate the bytes valid for in write mode when
the 32-bit bus width is used.
In read mode, all of the BE0# to BE3# signals are asserted regardless
of the data type. For the 8-bit or 16-bit bus width, the BE2# and BE3#
pins output ADR<1> and ADR<0>, respectively.
The BE0# to BE3# pins remain enabled during the bus cycle; the output level during the idle cycle is not guaranteed.
In the bus grant state, the pins enter the High-Z state and, only when
the DRAM controller is on with the 16-bit bus width used, the BE2# pin
serves as the ADR<1> input pin.
Width of
bus
Width of
32-bits
bus
Access type
Write
Read
BE0#
BE1#
BE2#
BE3#
Byte-0 (D<31:24>) *
0
1
1
1
Byte-1 (D<23:16>)
1
0
1
1
Byte-2 (D<15:8>)
1
1
0
1
Byte-3 (D<7:0>)
1
1
1
0
Half word-0(D<31:16>)
0
0
1
1
Half word-1(D<15:0>)
1
1
0
0
Word
0
0
0
0
All data types
0
0
0
0
(Continued)
(Continued)
11
MB86830 Series
(Continued)
Symbol
Pin name
I/O
Function
(Continued)
Width of
bus
Width of
16-bits
bus
Access type
Write
Read
BE0#
BE1#
BE2#
BE3#
BYTE ENABLE
O
O
I/O
O
Write
Width of
8-bits
bus
Read
BE0#
BE1#
BE2#
BE3#
Byte-0 (D<15:8>)
1
0
0
0
Byte-1 (D<7:0>)
0
1
0
0
Byte-2 (D<15:8>)
1
0
1
0
Byte-3 (D<7:0>)
0
1
1
0
Half word-0 (D<15:0>)
0
0
0
0
Half word-1 (D<15:0>)
0
0
1
0
Word (D<15:0>) access-0
0
0
1
0
Word (D<15:0> )access-1
0
0
0
0
Access-0
0
0
0
0
Access-1
0
0
1
0
Byte-0
X
X
0
0
Byte-1
X
X
0
1
Byte-2
X
X
1
0
Byte-3
X
X
1
1
Half word-0 access-1
X
X
0
1
Half word-0 access-0
X
X
0
0
Half word-1 access-0
X
X
1
1
Half word-1 access-1
X
X
1
0
word access-0
X
X
1
1
word access-1
X
X
1
0
word access-2
X
X
0
1
word access-3
X
X
0
0
Access-0
X
X
0
0
Access-1
X
X
0
1
Access-2
X
X
1
0
Access-3
X
X
1
1
* : The mark such as (D<31:24>) shows the bit of the data bus used.
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
12
CHIP SELECT
O
Chip select signals.
These chip select signals are asserted when the Address Range Specifier Register (ARSR) and Address Mask Register (AMR) is accessed
with the CS Enable bit (bit 4) in the System Support Control Register
(SSCR) set to “1.” (Note, however, that only the CS0# pin is independent of the CS Enable bit.)
(Continued)
MB86830 Series
(Continued)
Symbol
Pin name
I/O
Function
BREQ#
BUS REQUEST
I
Bus request signal.
When the BREQ# signal is asserted by external bus mastering, the
CPU releases the bus as shown below upon termination of the current
bus cycle:
(1)When executing the Atomic Load Store instruction, the CPU releases the bus after completing both of loading and storing.
(2)When loading or storing a double word:
If the BREQ# signal is asserted at the first word, the CPU releases
the bus after transfer of the first word. If the BREQ# signal is asserted in the bus cycle for the second word, the CPU releases the bus
after transfer of the second word.
(3)When storing data at the 8/16-bit bus width:
The CPU releases the bus after transfer of that size of data which is
handled by the instruction (for example, after writing 8-bit data four
times when storing word data using an 8-bit bus).
(4)When loading data at the 8/16-bit bus width:
The CPU releases the bus after transfer of one word.
When the ASISEL pin is at the “L” level, the “L” input to the AS# pin
is prohibited in the bus grant state.
BGRNT#
BUS GRANT
O
Bus grant signal.
Upon reception of a bus request (BREQ#), the BGRNT# signal is asserted to notify the external device of the bus released status.
I
Interrupt input pins.
These pins are used to input an encoded interrupt level. They handle
a group of asynchronous input signals, notifying the IU (integer unit) of
an interrupt level only when the same level is detected twice at the fall
of an external clock pulse. IRL = 0000 2 and IRL = 1111(2) indicate no
interrupt and a nonmaskable interrupt as defined in the SPARC architecture. IRL must be determined for priority by an external circuit and
must be held until confirmed by the CPU.
I
Ready signal input pin.
Input the “L” level signal to upon completion of a bus cycle.
Upon reception of READY#=“L”, the CPU starts the next bus cycle.
Note, however, that the“L” input to this pin is not necessary when the
internal wait state generator circuit is used.
For burst transfer, instruction fetch or data load using an 8-bit bus, instruction fetch or data load using an 16-bit bus, the pin must input the
ready signal for the prescribed number of times whenever the address
strobe signal is asserted.
IRL3
IRL2
IRL1
IRL0
READY#
MEXC#
INTERRUPT REQUEST LEVEL
EXTERNAL
READY
MEMORY
EXCEPTION
I
Memory access exception pin.
If this pin inputs the “L” level signal in the same cycle as the ready signal input, the CPU handles it as an instruction access or data access
exception to generate a trap. The operation of the device is unpredictable if the MEXC# signal is asserted at a timing other than the same
cycle as the ready signal input. (An exception occurring with the PSR
ET bit set to “0” results in an error state.)
(Continued)
13
MB86830 Series
(Continued)
Symbol
ERROR#
ASI<3:0>
LOCK#
RDYOUT#
IDLEEN
BMODE8#
BMODE16#
14
Pin name
I/O
Function
ERROR SIGNAL
O
Error signal.
This pin outputs an error signal indicating that the CPU has stopped in
the error state resulting from a trap occurring with traps disabled. The
CPU can exit the error state only by a reset.
ADDRESS
SPACE
IDENTIFIERS
ASI pin (address space identification signal) or ADR pin.
Setting the ASISEL pin to “H” selects the ASI pin; setting it to “L” selects
the ADR<28:31> pin on the MB86832/834 or ADR<24:27> pin on the
MB86833/835/836. When the ASISEL pin is set to “L”, the “L” input to
the AS# pin is prohibited. A choice of these pins is supported by the
MB8682/833/834/835/836 but not by the MB86831-66/80 (only
I/O
ASI<3:0> is available).
Like the ADR<27:2> pin (ADR<23:2> pin on the MB86833/835/836),
this pin remains enabled for output during the bus cycle. The ASI pin
serves as an input in the bus grant state, used for CS generation and
internal resource address decoding. When ASI<3:0> is input from an
external device, ASI<7:4> is handled as “0” in the CPU.
BUS LOCK
READY OUTPUT
IDLE ENABLE
BOOT MODE 8
BOOT MODE 16
O
Bus lock signal.
During execution of the Atomic Load Store instruction, the CPU asserts
the LOCK# signal to indicate that the current bus transaction requires
multiple transfers which cannot be divided. At a bus request (BREQ#)
during execution of an atomic instruction, the CPU releases the bus (by
asserting the BGRNT# signal) upon completion of the instruction execution. For normal use (where bus access permission is controlled by
BREQ#/BGRNT#), the LOCK# signal need not be used.
O
Ready signal output.
This pin outputs the composite signal consisting of the ready signal
generated by the internal wait state generator circuit and the external
ready signal (READY#). While the delay of the internally generated
ready signal is regulated based on the clock input, the input from the
pin is output delayed as it is at the timing of generation of the external
ready signal.
I
Idle insertion enable pin.
If the cycle that follows access to the CS0# area is load or store operation when this pin is at the “H” level, the CPU starts the next bus cycle
after inserting two idle clock cycles. This is efficient when EPROM
which takes long data bus output off time is connected directly to the
CPU.When this pin is at the “L” level, the CPU inserts only one idle cycle before a write cycle immediately after a read cycle (this control is
compatible with conventional SPARClite processors).
Fix this pin at the “H” or “L” level.
I
CS0# area bus width setting signals.
These pins input signals at a reset to determine the bus width of the
CS0# area. Setting the BMODE8# pin to “L” selects the 8-bit bus
mode; setting the BMODE16# pin to “L” selects the 16-bit bus mode.
(The bus width for the CS1#-CS5# area is specified by the Bus Width/
Cacheable Control Register (BWCR).)
Fix these pins to “L” or “H”. However, it is not allowed to set both of
them to “L”.
(Continued)
MB86830 Series
(Continued)
Symbol
NONCACHE#
PDOWN#
WKUP#
BMREQ#
BMACK#
PBREQ#
Pin name
NON-CACHEABLE
POWER DOWN
WAKE-UP
BURST MODE
REQUEST
BURST MODE
ACKNOWLEDGE
PROCESSOR
BUS REQUEST
I/O
Function
I
Non-cacheable signal.
This pin inputs the signal for exclusion from data caching. The NONCACHE# signal is enabled by setting the Cacheability Enable bit (bit 7)
in the Cache/BIU Control Register (CBIR). The “L” input to this pin
when data is read prevents the data and its address from being written
to the data cache (the NONCACHE# signal is disabled at an instruction
fetch). Usually, the NONCACHE# signal must be asserted in the cycle
in which the address strobe signal is asserted. Even if the NONCACHE# signal is asserted after a delay of one or more cycles, however, the signal can be used by setting the Non-cacheable bit (bit 9, bit
8) in the Cache/BIU Control Register (CBIR).
O
Sleep mode (low power consumption mode) output pin.
“L” level input to this pin releases the CPU from the sleep mode (low
power consumption mode) to start operation. Although the pin is an
asynchronous input, it requires an “L” width of at least two clock cycles.
Input “L” to this pin only when the PDOWN# pin is at the “L” level.
I
Sleep mode (low power consumption mode) cancel pin.
“L” input to this pin cancels the CPU sleep mode (low power consumption mode), causing the CPU to start operation. Although the pin is an
asynchronous input, it requires an “L” width of at least two clock cycles.
Input the“L” signal to this pin only when PDOWN# is “L”. When
PDOWN# goes “H”, set this pin to "H".
O
Burst transfer request pin.
If a cache miss occurs when the Instruction Burst Enable bit or Data
Burst Enable bit in the Bus Control Register (BCR) has been set, the
CPU sets the BMREQ# signal to “L” and requests external memory for
burst transfer. The BMREQ# signal is also asserted when the DRAM
Burst Enable bit in the System Support Control Register (SSCR) has
been set. In this case, however, the external device need not return
the BMACK# signal because the internal DRAM controller responds to
the request.
I
Burst mode acknowledge input.
When a burst transfer request is issued, the burst transfer mode is established if the “L” level asserted until the same cycle as the READY#
signal is input to this pin. (It is also established either when the “L” level
is input in the same cycle as the READY# signal or when the “L” level
input in an earlier cycle continues until the same cycle as the READY#
signal.) When the DRAM Burst Enable bit in the System Support Control Register (SSCR) has been set, the burst transfer mode is established even though this pin receives the BMACK# signal.
O
Processor bus request signal.
When the CPU requires accessing an external bus
The PBREQ# signal is asserted to issue a processor bus request to the
external bus master when the CPU requires accessing an external bus
(when it requires external access after a cache miss) while the CPU
has relinquished bus access permission.
(Continued)
15
MB86830 Series
(Continued)
Symbol
OVF#
Pin name
TIMER OVERFLOW
SAMEPAGE#
SAME PAGE
DETECT
FLOAT#
FLOATING
• State of pins
Pin symbol
Function
O
Timer overflow signal.
This pin outputs the “L” pulse when the timer reaches 0 after starting
counting according to the settings in the DRAM Refresh Timer Register
and DRAM Refresh Timer Pre-load Register with the TIMER ON/OFF
bit in the System Support Control Register (SSCR) set to “1” The pulse
width is the 1-clock width of the external bus clock when bit 31 in the
DRAM Refresh Timer Pre-load Register is “0”. When the bit is “1”, the
pulse width is the 3-clock width.
The timer performs counting based on the external bus clock.
Although this pin is used usually for the DRAM refresh request signal,
it can be connected to the interrupt input (IRQx) of the interrupt controller (IRC) when the pulse width has been specified as the 3-clock width.
O
Same-page detection output pin.
When the Same-Page Enable bit in the System Support Control Register (SSCR) has been “1”, this pin outputs the“L” level if the CS4# pin
is at the “L” level and if the address masked by the Same-Page Mask
Register (SPGMR) matches the previously accessed address when
compared.
The SAMEPAGE# signal remains output during the bus cycle.
I
Pin float input.
Fixing this pin at the “L” level puts all of the output pins and bidirectional
pins to the High-Z state.
At reset
At bus grant
At reset
At bus grant
ADR<27:2>
O (X)
I (D)
D<31:0>
I (Z)
I (Z)
AS#
O (H)
I (Z)
RDWR#
O (H)
I (Z)
BE0#
O (X)
O (Z)
BE1#
O (X)
O (Z)
BE2#
O (X)
I (Z)
BE3#
O (X)
O (Z)
CS0# to CS5#
O (H)
O (V)
BGRNT#
O (H)
O (L)
ERROR#
O (H)
O (V)
ASI<3:0>
O (X)
I (Z)
LOCK#
O (H)
O (Z)
RDYOUT#
O (V)
O (V)
PDOWN#
O (H)
O (H)
BMREQ#
O (H)
O (H)
PBREQ#
O (H)
O (V)
OVF#
O (H)
O (V)
SAMEPAGE#
O (H)
O (V)
O (V)
O (X)
O (Z)
O (H)
O (L)
I (Z)
I (D)
16
I/O
Pin symbol
:The circuit is active with the output at a valid level.
:The circuit is inactive with the output indeterminate.
:Output pins and High-Z.
:The “H”level is output.
:The “L” level is output.
:Input pins and High-Z
:When the DRAM controller has been enabled, the pin is switched to serve as an output, from the clock cycle
that follows the clock cycle in which the AS# pin becomes “L”, and remains as the output until the ready
signal input pin becomes “L”. When the DRAM controller has been disabled, the pin enters the High-Z state.
MB86830 Series
2. DRAM Controller Related Pins (MB86831/832/833/834/835)
Symbol
RAS0#
RAS1#
RAS2#
RAS3#
CAS0#
CAS1#
CAS2#
CAS3#
DWE0#
DWE1#
DWE2#
DWE3#
Pin name
DRAM ROW
ADDRESS
STROBE
DRAM COLUMN
ADDRESS
STROBE
DRAM WRITE
ENABLE
I/O
Function
O
DRAM controller RAS outputs.
The RAS0# to RAS3# signals are control signals corresponding to
DRAM banks 0 to 3, respectively.
The MB86833/835 does not support banks 1 to 3 because the RAS1#
to RAS3# pins do not exist on the chip.
O
DRAM CAS control outputs.
For using the 32-bit bus width along with 2-CAS DRAM, the CAS0# to
CAS3# pins are controlled in association with byte 0 (b31 to b24), byte
1 (b23 to b16), byte 2 (b15 to b8), and byte 3 (b7 to b0), respectively.
For using the 16-bit bus width along with 2-CAS DRAM, the CAS2# and
CAS3# pins correspond to byte 0 (byte data at an even-numbered address) and byte 1 (byte data at an odd-numbered address), respectively. When the 16-bit bus width is used, the outputs from the CAS0# and
CAS1# pins are unpredictable.
When 2-WE DRAM is used, the CAS0# to CAS3# pins provide the
same output.
O
DRAM write enable control outputs.
For using 2-WE DRAM, the DWE0# to DWE3# signals are controlled in
association with byte 0 (b31 to b24), byte 1 (b23 to b16), byte 2 (b15 to
b8), and byte 3 (b7 to b0), respectively.
When 2-CAS DRAM is used, the DWE0# to DWE3# pins provide the
same output.
The DWE1# to DWE3# pins do not exist on the MB86833/835.
DRAM OE control output.
When fast-page DRAM is used, the DRAM can be controlled without
using the DOE# signal because the DWEx# and CASx# pins are controlled at the early write timing. When EDO (hyper page mode) DRAM
is used, the DOE# signal is required for high-impedance control of the
DRAM output.
DOE#
DRAM OUTPUT
O
ADR<13:2>
ADDRESS BUS
DRAM address signal.
I/O The DRAM controller outputs the multiplexed row and column addresses to a CPU address pin of ADR<13:2>.
• State of pins
Pin symbol
At reset
At bus grant
Pin symbol
At reset
At bus grant
RAS3# to RAS0#
O (H)
O (V)
CAS3# to CAS0#
O (H)
O (V)
DOE#
O (H)
O (V)
ADR<13:2>
O (X)
I (D)
O (V)
O (X)
O (H)
I (D)
: The circuit is active with the output at a valid level.
: The circuit is inactive with the output indeterminate.
: The “H” level is output.
: When the DRAM controller has been enabled, the pin is switched to serve as an output, from the clock cycle
that follows the clock cycle in which the AS# pin becomes “L”, and remains as the output until the ready
signal input pin becomes “L”. When the DRAM controller has been disabled, the pin enters the High-Z
state.
17
MB86830 Series
3. Interrupt controller (IRC) Related Pins
Symbol
IRQ15/IRL3
IRQ14/IRL2
IRQ13/IRL1
IRQ12/IRL0
IRQ11
IRQ10
IRQ9
IRQ8
Pin name
INTERRUPT
REQUEST
I/O
Function
I
Interrupt input pins.
When the active level set for the interrupt controller (IRC) trigger mode
is input to these pins, the request sense register of the interrupt controller (IRC) holds the interrupt request. (The interrupt controller (IRC)
evaluates priority levels and performs coding for the IRL<3:0> pin, and
notifies the CPU core of the interrupt level.)
The IRQ15 to IRQ12 signals are assigned to the IRL<3:0> pin. They
function as IRQ15 to IRQ12 when the interrupt controller (IRC) becomes enabled.
4. Signals for the general-purpose 16-bit timer (MB86836)
Symbol
Pin name
Prescaler Clock
Output0
PRSCK0
I/O
Function
O
Prescaler output pin.
The external clock mode is not supported, which is included in the
functions of the prescaler on the MB86942.
The pin is reset to “L”.
OUT0
Timer Output0
O
Timer output pin.
The external clock mode is not supported, which is included in the
functions of the timer on the MB86942.
The pin is reset to “L”.
IN0
Timer Input0
I
Timer count operation control pin.
This pin inputs the GATE signal in MODE0 to MODE3 and the external
trigger signal in MODE4.This pin has an internal pull-down resistor.
• Pin status
Symbol
Reset
Bus granted
PRSCK0
O (L)
O (V)
OUT0
O (L)
O (V)
Note : O (L) : Output “L” level
O (V) : Circuit activated ; effective level is output
18
MB86830 Series
5. DDSU (Debug Support Unit) Related Pins (MB86832/834)
Symbol
EMUBRK#
EMUENB#
EMUD<3:0>
EMUSD<3:0>
Pin name
I/O
Function
I
Emulator Break pin.
When a reset is canceled, the EMUBRK# signal level is input to set a
mode in combination with the EMUENG# signal level.
The MB86832 contains a pull-up resistor (about 50 kΩ). Leave this pin
open when the DSU (debug support unit) is not used. The MB86834
has no pull-up resistor.
I/O
Emulator Enable pin.
When a reset is canceled, the EMUENB# signal level is input to set a
mode in combination with the EMUBRK# signal level. When a reset is
canceled, this pin becomes an output pin after four clock cycles if either
(DSUBRK# = DSUENB# = “L”) or (DSUBRK# = “H”, DSUENB# = “L”)
is set.
The MB86832 contains a pull-up resistor (about 50 kΩ). Leave this pin
open when the DSU (debug support unit) is not used. The MB86834
has no pull-up resistor.
I/O
Emulator Data pin.
This pin outputs traced instruction addresses divided into eight components in the monitor mode. It also inputs instruction codes and outputs
instruction or data addresses in the DSU mode.
Since this pin serves as an output with the DSU disabled, leave the pin
open if the DSU (debug support unit) is not to be used.
I/O
Emulator Status/Data pin.
This pin outputs the CPU status in the monitor mode and. It also inputs
instruction codes and outputs instruction or data addresses in the DSU
mode.
Since this pin serves as an output with the DSU disabled, leave the pin
open if the DSU (debug support unit) is not to be used.
Emulator Break
Emulator Enable
Emulator Data Bus
Emulator Status/
Data Bus
6. Signals for the JTAG Test Port (MB86836)
Symbol
Pin name
I/O
Function
TCK
Test Clock
I
JTAG test clock input pin.
This pin has an internal pull-down resistor.
TMS
Test Mode
I
JTAG test mode selection pin.
This pin has an internal pull-down resistor.
TDI
Test Data In
I
JTAG test data input pin.
This pin has an internal pull-down resistor.
TDO
Test Data Out
O
JTAG test data output pin.
TRST#
Test Reset
I
JTAG test reset pin.
This pin is reset to “L”. It has an internal pull-down resistor.
19
MB86830 Series
■ BLOCK DIAGRAM
CLKIN
DIVIDE STEP
Peripheral
resource
MULTIPLY
SCAN
Clock Generator
SPARC INTEGER UNIT
x1 x2 x3 x4 x5
32
DATA
ADDRESS
I Data
Bus Interface
Unit
32
Debug
Support
Unit 2
I Address
32
ASI
D Address
32
Address
Decode
CONTROL
IRL
Wait State
Generator
CHIP_SEL
PAGE_DET
D Data
DRAM Support
16 bit Timer
Instruction Cache
1
Data Cache
1
REFRESH
CPU Core
*1:The cache capacity is as follows.
Parts number
MB86831
Item
MB86832
MB86833
MB86835
MB86836
Instruction cash
4 KB/2 way
8 KB/2 way
1 KB/Direct 16 KB/2 way
4 KB/2 way
8 KB/2 way
Data cash
2 KB/2 way
8 KB/2 way
1 KB/Direct
2 KB/2 way
8 KB/2 way
*2:DSU (debug support unit) is added with MB86832/834.
20
MB86834
16 KB/2 way
MB86830 Series
■ ELECTRIC CHARACTERISTICS
1. ABSOLUTE MAXIMUM RATINGS
(1)MB86831-66/MB86832-66/MB86833
Parameter
(VSS = 0.0 V)
Symbol
Rating
Min.
Max.
Unit
Power supply voltage(I/O)
VDD5
− 0.5
6
V
Power supply voltage(Internal)
VDD3
− 0.5
4
V
Input voltage
VI
− 0.5
VDD5 + 0.5
V
Storage temperature
TSTG
− 55
+ 125
°C
Temperature at bias
TBIAS
0
+ 70
°C
Overshoot

Within VDD5 + 1.0 V (Within 50 ns )

Undershoot

Within VSS − 1.0 V (Within 50 ns )

(2)MB86834-108,-120/MB86836-90,-108
Parameter
Symbol
(VSS = 0.0 V)
Rating
Min.
Max.
Unit
Power supply voltage(I/O)
VDD5(VDDE)
− 0.5
4.0
V
Power supply voltage(Internal)
VDD3(VDDI)
− 0.5
3.0
V
Input voltage
VI
− 0.5
VDDE + 0.5
V
Storage temperature
TSTG
− 55
+ 125
°C
Temperature at bias
TBIAS
0
+ 70
°C
(3)MB86835
Parameter
(VSS = 0.0 V)
Symbol
Rating
Min.
Max.
Unit
Power supply voltage(I/O)
VDD5
− 0.5
4
V
Power supply voltage(Internal)
VDD3
− 0.5
4
V
Input voltage
VI
− 0.5
VDD5 + 0.5
V
Storage temperature
TSTG
− 55
+ 125
°C
Temperature at bias
TBIAS
0
+ 70
°C
Overshoot

Within VDD5 + 1.0 V (Within 50 ns )

Undershoot

Within VSS − 1.0 V (Within 50 ns )

21
MB86830 Series
(Notes on Board Wiring)
• For connecting the power supply and ground (GND), use multiple VDD and VSS pins. The system board based
on the MB86830 series must be a multilayer board containing power supply (VDD) and GND (VSS) layers for
stable power supply. Leave any pin designated as “N.C.” unconnected.
• Insert sufficient decoupling capacitors near the MB86830 series. Changes to the output levels of many of the
output pins on the MB86830 series (in particular, those with large load capacitance) may cause variation in
power supply.
• For those systems which run at a high frequency, low-inductance capacitors and mutual wiring are recommended. Inductance can be lowered by shortening the distance between the processor and decoupling
capacitor.
• For system reliability, the pin entering the tristate when the MB86830 series enters the bus grant state should
be driven by a bus master. In particular, the LOCK#, ADR<27:2>, ASI<3:0> (ASI<3:0>/ADR<28:31>, ASI<3:0>
/ADR<24:27>), BE0# to BE3#, D<31:0>, AS#, and RDWR# pins must be driven by other bus masters. Usually,
these pins require no external pull-up resistor because they are driven by the processor when the processor
is active or idle.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage,
current,temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB86830 Series
2. RECOMMENDED OPERATING CONDITIONS
(1)MB86831-66/MB86832-66/MB86833
Parameter
(VSS = 0.0 V)
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply voltage (I/O = 5.0 V)
VDD5
4.75
5.0
5.25
V
Power supply voltage (I/O = 3.3 V)
VDD5
3.0
3.3
3.6
V
Power supply voltage (internal)
VDD3
3.0
3.3
3.6
V
“L” level input voltage
VIL
0

VDD3 × 0.25
V
“H” level input voltage
VIH
VDD3 × 0.65

VDD5
V
Operating temperature
Topr
0
+ 25
+ 70
°C
(2)MB86831-80/MB86832- 80, -100
(VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply voltage (I/O = 5.0 V)
VDD5
4.75
5.0
5.25
V
Power supply voltage (I/O = 3.3 V)
VDD5
3.15
3.3
3.45
V
Power supply voltage (internal)
VDD3
3.15
3.3
3.45
V
“L” level input voltage
VIL
0

VDD3 × 0.25
V
“H” level input voltage
VIH
VDD3 × 0.65

VDD5
V
Operating temperature
Topr
0
+ 25
+ 70
°C
(3)MB86834-108,-120/MB86836-90,-108
Parameter
(VSS = 0.0 V)
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply voltage (I/O)
VDD5(VDDE)
3.15
3.3
3.45
V
Power supply voltage (internal)
VDD3(VDDE)
2.4
2.5
2.6
V
“L” level input voltage
VIL
− 0.3

0.8
V
“H” level input voltage
VIH
2.0

VDDE + 0.3
V
Operating temperature
Topr
0
+ 25
+ 70
°C
23
MB86830 Series
(4)MB86835
(VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply voltage (I/O = 3.3 V)
VDD5
3.15
3.3
3.45
V
Power supply voltage (internal)
VDD3
3.15
3.3
3.45
V
“L” level input voltage
VIL
0

VDD3 × 0.25
V
“H” level input voltage
VIH
VDD3 × 0.65

VDD5
V
Operating temperature
Topr
0
+ 25
+ 70
°C
• The MB86831/832/833 can be used with a 5.0-V or 3.3-V interface.
5.0-V interface: VDD5 = 5.0 V, VDD3 = 3.3 V (two power supplies)
3.3-V interface: VDD5 = VDD3 = 3.3 V (single power supply)
• When the 3.3-V interface is used, all signals input to the MB86830 series must be 3.3 V because the MB86830
series cannot input 5.0-V signals with that interface.
• When the 5.0-V interface is used, the output fully swings at 5.0 V. Although the input is always defined by a
3.3-V power supply, it can also accept 3.3 V or more.
• When the 5.0-V interface is used, the MB86830 series requires two power supplies. Follow the procedures
below to turn on and off these power supplies:
Power-on procedure: VDD3 → VDD5 → signal
Shutdown procedure: Signal → VDD5 → VDD3
• The MB86834/836 requires two power supplies of VDDE (3.3-V system) and VDDI (2.5-V system). Follow the
procedures below to turn on and off these power supplies:
Power-on procedure: VDDI → VDDE→ signal
Shutdown procedure: Signal → VDDE → VDDI
• The MB86835 has two VDD, VDD3 and VDD5. Connect each of them to a 3.3-V power supply.
• The MB86834/835/836 uses only a 3.3-V interface; they cannot accept 5-V signals.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
24
MB86830 Series
3. DC Characteristics
(1)MB86831-66 (Maximum internal operation frequency:66 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

40

mA
Power supply current (VDD3 )
IDD
66 MHz

150

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
Symbol
(VDD5 = VDD3 = 3.3 V ± 0.3%, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

30

mA
Power supply current (VDD3 )
IDD
66 MHz

150

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
25
MB86830 Series
(2)MB86831-80 (Maximum internal operation frequency:80 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
40MHz No-load

50

mA
Power supply current (VDD3 )
IDD
80MHz

200

mA
At sleep power supply
current(VDD3 )
ISLEEP
80MHz

20

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
26
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
40MHz No-load

36

mA
Power supply current (VDD3 )
IDD
80MHz

200

mA
At sleep power supply
current(VDD3 )
ISLEEP
80MHz

20

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
MB86830 Series
(3)MB86832-66 (Maximum internal operation frequency:66 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

40

mA
Power supply current (VDD3 )
IDD
66 MHz

200

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
Symbol
(VDD5 = VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

30

mA
Power supply current (VDD3 )
IDD
66 MHz

200

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
27
MB86830 Series
(4)MB86832-80 (Maximum internal operation frequency:80 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
40MHz No-load

50

mA
Power supply current (VDD3 )
IDD
80MHz

250

mA
At sleep power supply
current(VDD3 )
ISLEEP
80MHz

20

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
28
Symbol
(VDD5 = VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
40MHz No-load

36

mA
Power supply current (VDD3 )
IDD
80MHz

250

mA
At sleep power supply
current(VDD3 )
ISLEEP
80MHz

20

mA
Capacity of pins
CPIN
VDD5= VI = 0
f = 1 MHz


16
pF
MB86830 Series
(5)MB86832-100 (Maximum internal operation frequency:100 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33MHz No-load

40

mA
Power supply current (VDD3 )
IDD
100MHz

300

mA
At sleep power supply
current(VDD3 )
ISLEEP
100MHz

25

mA
Capacity of pins
CPIN
VDD5= VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
Symbol
(VDD5 = VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33MHz No-load

30

mA
Power supply current (VDD3 )
IDD
100MHz

300

mA
At sleep power supply
current(VDD3 )
ISLEEP
100MHz

25

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
29
MB86830 Series
(6)MB86833 (Maximum internal operation frequency:66 MHz)
• 5.0 V interface
(VDD5 = 5.0 V ± 5%, VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 4 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 4 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

40

mA
Power supply current (VDD3 )
IDD
66 MHz

120

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
• 3.3 V interface
Parameter
30
Symbol
(VDD5 = VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

30

mA
Power supply current (VDD3 )
IDD
66 MHz

120

mA
At sleep power supply
current(VDD3 )
ISLEEP
66 MHz

15

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
MB86830 Series
(7)MB86834-108 (Maximum internal operation frequency:108 MHz)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

0.8
V
“H” level input voltage
VIH

2.0

VDDE
V
“L” level output voltage
VOL
IOL = 2.0mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2.0mA
VDDE − 0.4

VDDE
V
Input leakage current
ILI
VIN = 0 or VDDE
−5

5
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDDE
−5

5
µA
Power supply current (VDD5 )
IDD
33 MHz No-load

30

mA
Power supply current (VDD3 )
IDD
108 MHz

250

mA
At sleep power supply
current(VDD3 )
ISLEEP
108 MHz

20

mA
Capacity of pins
CPIN
VDDE = VI = 0
f = 1 MHz


16
pF
(8)MB86834-120 (Maximum internal operation frequency:120 MHz)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

0.8
V
“H” level input voltage
VIH

2.0

VDDE
V
“L” level output voltage
VOL
IOL = 2.0mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2.0mA
VDDE − 0.4

VDDE
V
Input leakage current
ILI
VIN = 0 or VDDE
−5

5
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDDE
−5

5
µA
Power supply current (VDD5 )
IDD
40 MHz No-load

36

mA
Power supply current (VDD3 )
IDD
120 MHz

280

mA
At sleep power supply
current(VDD3 )
ISLEEP
120 MHz

23

mA
Capacity of pins
CPIN
VDDE = VI = 0
f = 1 MHz


16
pF
31
MB86830 Series
(9)MB86835 (Maximum internal operation frequency:84 MHz)
(VDD5 = VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

VDD3 × 0.25
V
“H” level input voltage
VIH

VDD3 × 0.65

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.5

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
− 10

10
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
− 10

10
µA
Power supply current
(VDD5 + VDD3)
IDD
84 MHz No-load

200

mA
At sleep power supply
current (VDD3 )
ISLEEP
84 MHz

20

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
(10)MB86836-90 (Maximum internal operation frequency:90 MHz)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
32
“L” level input voltage
VIL

0

0.8
V
“H” level input voltage
VIH

2.0

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.4

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
−5

5
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
−5

5
µA
Power supply current
(VDD5 = 3.3 V)
IDD
40 MHz No-load

36

mA
Power supply current
(VDD3 = 2.5 V)
IDD
90 MHz

180

mA
At sleep power supply
current
ISLEEP
90 MHz

17

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
MB86830 Series
(11)MB86836-108 (Maximum internal operation frequency:108 MHz)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
“L” level input voltage
VIL

0

0.8
V
“H” level input voltage
VIH

2.0

VDD5
V
“L” level output voltage
VOL
IOL = 2 mA
0

0.4
V
“H” level output voltage
VOH
IOH = − 2 mA
VDD5 − 0.4

VDD5
V
Input leakage current
ILI
VIN = 0 or VDD5
−5

5
µA
Trial state output leakage
current
ILZ
VOUT = 0 or VDD5
−5

5
µA
Power supply current
(VDD5 = 3.3 V)
IDD
40 MHz No-load

36

mA
Power supply current
(VDD3 = 2.5 V)
IDD
108 MHz

200

mA
At sleep power supply
current
ISLEEP
108 MHz

20

mA
Capacity of pins
CPIN
VDD5 = VI = 0
f = 1 MHz


16
pF
33
MB86830 Series
4. AC Characteristics
All are provided by CLKIN (BUS clock), and the AC characteristic does not depend on the frequency of the operation in CPU.
(1)MB86831-66/MB86832-66/MB86833 (Maximum internal operation frequency:66 MHz)
(VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
ClassificaVDD5 = 3.3 V ± 0.3 V Unit
Parameter
Symbol
VDD5 = 5.0 V ± 5%
tion
Min.
Max.
Min.
Max.
CLK
CLKIN cycle time

30
100
30
100
ns
CLKIN high time

10

10

ns
CLKIN low time

10

10

ns
CLKIN rising time


3

3
ns
CLKIN falling time


3

3
ns

20

20
ns
2

2

ns

20

21
ns
2

2

ns

20

21
ns
2

2

ns

20

21
ns
2

2

ns

20

21
ns
2

2

ns

20

21
ns
2

2

ns

18

19
ns
2

2

ns

18

19
ns
2

2

ns

18

19
ns
2

2

ns

20

21
ns
2

2

ns

18

19
ns
2

2

ns

18

19
ns
2

2

ns

18

19
ns
2

2

Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
34
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
ns
(Continued)
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Delay time
Output
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External Input setup time
bus master
Hold time
input
Setup time
Hold time
Setup time
Hold time
Symbol
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.3 V
Unit
Min.
Max.
Min.
Max.
RDYOUT#
(Internal ready
mode)

20

21
ns
2

2

ns
RDYOUT# *
(External ready
mode)

15

15
ns
2

2

ns

20

21
ns
2

2

ns

20

21
ns
2

2

ns
14

14

ns
2

2

ns
14

14

ns
2

2

ns
14

14

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
(Continued)
35
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Delay time
DRAMC
output
Hold time
Delay time
Hold time
Delay time
Hold time
Symbol
RAS0# to RAS3#
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
Setup time
IRC input
Hold time
“H” level period
“L” level period
P:Period (Cycle time)
IRQ15 to IRQ8
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.3 V
Unit
Min.
Max.
Min.
Max.

15

15
ns
2

2

ns

15

15
ns
2

2

ns

15

15
ns
2

2

ns

15

15
ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
2 × P + 10

2 × P + 10

ns
2 × P + 10

2 × P + 10

ns
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40-MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
36
MB86830 Series
(2)MB86831-80/MB86832-80 (Maximum internal operation frequency:80 MHz)
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
ClassificaParameter
Symbol
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V Unit
tion
Min.
Max.
Min.
Max.
CLK
CLKIN cycle time

25
100
25
100
ns
CLKIN high time

8

8

ns
CLKIN low time

8

8

ns
CLKIN rising time


3

3
ns
CLKIN falling time


3

3
ns

16

20
ns
2

2

ns

18

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

16

21
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

16

19
ns
2

2

ns

16

21
ns
2

2

ns
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
RDYOUT#
(Internal ready
mode)
(Continued)
37
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External Input setup time
bus master
Hold time
input
Setup time
Hold time
Setup time
Hold time
38
Symbol
RDYOUT# *
(External ready
mode)
ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V
Unit
Min.
Max.
Min.
Max.

14

15
ns
2

2

ns

14

21
ns
2

2

ns

14

21
ns
2

2

ns
10

10

ns
2

2

ns
10

10

ns
2

2

ns
12

12

ns
2

2

ns
10

10

ns
2

2

ns
10

10

ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
(Continued)
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Delay time
DRAMC
output
Hold time
Delay time
Hold time
Delay time
Hold time
Symbol
RAS0# to RAS3#
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
Setup time
IRC input
Hold time
“H” level period
“L” level period
IRQ15 to IRQ8
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V
Unit
Min.
Max.
Min.
Max.

12

15
ns
2

2

ns

12

15
ns
2

2

ns

12

15
ns
2

2

ns

12

15
ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
2 × P + 10

2 × P + 10

ns
2 × P + 10

2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40-MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
39
MB86830 Series
(3)MB86832-100 (Maximum internal operation frequency:100 MHz)
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
ClassificaParameter
Symbol
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V Unit
tion
Min.
Max.
Min.
Max.
CLK
CLKIN cycle time

25
100
25
100
ns
CLKIN high time

10

10

ns
CLKIN low time

10

10

ns
CLKIN rising time


3

3
ns
CLKIN falling time


3

3
ns

16

20
ns
2

2

ns

18

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

16

21
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

16

21
ns
2

2

ns

14

19
ns
2

2

ns

14

19
ns
2

2

ns

16

19
ns
2

2

ns

16

21
ns
2

2

ns
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
RDYOUT#
(Internal ready
mode)
(Continued)
40
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External
bus master input
Input Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Symbol
RDYOUT# *
(External ready
mode)
ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V
Unit
Min.
Max.
Min.
Max.

14

15
ns
2

2

ns

14

21
ns
2

2

ns

14

21
ns
2

2

ns
10

10

ns
2

2

ns
10

10

ns
2

2

ns
12

12

ns
2

2

ns
10

10

ns
2

2

ns
10

10

ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
12

12

ns
2

2

ns
(Continued)
41
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Delay time
DRAMC
output
Hold time
Delay time
Hold time
Delay time
Hold time
Symbol
RAS0# to RAS3#
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
Setup time
IRC input
Hold time
“H” level period
“L” level period
IRQ15 to IRQ8
VDD5 = 5.0 V ± 5%
VDD5 = 3.3 V ± 0.15 V
Unit
Min.
Max.
Min.
Max.

12

15
ns
2

2

ns

12

15
ns
2

2

ns

12

15
ns
2

2

ns

12

15
ns
2

2

ns
Asynchronous
Asynchronous
ns
Asynchronous
Asynchronous
ns
2 × P + 10

2 × P + 10

ns
2 × P + 10

2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40-MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
42
MB86830 Series
(4)MB86834-108,-120
Classification
CLK
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
CLKIN cycle time

25
40
ns
CLKIN high time

8

ns
CLKIN low time

8

ns
CLKIN rising time


3
ns
CLKIN falling time


3
ns

20
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
(Continued)
43
MB86830 Series
(Continued)
Classification
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
Delay time
Hold time
Delay time
Output
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External
bus master input
Input setup time
Hold time
Setup time
Hold time
Setup time
Hold time
RDYOUT#
(Internal ready mode)
RDYOUT# *
(External ready mode)
ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#

21
ns
2

ns

15
ns
2

ns

21
ns
2

ns

21
ns
2

ns
10

ns
2

ns
10

ns
2

ns
12

ns
2

ns
10

ns
2

ns
10

ns
2

ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
(Continued)
44
MB86830 Series
(Continued)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
Classification
Delay time
Hold time
Delay time
DRAMCoutput
Hold time
Delay time
Hold time
Delay time
Hold time
RAS0# to RAS3#
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
Setup time
IRC input
Hold time
“H” level period
IRQ15 to IRQ8
“L” level period

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns
Asynchronous
ns
Asynchronous
ns
2 × P + 10

ns
2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40 MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
45
MB86830 Series
(5)MB86835
Classification
CLK
(VDD5 = VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
MB86835
Unit
Min.
Max.
CLKIN cycle time

25
100
ns
CLKIN high time

8

ns
CLKIN low time

8

ns
CLKIN rising time


3
ns
CLKIN falling time


3
ns

20
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Symbol
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
(Continued)
46
MB86830 Series
(Continued)
Classification
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Delay time
Hold time
Delay time
Output
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External
bus master input
Input setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Symbol
MB86835
Unit
Min.
Max.
RDYOUT#
(Internal ready mode)

21
ns
2

ns
RDYOUT# *
(External ready mode)

15
ns
2

ns

21
ns
2

ns

21
ns
2

ns
10

ns
2

ns
10

ns
2

ns
12

ns
2

ns
10

ns
2

ns
10

ns
2

ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#
ns
(Continued)
47
MB86830 Series
(Continued)
(VDD3 = 3.3 V ± 0.15 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Classification
Parameter
Symbol
Delay time
RAS0# to RAS3#
Hold time
Delay time
DRAMC
output
MB86835
CAS0# to CAS3#
Hold time
Delay time
DWE0# to DWE3#
Hold time
Delay time
DOE#
Hold time
Setup time
IRC nput
Hold time
IRQ15 to IRQ8
“H” level period
“L” level period
Unit
Min.
Max.

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns
Asynchronous
ns
Asynchronous
ns
2 × P + 10

ns
2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40 MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
• An AC characteristic of pins and internal maximum operation frequency is separately defined.
• The maximum operation frequency of an external bus is 40MHz though the maximum internal operation
frequency are 80 MHz or 100 MHz (CLKIN Min.=25ns).Therefore,when an external bus is used with 40MHz,
an internal frequency are 84 MHz and 100 MHz.
• Relation between external bus clock and internal clock
CLKIN
48
MB86835(84MHz)
×1
×2
×3
×4
×5
20 MHz
20 MHz
40 MHz
60 MHz
80 MHz
N/A
33.3 MHz
33.3 MHz
66.6 MHz
N/A
N/A
N/A
40 MHz
40 MHz
80 MHz
N/A
N/A
N/A
MB86830 Series
(6)MB86836-90,-108(Preliminary)
Classification
CLK
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
CLKIN cycle time

25
40
ns
CLKIN high time

8

ns
CLKIN low time

8

ns
CLKIN rising time


3
ns
CLKIN falling time


3
ns

20
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns

21
ns
2

ns

19
ns
2

ns

19
ns
2

ns

19
ns
2

ns
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
D<31:0>
ADR<27:2>
BE0# to BE3#
ASI<3:0>
CS0# to CS5#
SAMEPAGE#
RDWR#
LOCK#
AS#
OVF#
BGRNT#
PBREQ#
BMREQ#
(Continued)
49
MB86830 Series
(Continued)
Classification
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
Delay time
Hold time
Delay time
Output
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
External
bus master input
Input setup time
Hold time
Setup time
Hold time
Setup time
Hold time
RDYOUT#
(Internal ready mode)
RDYOUT# *
(External ready mode)
ERROR#
PDOWN#
READY#
MEXC#
D<31:0>
BREQ#
BMACK#
IRL<3:0>
WKUP#
RDWR#
AS#
ASI<3:0>
ADR<27:2>
BE2#

21
ns
2

ns

15
ns
2

ns

21
ns
2

ns

21
ns
2

ns
10

ns
2

ns
10

ns
2

ns
12

ns
2

ns
10

ns
2

ns
10

ns
2

ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
Asynchronous
ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
12

ns
2

ns
(Continued)
50
MB86830 Series
(Continued)
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Unit
Min.
Max.
Classification
Delay time
RAS0# to RAS3#
Hold time
Delay time
DRAMCoutput
CAS0# to CAS3#
Hold time
Delay time
DWE0# to DWE3#
Hold time
Delay time
DOE#
Hold time
Setup time
IRC input
Hold time
IRQ15 to IRQ8
“H” level period
“L” level period

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns

15
ns
2

ns
Asynchronous
ns
Asynchronous
ns
2 × P + 10

ns
2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40 MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
• An AC characteristic of pins and internal maximum operation frequency is separately defined.
• The maximum operation frequency of an external bus is 40MHz though the maximum internal operation
frequency are 90 MHz or 100 MHz (CLKIN Min.=25ns).Therefore,when an external bus is used with 40MHz,
an internal frequency is 80 MHz
• Relation between external bus clock and internal clock
MB86836(90MHz)
MB86836(108MHz)*
CLKIN
×1
×2
×3
×4
×5
×1
×2
×3
×4
×5
27 MHz
27 MHz
54 MHz
33.3 MHz 33.3 MHz 66.6 MHz
81 MHz
N/A
N/A
N/A
N/A
N/A
27 MHz
54 MHz
33.3 MHz 66.6 MHz
81 MHz
108 MHz
N/A
100MHz
N/A
N/A
36 MHz
36MHz
72 MHz
N/A
N/A
N/A
36MHz
72 MHz
108MHz
N/A
N/A
40 MHz
40 MHz
80 MHz
N/A
N/A
N/A
40 MHz
80 MHz
N/A
N/A
N/A
*: MB86836 108MHz version is under developement.
51
MB86830 Series
■ TIMING DIAGRAM
• Reset timing
CLKIN
RESET#
Longer than four clock cycle
Note : CLKIN is steady, and raise reset input "H", please after at least 100msec.
• Input/output timing 1
CLKIN
Input pins
Setup
Hold
Valid delay
Hold
Valid delay
Hold
Outpou pins
Setup
Input/output
pins
Hold
Input data
Output data
Input pins
: BREQ#, BMACK#
Outpou pins : BE0# to BE1#, BE3#, CS0# to CS5#, SAMEPAGE#, LOCK#, OVF#, BGRNT#, PBREQ#, BMREQ#,
ERROR#, PDOWN#, RAS0# to RAS3#, CAS0# to CAS3#, DWE0# to DWE3#, DOE#
Input/output pins : D<31: 0>, ASI<3: 0>, RDWR#, BE2#
52
MB86830 Series
• Input/output timing 2
CLKIN
Input pins
Hold
Setup
Valid delay
Hold
Output pins
Hold
Hold
Setup
Input/Output
pins
Valid delay
Input data
Output data
Imput pins : READY#, MEXC#
Output pins : RDYOUT# (internal ready mode)
Input/output pins : ADR<27: 2>
• Input/output timing 3
CLKIN
Hold
Hold
Setup
AS#
Valid delay
Input data
Output data
• Input/output timing 4
READY#
Valid delay
Hold
RDYOUT#
(External ready mode)
53
MB86830 Series
■ ARCHITECTURE
The MB86830 series is a line of 32-bit RISC processors running at an operating frequency of 100 MHz, providing
high performance of 121 VAX-MIPS. As products belong to the Fujitsu SPARClite family, the MB86830 series is
based on the SPARC architecture and are thus upward code-compatible with the conventional products in the
SPARClite family. The MB86830 series was developed in particular for embedded applications, providing high performance and high level of integration when used as embedded controllers.
The MB86830 series has an efficient set of instructions and is hardwired so that most of them can be executed in
one cycle. The IU (integer unit) features five pipelined execution stages designed for processing data interlocks,
providing a branch handler optimized for for efficient transition of control and a bus interface for processing onecycle bus access for on-chip memory.
The internal register file consisting of a stack of eight windows, made up of 136 registers in total, speeds up interrupt response and context switching. The register file minimizes memory access during procedure linkage and
facilitates parameter passing and variable assignment.
The MB86830 series contains instruction and data caches to isolate processor operation from external memory.
These caches are designed for highest flexibility so that it can lock each entry to improve the performance of the
entire system.
The independent instruction and internal data buses serve as high-bandwidth interfaces between the IU (integer
unit) and the on-chip caches. These buses support single-cycle instruction execution and single-cycle data transfer between the IU and caches in parallel.
The MB86830 series incorporates an integer multiplier and auxiliary hardware for division. The MB86830 series
can therefore execute 32-bit integer multiplication in five cycles, 16-bit integer multiplication in three cycles, 8-bit
integer multiplication in two cycles, and integer multiplication by 0 in one cycle.
1. Main Features
(1)High-speed execution of instructions
Most of the instructions in most programs are simple, designing the programs so as to execute such simple instructions as fast as possible dramatically improves the program execution time.
(2)High-capacity register set
The register set reduces the number of required accesses to data memory. Registers are organized into a stack
of groups called register windows, allowing themselves to be used efficiently for high-priority tasks such as interrupt
services and operating system working registers. A stack of (overlapping) register windows also contributes to simplifying parameter passing during procedure linkage, thereby reducing the code size of most programs.
(3)On-chip caches
The MB86830 series incorporates data and instruction caches so that the processor can work independently of the
slower memory subsystem. These caches are implemented in two-way set-associative configuration on the
MB86831/832; they are directly mapped on the MB86833.
(4)Locking entries in caches
The MB86830 series can lock both of data and instruction entries in their respective caches, ensuring high performance in processing important or frequently called routines. Each cache offers maximum flexibility so that entries
can be locked in all or selective part of the cache.
(5)Bus interface
The MB86830 series supports programmable chip selection, a wait state generator, and fast page mode DRAM,
minimizing the necessity of connecting external circuits.
(6)On-chip DRAM controller
The on-chip DRAM controller supports fast page mode and EDO DRAMs. It also controls self-refreshing of DRAM
in sleep mode (low power consumption mode).
54
MB86830 Series
(7)On-chip interrupt controller
The on-chip interrupt controller accepts interrupt inputs through eight channels, allowing a trigger mode to be set
independently for each of the channels. The interrupt request accepted according to the trigger mode is encoded
and output to the processor.
(8)Multiplier circuit
The MB86830 series incorporates a multiplier circuit which can be selectively set to an operating clock frequency
of x1, x2, x3, x4,or x5 of the external clock frequency, allowing the processor to run at high speed.
(9) Instruction set
The MB86830 series supports high-speed integer multiply instructions which are executed in five, three, and two
cycles respectively for 32-, 16-, and 8-bit multiplications. The integer divide step instruction is near 10 times faster
in divide time than the previous SPARC implementation. The scan instruction supports the function for detecting
1 or 0 at the MSB in a word in a single cycle.
2. CPU
The CPU core of the MB86830 series is a high-performance version implemented by full custom design of the
SPARC architecture. The CPU core contains a compact circuitry for integrating peripheral circuits, designed to be
customizable to a variety of applications. The CPU core consists of three function units: instruction, address, and
execution blocks (see “Integer operation unit internal block diagram”).
The role of five execution stages for instruction pipelining is to decode all instructions and generate control signals
for other blocks. The five pipelined stages are the fetch (F), decode (D), execute (E), memory (M), and write back
(W) stages. The instruction memory returns an instruction addressed at stage (F), the register file returns an operand addressed at stage (D), the ALU perform calculation to obtain the result at stage(E), the external memory is
addressed at stage(M), and the register file is written back at stage (W).
55
MB86830 Series
• Integer operation unit internal block diagram
I data
Register file
ir
adder
read1
read2
A
B
read3
write
inc (+4)
e_ir
0
m_ir
w_ir
TBR
pc
ALU / Shifter
d_pc
R
W
e_pc
PSR/WIM/Y
Data address
st_align
Id_align
m_pc
Instruction
block
(I block)
Address block
(A block)
I address
Execution block
(E block)
D address
D data
3. Address Space
The MB86830 series has a wide addressable range in which user and supervisor spaces can be defined independently. Of 30 lines of addresses, eight lines of address space identifiers (ASI) are used to distinguish between
protected and unprotected spaces. Tow of 256 different ASI values are used to define the user data and user instruction spaces; the rest are used to define the supervisor space.
When a reset, synchronous trap, or asynchronous trap occurs, the processor enters the supervisor mode. In the
supervisor mode, the processor executes instructions in the supervisor space and transfers data. The processor
can access other ASI values even when staying in the supervisor mode. The processor can use the remaining ASI
values, excluding the reserved values, to allocate other spaces as application definable spaces.
By distinguishing between the user and supervisor spaces, hardware can prevent inadvertent or unauthorized access to system resources. When a real-time operating system (RTOS) is developed, for example, individual spaces provide the mechanism for separating the RTOS space efficiently from the user space.
4. Registers
The register set of the MB86830 series is made up of the registers to be used for general-purpose functions and
those to be used for control and status report purpose. The MB86830 series has 136 general-purpose registers
divided into eight global registers and a stack of eight register blocks (register windows). Each register window
incorporates 24 registers, of which eight registers are local to that window, eight “out” registers are overlapping the
next register window, and eight “in” registers are overlapping the previous register window. (See “General register
composition”.)
This register configuration allows a parameter to be passed to a subroutine. The next register window is made
56
MB86830 Series
available b writing the parameter to be passed to the “out” register and using a procedure call to decrement the
window pointer by one. The passed parameter remains in the “in“ registers in the current register window and can
be used by that subroutine.
Register windows improve the performance of embedded applications. This is because these windows serve as
the local variable caches for storing interrupt, subroutine, context, or operating system variables without increasing
overhead. In addition, the code size of programs can be reduced by using an efficient method of executing procedure linkage without optimizing the code using an inlining compiler.
The register file consists of 4-port registers: 3-port read and 1-port write registers. Even the store instruction can
therefore be executed in one cycle, which requires three operands to be read from the register file.
The control and status registers are divided into those defined in the SPARC architecture and those mapped into
the alternate address space for controlling the functions of peripheral devices.
• General register composition
W7
ins
locals
outs
outs
W1
WIM
ins
locals
ins
locals
W0
W6
locals
restore
ins
CWP
outs
ins
outs
save
outs
W2
locals
ins
locals
W4
outs
locals
W5
ins
outs
outs
locals
ins
W3
57
MB86830 Series
5. Instruction Set
The MB86830 series is upward code-compatible with other SPARC processors. The MB86830 series now supports additional instructions to improve performance, which were previously not directly supported. In addition to
a set of already supported SPARC instructions, the MB86830 series has been provided with the integer multiply
and integer divide step instructions as well as the scan instruction for detecting “1” or “0” at the MSB.
For the list of supported instructions, see the instruction set below.
• Instruction set
LOGICAL
ARITHMETIC/SHIFT
DATA MOVEMENT
CONDITION CODES UNCHANGED
TO USER/SUPERVISOR SPACE SIGNED
ADD
LOAD BYTE
SUBTRACT
LOAD HALF-WORD
MULTIPLY (SIGNED/UNSIGNED)
LOAD WORD
SCAN
LOAD DOUBLE WORD
SETHI
STORE BYTE
SHIFT LEFT LOGICAL
STORE HALF-WORD
SHIFT RIGHT LOGICAL
STORE WORD
SHIFT RIGHT ARITHMETIC
STORE DOUBLE WORD
CONDITION CODES SET
TO USER SPACE UNSIGNED
ADD
LOAD BYTE
SUBTRACT
LOAD HALF-WORD
MULTIPLY (SIGNED/UNSIGNED)
TO ALTERNATE SPACE SIGNED
MULTIPLY STEP
LOAD BYTE
DIVIDE STEP
LOAD HALF-WORD
EXTENDED AND CONDITION CODES
LOAD WORD
CONTROL TRANSFER
UNCHANGED
LOAD DOUBLE WORD
ADD
STORE BYTE
CONDITIONAL BRANCH
SUBTRACT
STORE HALF-WORD
CONDITIONAL TRAP
EXTENDED AND CONDITION CODES SET
STORE WORD
CALL
ADD
STORE DOUBLE WORD
RETURN
SUBTRACT
TO ALTERNATE SPACE UNSIGNED
SAVE
TAGGED AND CONDITION CODES SET
LOAD BYTE
RESTORE
(WITH AND WITHOUT TRAP ON OVERFLOW)
LOAD HALF-WORD
JUMP AND LINK
ADD
ATOMIC OPERATION IN USER SPACE
SUBTRACT
SWAP WORD
READ/WRITE CONTROL REGISTER
LOAD/STORE UNSIGNED BYTE
ATOMIC OPERATION IN
READ PSR
READ WIM
RDASR
ALTERNATE SPACE
WRITE PSR
WRITE WIM
WRASR
SWAP WORD
READ TBR
READ Y
LOAD/STORE UNSIGEND BYTE
WRITE TBR
WRITE Y
CONDITION CODES UNCHANGED
AND
OR
XOR
AND
NOT
OR NOT
XNOR
CONDITION CODES SET
AND
OR
XOR
AND NOT
OR NOT
XNOR
6. Interrupts
One of the key criteria to determine whether a processor is suitable for embedded applications is whether the processor can completely service interrupts within the minimum interrupt processing time. The processors implemented as the MB86830 series guarantee not only short average wait time but also short maximum wait time.
The interrupt response time is the sum of the time for the processor to complete the current task after recognizing
an interrupt and the time for the processor to start executing the interrupt service routine. The MB86830 series
offers a variety of functions to minimize the both factors.
To minimize the time to complete the current task, the MB86830 series is designed so that the task can be interrupted easily or it can be completed in a minimum of cycles. For this purpose, the MB86830 series implements
the cache system that updates only one word at a time using a prefetch buffer when a cache miss occurs, interruptible integer division using a divide step instruction, high-speed multiplication using a multiplier, and a 4-word
write buffer for processing a pending bus transaction.
To minimize the time required for starting executing the interrupt service routine, the processor switches the register window to a new one upon detection of an interrupt. This function allows the service routine to be executed
58
MB86830 Series
without saving the current register in advance. The user can also lock the service routine in the cache, allowing
faster processing with the routine. At this time, the on-chip data cache can be used as a high-speed local stack to
minimize the delay in accessing the routine variable in the service routine.
The MB86830 series has a maximum of 15 interrupt levels to directly support 15 interrupt sources. The highest
interrupt level is nonmaskable.
7. Caches
The MB86830 series incorporates independent data and instruction caches, allowing a high-performance system
to be constructed without the need for high-speed external memory or relevant control logics. The caches are
mapped onto physical addresses.
The instruction cache consists of: 64 units/2 banks on the MB86831/835, 128 units/2 banks on the MB86832/836,
256 units/2 banks on a 32-byte line on the MB86834, and 64 units/1 bank on a 16-byte line on the MB86833. The
data cache consists of: 64 units/2 banks on the MB86831/835, 64 units/1 bank on a 16-byte line on the MB86833,
128 units/2 banks on the MB86832/836, and 256 units/2 banks on a 32-byte line on the MB86834. (See “The composition of the data cache” and “The composition of the instruction cash.”) Each line is divided into 4-byte subblocks. When a cache miss occurs, the cache is updated in one word (4 bytes) or four words (16 bytes), selectively.
Updating the cache in one word eliminates the wait time for an interrupt generated for replacing a long cache line;
updating the cache in four words can result improvement in cache hit rate.
Updating the cache in four words uses the burst mode. The instruction prefetch buffer fetches the next instruction
in advance, assuming that it corresponds to the next instruction cache miss.
The caches can be used in the normal mode or in either of two lock modes. In the normal mode, the cache in twoway set-associative configuration replaces one of two corresponding entries using the LRU (Least Recently Used)
algorithm. As an alternate method, the entire cache or only the selected entry can be locked depending on the lock
mode in use. The lock mode can lock a time-critical routine in the cache. The global cache lock mode locks the
entries in the entire instruction or data cache.
The two control bits in the cache control register enable or disable the lock in the instruction and data caches. Once
an entire cache is locked, any valid entry in the cache cannot be replaced. To ensure optimum performance, however, an invalid entry is updated when it is accessed. This update is performed automatically without generating
time penalty.The instruction or data entry selected by local cache locking can be locked automatically in the corresponding cache. This mechanism can ensure the fastest response from a certain important interrupt routine by
locking the code of the routine in the cache.
Also, of those routines which can be removed from the cache, frequently used ones should be given priority in performance in some cases. In such cases, the entries can be locked.
The local cache lock mode can lock individual entries or lock entries automatically by hardware. To lock each entry,
the lock bit in the corresponding cache tag line is set by software. For automatic cache locking, the lock function
is enabled or disabled depending on the bit in the corresponding cache control register. The enable/disable bit is
set at the beginning of the routine for which the entry is to be locked. The location of cache access generated with
the bit enabling the lock function is locked in the cache. Automatic cache locking does not involve overhead other
than the initial setting cycle.
When a cache entry is unlocked, the data cache assign the cache entry only at load time based on the writethrough update policy. The write operation is buffered and the processor can continue execution while data is being written back to memory. In contrast, the data written to the locked data cache location is not written to main
memory.
The above method reduces external bus access and allows part of the data cache to be used as on-chip RAM
which is not mapped into external memory.
The data and instruction caches are designed to be accessed through the independent data and instruction buses
to load/write data from/to the cache at a maximum speed of 1 CPI (Clock/Instruction).
59
MB86830 Series
• The composition of the data cache (For MB86832).
SET 2
SET 1
31
12
0
8 entry
0
Address tag
Lock, valid, LRU
.
.
Sub-block
.
.
(Entry)
(Tag)
127
Address tag
• The composition of the instruction cash (For MB86832).
SET 2
SET 1
31
12
0
8 entry
0
Address tag
Lock, valid, LRU
.
.
Sub-block
.
.
(Tag)
Address tag
(Entry)
127
8. Bus Interface
The bus interface unit (BIU) is designed to simplify the interface between the MB86830 series and other parts of
the system. The non-multiplexed address bus and data bus allow a high-speed system to be constructed easily.
Also, the internal circuitry allows such a system to be constructed with a minimum of external hardware.
The bus interface supports programmable wait state generation, chip select output by address decoding, samepage detection for supporting page mode DRAM, booting from 8/16/32-bit memory, and a automatic reload timer
for refreshing DRAM. In addition, the burst mode can be used to perform cache line fill operation at high speed.
9. DRAM Controller
With the DRAM controller controlling DRAM, the MB86830 series can write/read data to/from DRAM. The DRAM
controller can control up to four banks on the MB86831/832/834 or only one bank on the MB86833/835. The fast
page mode, DRAM mode, or EDO DRAM mode can be selected depending on the register setting. The DRAM
60
MB86830 Series
controller also controls the RAS and CAS to place DRAM in the self-refresh mode when the processor enters the
sleep mode (low power consumption mode).
The MB86836 has no DRAM controller.
10. Interrupt Controller (IRC)
The interrupt controller (IRC) accepts interrupts inputs through eight channels, depending on the trigger mode and
mask bit set for each of the channels. When accepting an interrupt, the interrupt controller encodes it according
to the interrupt priority level and outputs the interrupt level to the processor. The interrupt level remains held unless
it is cleared by the processor. The processor is not therefore informed of the next interrupt.
11. Multiplier Circuit
The CLKSEL0, CLKSEL1, and CLKSEL2 pins can be used to select the multiplier circuit to be used. The ×1, ×2,
×3, ×4, or ×5 multiplier circuits are supported, which allow the processor to run faster.
12. IU (Integer Unit) Dedicated Registers (Not Memory Mapped)
(1)Processor Status Register (PSR)
bit→
31
28 27
0 0 0 0H
bit 23 to bit 20
bit 19 to bit 12
bit 11 to bit 8
bit 7
bit 6
bit 5
bit 4 to bit 3
bit 2 to bit 0
24 23
1 1 1 1H
20 19
icc
n
z
v
c
12 11
Reserved
8
PIL
7
S
6
5
4
3 2
PS ET Reserved
0
CWP
:Integer condition code [icc] (n:Negative = 1, z:Zero = 1, v:Overflow = 1, c:Carry = 1)
:Reserved[“0”Write, Don’t care for read]
:Processor Interrupt Level [PIL] (Value = 1 to 15, RST = X)
:Supervisor Mode [S] (Supervisor = 1, User = 0, RST = 1)
:Prior S Mode [PS]
:Enable Trap [ET] (Enable = 1, Disable = 0, RST = 0)
:Reserved [“0”Write, Don’t care for read]
:Current Window Point [CWP] (Value = 0 to 7, RST = X)
X:Don’t care
(2)Window Invalid Mask Register (WIM)
bit→
31
8
Reserved
bit 31 to bit 8
bit 7 to bit 0
7
6
5
4
3
2
1
0
w7 w6 w5 w4 w3 w2 w1 w0
:Reserved [“0”Write, Don’t care for read]
:Window mask [w7 to w0] (Invalid = 1, Valid = 0, RST = X)
X:Don’t care
(3)Trap Base Register (TBR)
bit→
31
12
TBA
11
4
tt
3
0
0000
bit 31 to bit 12 :Trap base address [TBA] (RST = X)
bit 11 to bit 4 :Trap type [tt] (RST = X)
X:Don’t care
61
MB86830 Series
(4)Y Register (Y)
bit→
31
0
(5)Ancillary State Register 17 (ASR17)
bit→
31
1
Reserved
bit 31 to bit 1
bit 0
0
SVT
:Reserved [“0”Write, Don’t care for read]
:Single Vector Trapping [SVT] (Enable = 1, Disable = 0, RST = 0)
13. IU (Integer Unit) General-Purpose Registers (Not Memory Mapped)
The IU (integer unit) contains 136 32-bit general-purpose registers for holding arguments for operations and their
results. Of these registers, only 32 registers can be accessed through blocks called register windows.
The integer unit has eight register windows. The register window to be used is determined by the CWP bits (bits
2 to 0) in the Processor Status Register (PSR). Each register window consists of eight global registers available
commonly to all register windows and 24 registers (in-register × 8, local register × 8, out-register × 8). The in-registers and out-registers are used commonly between adjacent register windows.
(1)Zero Register (r0)
bit→
31
0
0
bit 31 to bit 0
:0
(2)General register (r1 to r31)
bit→
31
0
Don’t care at reset.
14. Bit map of register with built-in CPU core
(1)Cache/BIU Control Register (CBIR)
bit→
31
ASI= 0x01, Address= 0x00000000H
10 9
8 7 6 5 4 3 2 1 0
Reserved
bit 31 to bit 10
bit 9 to bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
62
:Reserved [“0”Write, Don’t care for read]
:Non-cacheable Wait-state [Don’t care for read]
:Cacheability Enable [Don’t care for read] (Enable = 1, Disable = 0, RST = 0)
:Reserved [“0”Write, Don’t care for read]
:Write Buffer Enable (Enable = 1, Disable = 0, RST = 0)
:Prefetch Buffer Enable (Enable = 1, Disable = 0, RST = 0)
:Data Cache Lock (Lock = 1, Unlock = 0, RST = 0)
:Data Cache Enable (Enable = 1, Disable = 0, RST = 0)
:Instruction Cache Lock (Lock = 1, Unlock = 0, RST = 0)
:Instruction Cache Enable (Enable = 1, Disable = 0, RST = 0)
MB86830 Series
(2)Lock Control Register (LCR)
bit→
ASI= 0x01, Address= 0x00000004H
31
2
1
0
Reserved
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Cache Entry Auto Lock (Enable = 1, Disable = 0, RST = 0)
:Instruction Cache Entry Auto Lock (Enable = 1, Disable = 0, RST = 0)
ASI = 0x01, Address = 0x00000008H
(3)Lock Control Save Register (LCSR)
bit→
31
2
1
0
Reserved
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Previous Data Cache Auto Lock (Off = 0, On = 1, RST = 0)
:Previous Instruction Cache Auto Lock (Off = 0, On = 1, RST = 0)
ASI = 0x01, Address = 0x00000010H
(4)Restore Lock Control Register (RLCR)
bit→
31
1
0
Reserved
bit 31 to bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Restore Lock Control Register (Restore = 1, Ignore = 0, RST = 0)
ASI = 0x01, Address = 0x00000020H
(5)Bus Control Register (BCR)
bit→
31
2
1
0
Reserved
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Burst Enable (Enable = 1, Disable = 0, RST = 0)
:Instruction Burst Enable (Enable = 1, Disable = 0, RST = 0)
(6)System Support Control Register (SSCR)
bit→
ASI = 0x01, Address = 0x00000080H
31
8
7
6
5
4
3
2
1
0
Reserved
bit 31 to bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 to bit 0
:Reserved [“0”Write, Don’t care for read]
:DRAM Burst Enable (Enable = 1, Disable = 0, RST = 0)
:DRAM Controller Enable (Enable = 1, Disable = 0, RST = 0)
:Same Page Enable (Enable = 1, Disable = 0, RST = 0)
:CS Enable (Enable = 1, Disable = 0, RST = 0) *
:Programmable Wait-state (Enable = 1, Disable = 0, RST = 1)
:Timer On/Off (Enable = 1, Disable = 0, RST = 0)
:Reserved “0”Write, Don’t care for read]
*:CS0 is always enable.
63
MB86830 Series
ASI = 0x01, Address = 0x00000120H
(7)Same Page Mask Register (SPGMR)
bit→
31 30
23 22
1
ASI<7:0>Mask
bit 31
bit 30 to bit 23
bit 22 to bit 1
bit 0
0
Address<31:10>Mask
:Reserved [“0”Write, Don’t care for read]
:ASI<7:0>Mask (Care = 0, Don’t Care = 1, RST = X)
:Address<31:10>Mask (Care = 0, Don’t Care = 1, RST = X)
:Reserved [“0”Write,Don’t care for read]
X:Don’t care
ASI = 0x01, Address = 0x00000124H to 0x00000134H
(8)Address Range Specifier Register (ARSR)
bit→
31 30
23 22
1
ASI<7:0>
bit 31
bit 30 to bit 23
bit 22 to bit 1
bit 0
0
Address<31:10>
:Reserved [“0”Write, Don’t care for read]
:ASI<7:0>(RST = X) *
:Address<31:10>(RST = X) *
:Reserved [“0”Write, Don’t care for read]
*CS0 is fixed to Address<31: 15>=0,Address<14: 10>=0,ASI<7:0>=0x09.
X:Don’t care
ASI = 0x01, Address = 0x00000140H to 0x00000154H
(9)Address Mask Register (AMR)
bit→
31 30
23 22
1
ASI<7:0>Mask
bit 31
bit 30 to bit 23
bit 22 to bit 1
bit 0
0
Address<31:10>Mask
:Reserved [“0”Write, Don’t care for read]
:ASI<7:0>Mask (CS0:RST = 0, CS1 to CS5:RST = X)
:Address<31:10>Mask (CS0:RST = <31:15> = 0, <14:10> = 0x1f, CS1 to CS5:RST = X)
:Reserved [“0”Write, Don’t care for read]
X:Don’t care
(10)Wait State Specifier Register (WSSR)
bit→
31
27 26
count 1
64
22 21 20 19 18
count 2
bit 31 to bit 27,bit 18 to bit 14
bit 26 to bit 22,bit 13 to bit 9
bit 21,bit 8
bit 20,bit 7
bit 19,bit 6
bit 5,bit 4
bit 3 to bit 0
ASI = 0x01, Address = 0x00000160H to 0x00000168H
14 13
count 1
9
8
7
6
5
count 2
:count 1 (CS0:RST = 0x1f, CS1 to CS5:RST = 0)
:count 2 (CS0:RST = 0x1f, CS1 to CS5:RST = 0)
:Wait Enable (On = 1, Off = 0,CS0:RST = 1, CS1 to CS5:RST = 0)
:Single Cycle Non Burst Mode (On = 1, Off = 0,RST = 0)
:Override (On = 1, Off = 0, CS0 = 1, CS1 to CS5 = 0)
:Single Cycle Burst Mode (On = 1, Off = 0, RST = 0)
:Reserved [“0”Write, Don’t care for read]
4
3
0
MB86830 Series
ASI = 0x01, Address = 0x0000016CH
(11)Bus Width/Cacheable Register (BWCR)
bit→
31
24
Reserved
23 22 21 20 19 18 17 16
CS5
CS4
CS3
CS2
15 14
CS1
bit 31 to bit 24
bit 23,bit 21,bit 19,bit 17,bit 15,bit 13
bit 22,bit 20,bit 18,bit 16,bit 14,bit 12
bit 11 to bit 10,bit 9 to bit 8,bit 7 to bit 6,bit 5 to bit 4,
bit 3 to bit 2
bit 1 to bit 0
CS0
CS5
8
CS4
7
6
CS3
5
4
CS2
3
2 1
0
CS1
:Reserved [“0”Write, Don’t care for read]
:Internal/External Cacheable (0 = External, 1 = Internal)
:Cacheable (0 = cacheable, 1 = noncacheable)
:Bus Width Control bit
:Reserved [“0”Write, Don’t care for read]
ASI = 0x01, Address = 0x00000174H
(12)DRAM Refresh Timer Register (REFTMR)
bit→
13 12 11 10 9
31 30
16 15
Reserved
0
Timer Value
bit 31
:Test Mode [“0“Write, Don’t care for read]
bit 30 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Timer Value (RST = 0xffff)
ASI = 0x01, Address = 0x00000178H
(13)DRAM Refresh Timer Pre-load (DRLD)
bit→
31 30
16 15
Reserved
0
Timer Pre-load Value
bit 31
:3 Cycle Mode (On = 1, Off = 0, RST = 0)
bit 30 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Timer Pre-load Value (RST = 0xffff)
ASI = 0x01, Address = 0x00020000H
(14)Ancillary Version Register (VER2)[Read only]
bit→
31
16 15
Reserved
0
Version
bit 31 to bit 16 :Reserved [Don’t care for read]
bit 15 to bit 0 :Version
(MB86831:Value = 0, MB86832:Value = 1, MB86833:Value = 2, MB86834:Value = 3,
MB86835:Value = 4, MB86836:Value = 1)
ASI = 0x01, Address = 0x00020004H
(15)Sleep Mode Register (SLPMD)[Write only]
bit→
31
1
0
Reserved
bit 31 to bit 1
bit 0
:Reserved
:Sleep Mode (On = 1, Off = 0, RST = 0)
65
MB86830 Series
15. Bit map of register for cash access
(1)Instruction Tag Lock Bit (ICLOCK) [Wite only]
bit→
ASI = 0x02
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H (+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
31
1
0
Reserved
bit 31 to bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
(2)Data Tag Lock Bit (DCLOCK)[Wite only]
bit→
ASI = 0x03
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H (+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
31
1
Reserved
bit 31 to bit 1
bit 0
66
:Reserved [“0”Write, Don’t care for read]
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
0
MB86830 Series
(3)Instruction Cache Tag (ICTAG)
bit→
31
ASI = 0x0c
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H (+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
13 12 11 10
9
6
5
4
2
1
0
2
1
0
Address Tag
bit 31 to bit 13
bit 12
bit 11
bit 10
bit 9 to bit 6
bit 4 to bit 2
bit 5
bit 1
bit 0
:Address Tag (RST = X)
:Capacity 16 KB = <Reserved>, Other = <Address Tag>
:Capacity 16 KB, 8 KB = <Reserved>, Other = <Address Tag>
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Address Tag>
:Sub Block Valid (Valid = 1, Invalid = 0,RST = 0)
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity2 KB, 1 KB = <Reserved> [Don’t care for read]
:User/Supervisor (User = 0, Supervisor = 1, RST = X)
:Capacity1 KB = <Reserved>, Other= LRU (RST = 0) *
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
*:BANK only, BANK 2 is Reserved
X:Don’t care
(4)Instruction Cache Invalidate Register (ICINVLD)[Wite only]
ASI = 0x0c
Capacity 16 KB
Bank 1:Address = 0x00008000H
Bank 2:Address = 0x80008000H
Other
Bank 1:Address = 0x00001000H
Bank 2:Address = 0x80001000H
bit→
31
Reserved
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write]
:Cache LRU, Lock Bit Clear (Clear = 1, Not Clear = 0)
:Valid Bit Clear (Clear = 1, Not Clear = 0)
67
MB86830 Series
(5)Instruction Cache Data RAM (ICDATA)
bit→
ASI = 0x0d
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80001ffcH (+4)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80000ffcH (+4)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007fcH (+4)
Bank 2:Address = 0x80000000H to 0x800007fcH (+4)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003fcH (+4)
Bank 2:Address = 0x80000000H to 0x800003fcH (+4)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003fcH
31
0
Data
bit 31 to bit 0:Data (RST = X)
X:Don’t care
ASI = 0x0e
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H(+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
(6)Data Cache Tag (DCTAG)
bit→
31
13 12 11 10
9
6
5
4
Address Tag
bit 31 to bit 13
bit 12
bit 11
bit 10
bit 9 to bit 6
bit 4 to bit 2
bit 5
bit 1
bit 0
:Address Tag (RST = X)
:Capacity 16 KB = <Reserved>, Other = <Address Tag>
:Capacity 16 KB, 8 KB = <Reserved>, Other = <Address Tag>
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Address Tag>
:Sub Block Valid (Valid = 1, Invalid = 0,RST = 0)
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Reserved>[Don’t care for read]
:User/Supervisor (User = 1, Supervisor = 0, RST = X)
:Capacity 1 KB = <Reserved>, Other = LRU (RST = 0) *
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
*:BANK 1 only, BANK 2 is Reserved
X:Don’t care
68
2
1
0
MB86830 Series
(7)Data Cache Invalidate Register (DCINVLD)[Wite only]
ASI = 0x0e
Capacity 16 KB
Bank 1:Address = 0x00008000H
Bank 2:Address = 0x80008000H
Other
Bank 1:Address = 0x00001000H
Bank 2:Address = 0x80001000H
bit→
31
2
1
0
Reserved
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write]
:Cache LRU, Lock Bit Clear (Clear = 1, Not Clear = 0)
:Valid Bit Clear (Clear = 1, Not Clear = 0)
(8)Data Cache Data RAM(DCDATA)
bit→
ASI = 0x0f
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80001ffcH (+4)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000ffcH (+4)
Bank 2:Address = 0x80000000H to 0x80000ffcH (+4)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007fcH (+4)
Bank 2:Address = 0x80000000H to 0x800007fcH (+4)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003fcH (+4)
Bank 2:Address = 0x80000000H to 0x800003fcH (+4)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003fcH (+4)
31
0
Data
bit 31 to bit 0
:Data (RST = X)
X:Don’t care
69
MB86830 Series
16. Interrupt controller (IRC)
CS3# = L, Address<9:2> = 0x00
(1)Trigger Mode 0 Register (TRGM0)
bit→
31
16
Reserved
15 14 13 12 11 10 9
ch 15
ch 14
ch 13
8 7
ch 12
6 5
ch 11
4
3
ch 10
2
1
ch 9
0
ch 8
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Trigger Mode (High Level = 00, Low Level = 01, High Edge = 10, Low Edge = 11, RST = 00)
CS3# = L, Address<9:2> = 0x01
(2)Trigger Mode 1 Register (TRGM1)
bit→
31
16
Reserved
15 14 13 12 11 10 9
ch 7
ch 6
ch 5
8 7
ch 4
6 5
ch 3
4 3
ch 2
2 1
ch 1
0
00
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2 :Trigger Mode (High Level = 00, Low Level = 01, High Edge = 10, Low Edge = 11, RST = 00)
bit 1 to bit 0
:Reserved [“0”Write, Read“0”]
CS3# = L, Address<9:2> = 0x02
(3)Request Sense Register (REQSNS)[Read only]
bit→
31
16 15
Reserved
1
0
Request Sense 15 to Request Sense 1
0
bit 31 to bit 16 :Reserved [Don’t care for read]
bit 15 to bit 1 :Request Sense 15 to Request Sense 1 (RST = 0)
bit 0
:Reserved [Read“0”]
CS3# = L, Address<9:2> = 0x03
(4)Request Clear Register (REQCLR)[Wite only]
bit→
31
16 15
Reserved
1
Request Clear 15 to Request Clear 1
0
0
bit 31 to bit 16 :Reserved [“0”Write]
bit 15 to bit 1 :Request Clear 15 to Request Clear 1 (Clear = 1, Not Clear = 0)
bit 0
:Reserved [“0”Write]
CS3# = L, Address<9:2> = 0x04
(5)Interrupt Mask Register (IMASK)
bit→
31
16 15
Reserved
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 1 :Mask 15 to Mask 1 (Mask = 1, Not Mask = 0, RST = 1)
bit 0
:IRL Mask (Mask = 1, Not Mask = 0, RST = 0)
70
1
Mask 15 to Mask 1
0
IM
MB86830 Series
CS3# = L, Address<9:2> = 0x05
(6)IRL Latch/Clear Register (IRLAT)
bit→
31
16 15
5
Reserved
bit 31 to bit 16
bit 15 to bit 5
bit 4
bit 3 to bit 0
Reserved
3
CL
0
IRL
:Reserved [“0”Write, Don’t care for read]
:Reserved [“0”Write, Read"0"]
:IRL Clear [Wite only] (Clear = 1, Not Clear = 0)
:IRL Latch [Read only] (RST = 0000)
CS3# = L, Address<9:2> = 0x06
(7)IRC Mode Register (IMODE)
bit→
4
31
16 15
2
Reserved
1
Reserved
0
IRCMD
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2 :Reserved [“0”Write, Read“0”]
bit 1 to bit 0
:IRC Mode [IRCMD] (Disable = 00, Enable = 01, RST = 00)
17. DRAM controller
CS3# = L, Address<9:2> = 0x08
(1)DRAM Bank Configuration Register (DBANKR)
bit→
31
11 10
ERR
bit 31
bit 30 to bit 11
bit 10 to bit 9
bit 8
bit 7
bit 6 to bit 4
bit 3 to bit 0
Reserved
9
8
7
6
STADR HE TP
4
3
0
COL
BKSIZE
:Access Error [ERR] (Error = 1, No Error = 0, RST = X, “0”Write Clear)
:Reserved [“0”Write, Don’t care for read]
:DRAM Start Address [STADR] (RST = 01)
:Hyper Page Enable [HE] (Page Mode DRAM = 0, EDO DRAM = 1, RST = 0)
:DRAM Type[TP] (4CAS-1WE= 0, 4WE -1CAS = 1, RST = 0)
:Column Address [COL] (RST = 011)
:Bank Size [BKSIZE] (RST = 0011)
X:Don’t care
CS3# = L, Address<9:2> = 0x09
(2)DRAM Timing Register (DTIMR)
bit→
31
5
Reserved
bit 31 to bit 5
bit 4
bit 3 to bit 2
bit 1
bit 0
4
TRPS
3
2
TRASCBR
1
0
TCAS
TRP
:Reserved [“0”Write, Don’t care for read]
:RAS#Precharge time specification bits [TRPS] at Self-Refresh (2 Cycle = 0, 4 Cycle = 1, RST = 1)
:RAS#Pulse width specification bit [TRASCBR] at CBR Refresh
(1 Cycle = 00, 2 Cycle = 01, 3 Cycle = 10, RST = 01)
:CAS#Pulse width specification bit [TCAS] (1 Cycle = 0, 2 Cycle = 1, RST = 1)
:RAS#Precharge width specification bit [TRP] (1 Cycle = 0, 2 Cycle = 1, RST = 0)
71
MB86830 Series
18. DSU (Debugging support unit )(MB86832/834)
(1)Instruction Address Descriptor Register (INSTADR)
bit→
ASI = 0x01, Address = 0x0000ff00H to 0x0000ff04H
31
2
Instruction Address Compare Data
bit 31 to bit 2
bit 1 to bit 0
0
Reserved
:Instruction Address Compare Data (RST = 0x00000000H)
:Reserved [“0”Write, Don’t care for read]
ASI = 0x01, Address = 0x0000ff08H to 0x0000ff0cH
(2)Data Address Descriptor Register (DATAADR)
bit→
1
31
0
Data Address Compare Data
bit 31 to bit 0
:Data Address Compare Data (RST = 0x00000000H)
ASI = 0x01, Address = 0x0000ff10H
(3)Data Value Descriptor Register (DVDR)
bit→
31
0
Data Value
bit 31 to bit 0
:Data Value (RST = 0x00000000H)
ASI = 0x01, Address = 0x0000ff14H
(4)Data Value Descriptor Register/Mask Register (DVDMSK)
bit→
31
0
Data/Mask Value
bit 31 to bit 0
:Data/Mask Value (RST = 0x00000000H)
ASI = 0x01, Address = 0x0000ff18H
(5)Debug Control Register (DSUCR)
bit→
31
24
ASI Value2
bit 31 to bit 24
bit 23 to bit 16
bit 15
bit 14
bit 13 to bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3 to bit 2
72
23
16
ASI Value1
15 14 13
9
8
7
6
Reserved
:ASI Value2 (RST = 0x00)
:ASI Value1 (RST = 0x00)
:Instruction User/Supervrisor2 (Supervrisor = 1, User = 0, RST = 0)
:Instruction User/Supervrisor1 (Supervrisor = 1, User = 0, RST = 0)
:Reserved
:Enable Data Address2 Break (Enable = 1, Disable = 0, RST = 0)
:Enable Data Address1 Break (Enable = 1, Disable = 0, RST = 0)
:Enable Instruction Address2 Break (Enable = 1, Disable = 0, RST = 0)
:Enable Instruction Address1 Break (Enable = 1, Disable = 0, RST = 0)
:Single Step (On = 1, Off = 0, RST = 0)
:Data Value Transaction Type (RST = 0x0)
5
4
3
2
1
0
MB86830 Series
bit 3
bit 2
Type
0
0
Break only on Loads
0
1
Break only on Stores
1
0
Break on Load or Store
1
1
Break Always
:Data Value Condition (Outside = 1, Inside = 0, RST = 0)
:Data Value Mask (Mask = 1, Range = 0, RST = 0)
bit 1
bit 0
ASI = 0x01, Address = 0x0000ff1CH
(6)Debug Status Register (DSR)
bit→
31
6
5
4
3
2
1
0
Reserved
bit 31 to bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Address 2 Match (Match = 1, Not Match = 0, RST = 0)
:Data Address 1 Match (Match = 1, Not Match = 0, RST = 0)
:Instruction Address 2 Match (Match = 1, Not Match = 0, RST = 0)
:Instruction Address 1 Match (Match = 1, Not Match = 0, RST = 0)
:EMUENBL [Read only]
:EMUBRK [Read only]
19. Clock gear (Not supported in MB86831-66,80)
CS3# = L, Address<9:2> = 0x0b
Internal Clock Control/Status Register (ICCS)
bit→
31
7
Reserved
bit 31 to bit 7
bit 6 to bit 4
bit 3
bit 2 to bit 0
6
4
CLKST
3
CE
2
0
CLKSEL
:Reserved [“0”Write, Don’t care for read]
:Internal Clock Status [CLKST]
:Internal Clock Change Enable [CE] (Enable = 1, Disable = 0, RST = 0)
:Internal Clock Select [CLKSEL]
CLKST
Internal Clock
100
×1
101
×2
110
×3
111
×4
011
×5
010
001
Reserved
000
73
MB86830 Series
• Register explanation
Internal Clock Control/Status Register (ICCS)
bit→
31
7
6
Reserved
bit 31 to bit 7
bit 6 to bit 4
4
CLKST
3
CE
2
0
CLKSEL
:Reserved [“0”Write, Don’t care for read]
:CLKST (Internal Clock Status)(An initial value is a set point of external terminal CLKSEL2,
CLKSEL1, and CLKSEL0. )
Can know the multiplication rate that CPU works by the bit which shows Internal Clock.
CLKST
Internal Clock
100
×1
101
×2
110
×3
111
×4
011
×5
010
001
bit 3
bit 2 to bit 0
Reserved
000
:CE (Internal Clock Change Enable)(Initial value “0”)
Internal Clock change inable bit.Internal Clock is changed according to the CLKSEL bit according
to this value at sleep mode (low power consumption mode).
1: Internal Clock is changed by the CLKSEL bit.
0: No change Internal Clock.
It is necessary to set “1” in this bit to change Internal Clock before sleep mode (low power consumption mode) is set.
:CLKSEL (Internal Clock Select)
Internal Clock specification bit.
20. General-purpose 16-bit Timer (MB86836)
CS3# = L, Address<9:2> = 0x0c
(1) Prescaler0 (PRS0)
bit→
31
16
Reserved
bit 31 to bit 16
bit 15
bit 14
bit 13 to bit 11
bit 10 to bit 8
bit 7 to bit 0
74
15
14
EX
Test
:Reserved [“0”Write, Don’t care for read]
:External Clock [“0”Write]
Support to only internal clock mode
:Test [“0”Write]
:Reserved [“0”Write, Don’t care for read]
:Select (RST = 000)
:Prescale Value (RST = 01)
13
11 10
Reserved
Select
8
7
0
Prescale Value
MB86830 Series
CS3# = L, Address<9:2> = 0x0d
(2) Timer Control Register (TCR)
bit→
31
16 15 14 13 12 11 10 9
8
7
6
5
3
2
0
Reserved
bit 31 to bit 16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10 to bit 9
bit 8 to bit 7
bit 6
bit 5 to bit 3
bit 2 to bit 0
:Reserved [“0”Write, Don’t care for read]
:Value Of OUT Signal
:Value Of IN Signal
:Reserved [“0”Write, Don’t care for read]
:Test [“0”Write]
:Count Enable (Enable = 1, Disable = 0, RST = 0)
:Clock Select (Internal Clock = 0, Prescaler Clock = 2, Don’t Use = 1 or 3, RST = 0)
:OUT Signal Control (Keep = 0, Set = 1, Reset = 2, Don’t Use = 3)
:Invert (true = 0, Invert = 1, RST = 0)
:Mode Select
:Event Select
CS3# = L, Address<9:2> = 0x0e
(3) Reload Value Register (RVR)
bit→
31
16 15
Reserved
bit 31 to bit 16
bit 15 to bit 0
Reload Value
:Reserved [“0”Write, Don’t care for read]
:Reload Value
CS3# = L, Address<9:2> = 0x0f
(4) Count Value Register (CVR) [Read Only]
bit→
31
16 15
Reserved
bit 31 to bit 16
bit 15 to bit 0
0
0
Count Value
:Reserved [“0”Write, Don’t care for read]
:Count Value
For details on each register, refer to the manual for the MB86942.
21. Notes on Register Setting
(1)Cache/BIU Control Register
• To set Cache Enable or Cache Disable, be sure to insert at least three NOP instructions after the Enable or
Disable instruction.
• The Non-Cacheable bit (bit 9, bit 8) and Cacheability Enable bit (bit 7) cannot be read.
75
MB86830 Series
(2)Bus Control Register
• Enable burst transfer after setting Cache Enable. To set Cache Disable, disable burst transfer in advance.
(3)System Support Control Register
• Set Cache Enable before setting DRAM Burst Enable. To set Cache Disable, disable the DRAM Burst Enable
bit.
• Before setting DRAM Burst Enable, be sure to set Burst Enable using the Bus Control Register.
• The SAMEPAGE# pin may become “L” at the first CS4 access after setting Same Page Enable.
• The Same Page circuit holds previous data even after the bus master is changed.
• Set the Same Page Mask Register before setting Same Page Enable to “1”.
• Before changing the Same Page Enable (bit 5) setting, set Cache Disable.
• Set all of the Address Range Specifier Registers and Address Mask Registers before setting CS Enable to
“1”. (Set all of the Address Range Specifier Registers and Address Mask Registers even if any CS is not to
be used.)
• Before changing the CS Enable (bit 4) setting, set Cache Disable.
• When setting the Programmable Wait-state, be sure to set the Wait State Specifier Register.
(4)Wait State Specifier Register
• Do not set the Wait Enable bit and the Single Cycle Non Burst Mode bit to “1” at the same time.
• If the Single Cycle Non Burst Mode bit is set to “1” in the burst mode, the ready signal is generated in one
cycle regardless of the setting of the Single Cycle Burst Mode bit.
• When setting the CS3 Wait State Specifier Register, be sure to set the Override bit to“1”. (The Wait State bit
can also be set to “1”.)
When the half-word load instruction is executed with CS3 in 16-bit Bus Mode, the CPU accesses twice but
the ready signal from the peripheral resource is generated only once. Therefore the CPU hangs at the second
access. To generate the second ready signal, set the Wait Enable bit to “1” (the CPU discards the data received
at the second access).
(5)Bus Width/Cacheable Register
• In the DRAM Controller Enable state with CS4# = “L”, CS5 is handled as a Non-Cacheable signal.
• In the DRAM Controller Enable state, the CS5 bus width follows the CS4 bus width setting. When the CS4
Bus Width Control bit has been set to (10) 2, for example, the CS5 bus width is forced to be set to (10) 2.
• The CS3 Bus Width can be set only to the 16-bit or 32-bit bus width. When the 16-bit bus width is set, use
Half-Word Load (address “0”) or Half-Word Store (address “0”) to access the interrupt controller (IRC) and
DRAM controller registers.
(6)DRAM Refresh Timer Register
• Be sure to set the Test Mode bit to “0”. Otherwise, TOVF# may not become “L”.
• Since the timer performs counting based on the external clock, it is not affected by the multiplier circuit.
(7)Sleep Mode Register
• To set the sleep mode (low power consumption mode), disable the caches.
• The instruction to set the sleep mode (low power consumption mode) must be followed by at least three NOP
instructions.
(8)Trigger Mode Register
• Set the Interrupt Mask Register to (ffff)16 before changing the Trigger mode.
76
MB86830 Series
• The Request Sense Register may contain “1” when the Trigger Mode is changed. Therefore, issue “Request
Clear” before canceling interrupt masks.
The interrupt controller (IRC) and DRAM controller registers cannot be accessed until CS3# becomes“L”.
(9)Cache Invalidate Register
When the caches are off, write to the Cache Invalidate Register.
(10)Internal Clock Control/Status Register
To change clock multiplication by setting the CE bit in the internal clock control/status register to “1”, input the “L”
pulse to the WKUP# pin at least 4000 CLKIN after entering the sleep mode.
77
MB86830 Series
■ ORDERINGINFORMATION
Part number
78
Package
MB86831PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86831-80PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86832-66PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86832- 80PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86832-100PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86833PMT2
Plastic LQFP 144-pin
(FPT-144P-M08)
MB86834PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86834-120PFV
Plastic QFP 176-pin
(FPT-176P-M01)
MB86835PMT2
Plastic LQFP 144-pin
(FPT-144P-M08)
MB86836PMT2
Plastic LQFP 144-pin
(FPT-144P-M08)
MB86836-108PMT2
Plastic LQFP 144-pin
(FPT-144P-M08)
MB86836PBT
Plastic FBGA 144-pin
(BGA-144P-M02)
MB86836-108PBT
Plastic FBGA 144-pin
(BGA-144P-M02)
Remarks
Under development
Under development
MB86830 Series
■ PACKAGE DIMENSIONS
176-pin plastic QFP
(FPT-176P-M01)
26.60±0.20(1.047±.008)SQ
3.85(.152)MAX
(Mounting height)
24.00±0.10(.945±.004)SQ
132
89
133
88
0(0)MIN
(STAND OFF)
21.50
(.846)
REF
25.60
(1.008)
NOM
Details of "A" part
0.25(.010)
0.20(.008)
0.15(.006)MAX
INDEX
0.40(.016)MAX
176
45
"A"
LEAD No.
1
Details of "B" part
44
0.50(.0197)TYP
0.20±0.10
(.008±.004)
0.08(.003)
M
0.15±0.05
(.006±.002)
0
10°
0.50±0.20(.020±.008)
0.10(.004)
C
"B"
1995 FUJITSU LIMITED F176001S-3C-3
Dimensions inmm (inches)
(Continued)
79
MB86830 Series
(Continued)I
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.30(.866±.012)SQ
1.70(.67)MAX
(Mounting height)
20.00±0.10(.787±.004)SQ
108
0(0)MIN
(STAND OFF)
73
109
72
17.50
(.686)
REF
21.00
(.827)
NOM
Details of "A" part
0.15(.006)
0.15(.006)
INDEX
0.15(.006)MAX
144
37
0.40(.016)MAX
"A"
LEAD No.
1
36
0.50(.0197)TYP
0.20±0.10
(.008±.004)
0.08(.003)
Details of "B" part
M
0.15±0.05
(.006±.002)
0
0.10(.004)
C
10°
0.50±0.20(.020±.008)
"B"
1995 FUJITSU LIMITED F144019S-1C-2
Dimensions inmm (inches)
(Continued)
80
MB86830 Series
(Continued)
144-pin plastic FBGA
(BGA-144P-M02)
12.00±0.10(.472±.004)SQ
+0.20
+.008
1.25 –0.10 .049 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
9.60(.378)REF
0.80(.031)TYP
13
12
11
10
9
8
7
6
5
0.10(.004)
4
3
INDEX
2
1
N M L K J H G F E D C B A
C0.80(.031)
C
144-Ø0.45±0.10
(144-Ø.018±.004)
0.08(.003)
M
1998 FUJITSU LIMITED B144002S-2C-2
Dimensions inmm (inches)
81
MB86830 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
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FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909
 FUJITSU LIMITED Printed in Japan
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
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presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
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standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
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failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
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